pass through downstream compiler directives

src/Convert/Logic.hs

@@ -68,7 +68,6 @@ convertDescription ports orig =
             Part _ _ Module _ _ _ _ -> True
             PackageItem _ -> True
             Package _ _ _ -> False
-            Directive _ -> False
 
         origIdents = execWriter (collectModuleItemsM regIdents orig)
         fixed = traverseModuleItems fixModuleItem orig

src/Convert/NestPI.hs

@@ -100,3 +100,4 @@ piName (Decl (ParamType  _ ident   _)) = Just ident
 piName (Import x y) = Just $ show $ Import x y
 piName (Export    _) = Nothing
 piName (Comment   _) = Nothing
+piName (Directive _) = Nothing

src/Convert/Package.hs

@@ -186,3 +186,4 @@ piName (Decl (ParamType  _ ident   _)) = Just ident
 piName (Import  _ _) = Nothing
 piName (Export    _) = Nothing
 piName (Comment   _) = Nothing
+piName (Directive _) = Nothing

src/Convert/Traverse.hs

@@ -174,7 +174,6 @@ traverseModuleItemsM mapper (Package lifetime name packageItems) = do
             _ -> error $ "redirected Package traverse failed: "
                     ++ show converted
     return $ Package lifetime name $ map (\(MIPackageItem item) -> item) items'
-traverseModuleItemsM _ (Directive str) = return $ Directive str
 
 traverseModuleItems :: Mapper ModuleItem -> Mapper Description
 traverseModuleItems = unmonad traverseModuleItemsM
@@ -623,6 +622,8 @@ traverseExprsM' strat exprMapper = moduleItemMapper
     moduleItemMapper (Generate items) = do
         items' <- mapM (traverseNestedGenItemsM genItemMapper) items
         return $ Generate items'
+    moduleItemMapper (MIPackageItem (Directive c)) =
+        return $ MIPackageItem $ Directive c
     moduleItemMapper (MIPackageItem (Comment c)) =
         return $ MIPackageItem $ Comment c
     moduleItemMapper (MIPackageItem (Import x y)) =

src/Language/SystemVerilog/AST/Description.hs

@@ -28,7 +28,6 @@ data Description
     = Part [Attr] Bool PartKW (Maybe Lifetime) Identifier [Identifier] [ModuleItem]
     | PackageItem PackageItem
     | Package (Maybe Lifetime) Identifier [PackageItem]
-    | Directive String -- currently unused
     deriving Eq
 
 instance Show Description where
@@ -53,7 +52,6 @@ instance Show Description where
         where
             bodyStr = indent $ unlines' $ map show items
     show (PackageItem i) = show i
-    show (Directive str) = str
 
 data PackageItem
     = Typedef Type Identifier
@@ -62,6 +60,7 @@ data PackageItem
     | Import Identifier (Maybe Identifier)
     | Export (Maybe (Identifier, Maybe Identifier))
     | Decl Decl
+    | Directive String
     | Comment String
     deriving Eq
 
@@ -79,6 +78,7 @@ instance Show PackageItem where
     show (Export Nothing) = "export *::*";
     show (Export (Just (x, y))) = printf "export %s::%s;" x (fromMaybe "*" y)
     show (Decl decl) = show decl
+    show (Directive str) = str
     show (Comment c) =
         if elem '\n' c
             then "// " ++ show c

src/Language/SystemVerilog/Parser/Lex.x

@@ -884,6 +884,10 @@ handleDirective (posOrig, _, _, strOrig) len = do
     env <- gets lsEnv
     tempInput <- alexGetInput
     let dropUntilNewline = removeUntil "\n" tempInput 0
+    let passThrough = do
+            rest <- takeUntilNewline
+            let str = '`' : directive ++ rest
+            tok Spe_Directive (posOrig, ' ', [], strOrig) (length str)
 
     condStack <- gets lsCondStack
     if any (/= CurrentlyTrue) condStack
@@ -891,9 +895,18 @@ handleDirective (posOrig, _, _, strOrig) len = do
     then alexMonadScan
     else case directive of
 
-        "default_nettype" -> dropUntilNewline
         "timescale" -> dropUntilNewline
 
+        "celldefine" -> passThrough
+        "endcelldefine" -> passThrough
+
+        "unconnected_drive" -> passThrough
+        "nounconnected_drive" -> passThrough
+
+        "default_nettype" -> passThrough
+        "pragma" -> passThrough
+        "resetall" -> passThrough
+
         "__FILE__" -> do
             tokPos <- toTokPos posOrig
             currFile <- gets lsCurrFile

src/Language/SystemVerilog/Parser/Parse.y

@@ -293,6 +293,7 @@ systemIdentifier   { Token Id_system       _ _ }
 number             { Token Lit_number      _ _ }
 string             { Token Lit_string      _ _ }
 time               { Token Lit_time        _ _ }
+directive          { Token Spe_Directive   _ _ }
 
 "("                { Token Sym_paren_l _ _ }
 ")"                { Token Sym_paren_r _ _ }
@@ -775,6 +776,7 @@ NonDeclPackageItem :: { [PackageItem] }
   | "export" "*" "::" "*" ";"       { [Export Nothing] } -- "Nothing" being no restrictions
   | ForwardTypedef ";"              { $1 }
   | TimeunitsDeclaration            { $1 }
+  | Directive                       { [Directive $1] }
 ForwardTypedef :: { [PackageItem] }
   : "typedef"          Identifier { [] }
   | "typedef" "enum"   Identifier { [] }
@@ -785,6 +787,9 @@ TimeunitsDeclaration :: { [PackageItem] }
   | "timeunit" Time "/" Time ";" { [] }
   | "timeprecision" Time     ";" { [] }
 
+Directive :: { String }
+  : directive { tokenString $1 }
+
 PackageImportItems :: { [(Identifier, Maybe Identifier)] }
   : PackageImportItem                        { [$1] }
   | PackageImportItems "," PackageImportItem { $1 ++ [$3] }

src/Language/SystemVerilog/Parser/Tokens.hs

@@ -378,6 +378,7 @@ data TokenName
     | Sym_amp_amp_amp
     | Sym_lt_lt_lt_eq
     | Sym_gt_gt_gt_eq
+    | Spe_Directive
     | Unknown
     | MacroBoundary
     deriving (Show, Eq)