prefix bare generate blocks with conditionals in codegen

src/Language/SystemVerilog/AST/GenItem.hs

@@ -31,26 +31,31 @@ data GenItem
 instance Show GenItem where
     showList i _ = unlines' $ map show i
     show (GenBlock x i) =
-        printf "begin%s\n%s\nend"
-            (if null x then "" else " : " ++ x)
-            (indent $ show i)
+        "if (1) " ++ showBareBlock (GenBlock x i)
     show (GenCase e cs) =
         printf "case (%s)\n%s\nendcase" (show e) bodyStr
         where bodyStr = indent $ unlines' $ map showGenCase cs
-    show (GenIf e a GenNull) = printf "if (%s) %s"          (show e) (show a)
-    show (GenIf e a b      ) = printf "if (%s) %s\nelse %s" (show e) (showBlockedBranch a) (show b)
+    show (GenIf e a GenNull) = printf "if (%s) %s"          (show e) (showBareBlock a)
+    show (GenIf e a b      ) = printf "if (%s) %s\nelse %s" (show e) (showBlockedBranch a) (showBareBlock b)
     show (GenFor (x1, e1) c (x2, o2, e2) s) =
         printf "for (%s = %s; %s; %s %s %s) %s"
             x1 (show e1)
             (show c)
             x2 (show o2) (show e2)
-            (if s == GenNull then "begin end" else show s)
+            (if s == GenNull then "begin end" else showBareBlock s)
     show (GenNull) = ";"
     show (GenModuleItem item) = show item
 
+showBareBlock :: GenItem -> String
+showBareBlock (GenBlock x i) =
+    printf "begin%s\n%s\nend"
+        (if null x then "" else " : " ++ x)
+        (indent $ show i)
+showBareBlock item = show item
+
 showBlockedBranch :: GenItem -> String
 showBlockedBranch genItem =
-    show $
+    showBareBlock $
     if isControl genItem
         then GenBlock "" [genItem]
         else genItem
@@ -65,5 +70,5 @@ showBlockedBranch genItem =
 type GenCase = ([Expr], GenItem)
 
 showGenCase :: GenCase -> String
-showGenCase (a, b) = printf "%s: %s" exprStr (show b)
+showGenCase (a, b) = printf "%s: %s" exprStr (showBareBlock b)
     where exprStr = if null a then "default" else commas $ map show a

test/basic/array.v

@@ -11,7 +11,7 @@ module top;
     assign c = x ? d : e;
 
     generate
-        begin : A
+        if (1) begin : A
             wire [1:0] c [0:2];
             wire [5:0] d;
         end

test/basic/cast.v

 module top;
 
     generate
-        begin : A
+        if (1) begin : A
             reg signed [31:0] x;
         end
     endgenerate

test/basic/decl_scope.v

@@ -3,13 +3,13 @@ module top;
     initial $display("A t %0d", 1);
     initial $display("A top.t %0d", 1);
     generate
-        begin : X
+        if (1) begin : X
             wire [1:0] t;
             initial $display("B t %0d", 2);
             initial $display("B top.t %0d", 1);
             initial $display("B X.t %0d", 2);
             initial $display("B top.X.t %0d", 2);
-            begin : Y
+            if (1) begin : Y
                 wire [2:0] t;
                 initial $display("C t %0d", 3);
                 initial $display("C top.t %0d", 1);
@@ -46,7 +46,7 @@ module top;
 
     wire [11:0] arr;
     generate
-        begin : M
+        if (1) begin : M
             wire [19:0] arr;
             initial $display("M arr[0] = %b", arr[4:0]);
             initial $display("M M.arr[0] = %b", M.arr[4:0]);

test/basic/interface_generate.v

@@ -33,7 +33,7 @@ module top;
 
 
     generate
-        begin : intf
+        if (1) begin : intf
             wire [N-1:0] req;
         end
         genvar j;

test/basic/interface_infer.v

@@ -2,7 +2,7 @@ module top;
     genvar g;
     localparam SOME_VAL = 3;
     generate
-        begin : i
+        if (1) begin : i
             wire x = 0;
             initial $display("Interface %d %d", x, SOME_VAL);
             for (g = 10; g < 15; g = g + 1) begin
@@ -11,7 +11,7 @@ module top;
         end
     endgenerate
     generate
-        begin : m
+        if (1) begin : m
             initial $display("Module %d", i.x);
             for (g = 0; g < 5; g = g + 1) begin
                 initial $display(g);

test/basic/interface_nested.v

 module top;
     wire x = 1;
     generate
-        begin : f
+        if (1) begin : f
             wire x;
-            begin : a
+            if (1) begin : a
                 wire x;
                 initial begin
                     $display("bar got %b", x);
                 end
             end
             assign a.x = x;
-            begin : b
+            if (1) begin : b
                 wire x;
                 initial begin
                     $display("bar got %b", x);

test/basic/interface_param.v

@@ -13,10 +13,10 @@ endmodule
 
 module top;
     generate
-        begin : x
+        if (1) begin : x
             wire [31:0] data = 0;
         end
-        begin : y
+        if (1) begin : y
             wire [9:0] data = 0;
         end
     endgenerate

test/basic/interface_shadow.v

 module top;
     generate
-        begin : x
+        if (1) begin : x
             integer x;
             function z;
                 input x;
@@ -10,7 +10,7 @@ module top;
     endgenerate
     initial x.x = 1;
     generate
-        begin : y
+        if (1) begin : y
             function z;
                 input x;
                 z = x;

test/basic/interface_struct.v

 module top;
     generate
-        begin : i
+        if (1) begin : i
             wire [3:0] x;
             reg [1:0] w;
         end

test/basic/logic_tf.v

@@ -19,12 +19,12 @@ module top;
     end
 
     generate
-        begin : A
+        if (1) begin : A
             wire x;
-            begin : B
+            if (1) begin : B
                 reg x;
             end
-            begin : C
+            if (1) begin : C
                 wire x;
             end
             assign x = B.x ^ C.x;

test/basic/stmt_task.sv

@@ -3,7 +3,7 @@ module top;
         $display("tick() called");
     endtask
     generate
-        begin : foo
+        if (1) begin : foo
             task tick;
                 $display("foo.tick() called");
             endtask

test/basic/struct_scope.v

@@ -4,7 +4,7 @@ module top;
     wire [17:0] c;
 
     generate
-        begin : foo
+        if (1) begin : foo
             wire [2:0] a;
             wire [14:0] b;
             wire [17:0] c;

test/lib/functions.sh

@@ -21,7 +21,6 @@ simulate() {
     iv_output=`iverilog \
         -Wall \
         -Wno-select-range \
-        -Wno-anachronisms \
         -Wno-portbind \
         -o $sim_prog \
         -g2005 \