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lvzhengyang
sv2v
Commits
0f822402
Commit
0f822402
authored
Jun 24, 2023
by
Zachary Snow
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test runner simplifications
parent
a2956445
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4 changed files
with
19 additions
and
17 deletions
+19
-17
test/lib/functions.sh
+13
-11
test/lib/tb_dumper.v
+1
-1
test/search/run.sh
+1
-1
test/truncate/run.sh
+4
-4
No files found.
test/lib/functions.sh
View file @
0f822402
...
...
@@ -3,13 +3,12 @@
SCRIPT_DIR
=
`
dirname
"
${
BASH_SOURCE
[0]
}
"
`
SV2V
=
"
$SCRIPT_DIR
/../../bin/sv2v +RTS -N1 -RTS"
# USAGE: simulate <vcd-file> <log-file> <
top-module> <
file> [<file> ...]
# USAGE: simulate <vcd-file> <log-file> <file> [<file> ...]
simulate
()
{
# arguments
sim_vcd
=
$1
sim_log
=
$2
sim_top
=
$3
shift
3
shift
2
# compile the files
sim_vcd_tmp
=
$SHUNIT_TMPDIR
/simvcdtmp
sim_prog
=
$SHUNIT_TMPDIR
/simprog.exe
...
...
@@ -19,8 +18,7 @@ simulate() {
-o
$sim_prog
\
-g2005
\
-gstrict-expr-width
\
-DTEST_VCD
=
"
\"
$sim_vcd_tmp
\"
"
\
-DTEST_TOP
=
$sim_top
\
-DTEST_VCD
=
\"
$sim_vcd_tmp
\"
\
"
$@
"
\
$SCRIPT_DIR
/tb_dumper.v
\
2>&1
`
...
...
@@ -33,10 +31,14 @@ simulate() {
assertNotNull
"iverilog on
$1
did not emit any warnings"
"
$iv_output
"
fi
# run the simulation
$sim_prog
>
$sim_log
$sim_prog
-no-date
>
$sim_log
assertTrue
"simulating
$1
failed"
$?
# remove the date from the VCD
sed
-e
"1,3d"
<
$sim_vcd_tmp
|
$SCRIPT_DIR
/clean_vcd.py
>
$sim_vcd
# remove parameters from the VCD if present
if
grep
"var parameter"
$sim_vcd_tmp
>
/dev/null
;
then
$SCRIPT_DIR
/clean_vcd.py <
$sim_vcd_tmp
>
$sim_vcd
elif
[
$sim_vcd
!=
"/dev/null"
]
;
then
mv
-f
$sim_vcd_tmp
$sim_vcd
fi
}
assertConverts
()
{
...
...
@@ -167,9 +169,9 @@ simulateAndCompare() {
cvv_log
=
$SHUNIT_TMPDIR
/cvv.log
# simulate the three files
simulate
$ref_vcd
$ref_log
top
$ve
$tb
simulate
$cvs_vcd
$cvs_log
top
$cs
$tb
simulate
$cvv_vcd
$cvv_log
top
$cv
$tb
simulate
$ref_vcd
$ref_log
$ve
$tb
simulate
$cvs_vcd
$cvs_log
$cs
$tb
simulate
$cvv_vcd
$cvv_log
$cv
$tb
# compare reference verilog to converted succinct
output
=
`
diff
$ref_vcd
$cvs_vcd
`
...
...
test/lib/tb_dumper.v
View file @
0f822402
module
sv2v_dumper
;
initial
begin
$
dumpfile
(
`TEST_VCD
)
;
$
dumpvars
(
1
,
`TEST_TOP
)
;
$
dumpvars
(
1
,
top
)
;
end
endmodule
test/search/run.sh
View file @
0f822402
...
...
@@ -4,7 +4,7 @@ evaluate() {
design_v
=
$SHUNIT_TMPDIR
/search_design.v
output_log
=
$SHUNIT_TMPDIR
/search.log
touch
$output_log
simulate /dev/null
$output_log
top
<
(
echo
"
$1
"
)
/dev/null
simulate /dev/null
$output_log
<
(
echo
"
$1
"
)
/dev/null
tail
-n1
$output_log
}
...
...
test/truncate/run.sh
View file @
0f822402
...
...
@@ -32,8 +32,8 @@ testNumber() {
# simulate and compare in strict mode
EXPECT_IVERILOG_WARNINGS
=
`
[
$mode
=
trunc_ivl_warns
]
;
echo
$?
`
\
simulate /dev/null
$ve_log
top
$ve
simulate /dev/null
$cs_log
top
$cs
simulate /dev/null
$ve_log
$ve
simulate /dev/null
$cs_log
$cs
output
=
`
diff
$ve_log
$cs_log
`
assertTrue
"number literals differ:
\n
$output
"
$?
...
...
@@ -56,8 +56,8 @@ testNumber() {
# simulate and compare in lax mode
EXPECT_IVERILOG_WARNINGS
=
`
[[
"
$number
"
=
~ .
\'
]]
&&
[
$mode
=
trunc_ivl_warns
]
;
echo
$?
`
\
simulate /dev/null
$ve_log
top
-gno-strict-expr-width
$ve
simulate /dev/null
$cs_log
top
-gno-strict-expr-width
$cs
simulate /dev/null
$ve_log
-gno-strict-expr-width
$ve
simulate /dev/null
$cs_log
-gno-strict-expr-width
$cs
output
=
`
diff
$ve_log
$cs_log
`
assertTrue
"number literals differ:
\n
$output
"
$?
}
...
...
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