fixed off by 1 in logic conversion

04983b0c · Zachary Snow · 7734fa53 · 04983b0c
Commit 04983b0c authored Apr 23, 2019 by Zachary Snow
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src/Convert/Logic.hs
+1 -1

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--- a/src/Convert/Logic.hs
+++ b/src/Convert/Logic.hs
@@ -97,7 +97,7 @@ convertDescription ports orig =
                            collectNestedExprsM exprIdents expr
                        tmp = "sv2v_tmp_" ++ instanceName ++ "_" ++ portName
                        tmpExpr = Ident tmp
-                        t = Net TWire [(Bits $ Right expr, Number "0")]
+                        t = Net TWire [(Bits $ Right expr, Number "1")]
                        items =
                            [ MIDecl $ Variable Local t tmp [] Nothing
                            , AlwaysC AlwaysComb $ AsgnBlk AsgnOpEq lhs tmpExpr]