;;- Machine description for GNU compiler, MIL-STD-1750A version.
;;  Copyright (C) 1994 Free Software Foundation, Inc.
;;  Contributed by O.M.Kellogg, Deutsche Aerospace (okellogg@salyko.cube.net).

;; This file is part of GNU CC.

;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 1, or (at your option)
;; any later version.

;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.


;;- instruction definitions

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;;- When naming insn's (operand 0 of define_insn) be careful about using
;;- names from other targets machine descriptions.

;; MIL-STD-1750 specific remarks:
;;
;; 1) BITS_PER_UNIT = 16
;;
;; 2) GCC   to    MIL-STD-1750       data type mappings:
;;    QImode => single integer (16 bits or 1 reg).
;;    HImode => double integer (32 bits or 2 regs).
;;    HFmode => single precision float (32 bits or 2 regs).
;;    TQFmode => extended precision float (48 bits or 3 regs).
;; 
;; 3) Immediate integer operands Constraints:
;;    'I'  1 .. 16
;;    'J' -1 ..-16
;;    'K'  0 .. 15
;;    'L'  0 .. 255
;;    'M' -32768 .. 32767
;;    'O' => 0  (for optimizations and GCC quirks)
;;
;; Further notes:
;;-  Assembly output ending in ".M" are macros in file M1750.INC


;; stackpush
(define_insn ""
  [(set (match_operand:QI 0 "push_operand" "=<")
        (match_operand:QI 1 "general_operand" "r"))]
  ""
  "PSHM   R%1,R%1")

(define_insn ""
  [(set (match_operand:HI 0 "push_operand" "=<")
        (match_operand:HI 1 "general_operand" "r"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[1];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
   } ")

(define_insn ""
  [(set (match_operand:HF 0 "push_operand" "=<")
        (match_operand:HF 1 "general_operand" "r"))]
  ""
  "*
  { 
        rtx new_operands[2];
        new_operands[0] = operands[1];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
        output_asm_insn(\"PSHM   R%0,R%1\",new_operands);
        return \"\;\";
   } ")

(define_insn ""
  [(set (match_operand:TQF 0 "push_operand" "=<")
        (match_operand:TQF 1 "general_operand" "r"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[1];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2);
        output_asm_insn(\"PSHM   R%0,R%1\",new_operands);
        return \"\;\";
   } ")

;; stackpop
(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=r")
        (match_operand:QI 1 "push_operand" ">"))]
  ""
  "POPM   R%1,R%1")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=r")
        (match_operand:HI 1 "push_operand" ">"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[0];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
        output_asm_insn(\"POPM   R%0,R%1\",new_operands);
        return \"\;\";
   } ")

(define_insn ""
  [(set (match_operand:HF 0 "general_operand" "=r")
        (match_operand:HF 1 "push_operand" ">"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[0];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
        output_asm_insn(\"POPM   R%0,R%1\",new_operands);
        return \"\;\";
   } ")

(define_insn ""
  [(set (match_operand:TQF 0 "general_operand" "=r")
        (match_operand:TQF 1 "push_operand" ">"))]
  ""
  "*
   { 
        rtx new_operands[2];
        new_operands[0] = operands[0];
        new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2);
        output_asm_insn(\"POPM   R%0,R%1\",new_operands);
        return \"\;\";
   } ")

;; Test operations. These shouldn't really occur for 1750:
;; all important instructions set the cc's (see NOTICE_UPDATE_CC)

(define_insn "tstqi"
  [(set (cc0)
        (match_operand:QI 0 "register_operand" "r"))]
  ""
  "LR     R%0,R%0   ; from tstqi")

(define_insn "tsthi"
  [(set (cc0)
        (match_operand:HI 0 "register_operand" "r"))]
  ""
  "DLR    R%0,R%0   ; from tsthi")

(define_insn "tsthf"
  [(set (cc0)
        (match_operand:HF 0 "register_operand" "r"))]
  ""
  "DLR    R%0,R%0   ; from tsthf")

;; This one is happy with "roughly zero" :-)  (should be improved)
(define_insn "tsttqf"
  [(set (cc0)
        (match_operand:TQF 0 "register_operand" "r"))]
  ""
  "DLR    R%0,R%0   ; from tsttqf")


;; block move.

; there is a problem with this insn in gcc-2.2.3
; (clobber (match_dup 2)) does not prevent use of this operand later
;
(define_insn "movstrqi"
  [(set (mem:BLK (match_operand:QI 0 "register_operand" "r"))
	(mem:BLK (match_operand:QI 1 "register_operand" "r")))
   (use (match_operand:QI 2 "register_operand" "r"))
   (use (match_operand:QI 3 "immediate_operand" ""))
   (clobber (match_dup 0))
   (clobber (match_dup 1))
   (clobber (match_dup 2))]
  ""
  "* return (char *)movcnt_regno_adjust(operands); ")


;; compare instructions.

(define_insn "cmpqi"
  [(set (cc0)
        (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
                 (match_operand:QI 1 "general_operand"  "I,J,i,r,m")))]
  ""
  "@
     CISP   R%0,%1
     CISN   R%0,%J1
     CIM    R%0,%1
     CR     R%0,R%1
     C      R%0,%1 ")

(define_insn "cmphi"
  [(set (cc0)
        (compare (match_operand:HI 0 "general_operand" "r,r")
                 (match_operand:HI 1 "general_operand" "r,m")))]
  ""
  "@
    DCR    R%0,R%1
    DC     R%0,%1 ")

(define_insn "cmphf"
 [(set (cc0)
       (compare (match_operand:HF 0 "general_operand" "r,r")
                (match_operand:HF 1 "general_operand" "r,m")))]
 ""
 "@
   FCR    R%0,R%1
   FC     R%0,%1 ")

(define_insn "cmptqf"
  [(set (cc0)
        (compare (match_operand:TQF 0 "general_operand" "r,r")
                 (match_operand:TQF 1 "general_operand" "r,m")))]
  ""
  "@
    EFCR   R%0,R%1
    EFC    R%0,%1 ")


;; truncation instructions
;;- 1750: any needed?

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (truncate:QI
         (match_operand:HI 1 "register_operand" "r")))]
  ""
  "*
     {
        REGNO(operands[1]) += 1;
        return \"LR     R%0,R%1  ;trunchiqi2\";
     } ")

;; zero extension instructions

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
        (zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))]
  ""
  "*
      {
        output_asm_insn(\"XORR   R%0,R%0   ;zero_extendqihi2\",operands);
        REGNO(operands[0]) += 1;
        switch (which_alternative)
          {
            case 0:
              return \"LR     R%0,R%1\";
            case 1:
              return \"L      R%0,%1\";
            case 2:
              return \"LIM    R%0,%1\";
          }
      } ")

;; sign extension instructions

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
        (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )]
  ""
  "@
    LR     R%0,R%1 ;extendqihi2\;DSRA   R%0,16
    L      R%0,%1  ;extendqihi2\;DSRA   R%0,16
    LIM    R%0,%1  ;extendqihi2\;DSRA   R%0,16 ")


;; Conversions between float and double.

; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
(define_insn "extendhftqf2"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (float_extend:TQF
         (match_operand:HF 1 "general_operand" "r,m")))]
  ""
  "*
      {
        REGNO(operands[0]) += 2;
        output_asm_insn(\"XORR   R%0,R%0   ;extendhftqf2\",operands);
        REGNO(operands[0]) -= 2;
        if (which_alternative == 0)
          return \"DLR    R%0,R%1\";
        else
          return \"DL     R%0,%1\";
      } ")

; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
(define_insn "trunctqfhf2"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (float_truncate:HF
          (match_operand:TQF 1 "general_operand" "r,m")))]
  ""
  "@
     DLR    R%0,R%1  ;trunctqfhf2
     DL     R%0,%1   ;trunctqfhf2 ")


;; Conversion between fixed point and floating point.

(define_insn "floatqihf2"
  [(set           (match_operand:HF 0 "register_operand" "=r")
        (float:HF (match_operand:QI 1 "register_operand" "r")))]
  ""
  "FLT    R%0,R%1")

(define_insn "floathitqf2"
  [(set           (match_operand:TQF 0 "register_operand" "=r")
        (float:TQF (match_operand:HI 1 "register_operand" "r")))]
  ""
  "EFLT   R%0,R%1")


;; Convert floats to ints

(define_insn "fix_trunchfqi2"
  [(set                 (match_operand:QI 0 "register_operand" "=r")
        (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
  ""
  "FIX    R%0,R%1")

(define_insn "fix_trunctqfhi2"
  [(set                 (match_operand:HI 0 "register_operand" "=r")
        (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
  ""
  "EFIX   R%0,R%1")


;; Move instructions

;; We can't deal with normal byte-size characters, only with WIDE characters!
;; This may appear as a serious restriction, but it also opens the doors
;; for ISO 10646  :-)

;; 16-bit moves

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,r,m,m")
        (match_operand:QI 1 "general_operand"  "O,I,J,M,i,r,m,r,K"))]
  ""
  "@
     XORR   R%0,R%0
     LISP   R%0,%1
     LISN   R%0,%J1
     LIM    R%0,%1  ; 'M' constraint
     LIM    R%0,%1  ; 'i' constraint
     LR     R%0,R%1
     L      R%0,%1
     ST     R%1,%0
     STC    %1,%0   ")

;; 32-bit moves

;; Set HIreg to constant
(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
        (match_operand    1 "immediate_operand" "i"))]
  ""
  "*
    if (GET_CODE(operands[1]) == CONST_INT)
      {
        int val = INTVAL(operands[1]);
        if (val >= 0)
          {
            if (val <= 65535)
              {
                output_asm_insn(\"XORR   R%0,R%0 ;movhi cst->reg\",operands);
                operands[0] = gen_rtx(REG,QImode,REGNO(operands[0]) + 1);
                if (val == 0)
                  return \"XORR   R%0,R%0\";
                else if (val <= 16)
                  return \"LISP   R%0,%1\";
                else
                  return \"LIM    R%0,%1\";
              }
          }
        else if (val >= -16)
          return \"LISN   R%0,%J1\;DSRA   R%0,16 ;movhi cst\";
        INTVAL(operands[1]) >>= 16;
        output_asm_insn(\"LIM    R%0,%1 ;movhi cst->reg\",operands);
        REGNO(operands[0]) += 1;
        INTVAL(operands[1]) = val & 0xFFFF;
        return \"LIM    R%0,%1\";
      }
    return \"LIM    R%0,%1\;DSRA   R%0,16 ;movhi cst\";
  ")

(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=r,r,m")
        (match_operand:HI 1 "general_operand"  "r,m,r"))]
  ""
  "@
    DLR    R%0,R%1
    DL     R%0,%1
    DST    R%1,%0 ")


;; Single-Float moves are *same* as HImode moves:

(define_insn "movhf"
  [(set (match_operand:HF 0 "general_operand" "=r,r,r,r,m")
        (match_operand:HF 1 "general_operand"  "G,F,r,m,r"))]
  ""
  "@
    DXRR.M %0,%0 ; movhf const(0.0)
    %E1\;DL     R%0,%F1
    DLR    R%0,R%1
    DL     R%0,%1
    DST    R%1,%0 ")


;; Longfloat moves

(define_insn "movtqf"
  [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
        (match_operand:TQF 1 "general_operand"  "F,r,m,r"))]
  ""
  "@
    %D1\;EFL    R%0,%F1
    EFLR.M %0,%1
    EFL    R%0,%1
    EFST   R%1,%0 ")


;; add instructions 

;; single integer

;; Use "LIM Ra,sym,Rb" for adding a symbol value to a register and
;; transferring the result to a different register.
;(define_insn ""
;  [(set (match_operand:QI 0 "register_operand" "=r")
;        (plus:QI (match_operand:QI 1 "register_operand" "b")
;                 (match_operand:QI 2 "immediate_operand"  "i")))]
;   "REGNO(operands[0]) != REGNO(operands[1])"
;   "LIM    R%0,%2,R%1 ;md special addqi")

(define_insn "addqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
        (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
                 (match_operand:QI 2 "general_operand"  "I,J,i,r,m,I,J")))]
  ""
  "*
    switch (which_alternative)
      {
        case 0:
          return \"AISP   R%0,%2\";
        case 1:
          return \"SISP   R%0,%J2\";
        case 2:
          if (INTVAL(operands[2]) < 0)
            return \"SIM    R%0,%J2\";
          else
            return \"AIM    R%0,%2\";
        case 3:
          return \"AR     R%0,R%2\";
        case 4:
          return \"A      R%0,%2\";
        case 5:
          return \"INCM   %2,%0\";
        case 6:
          return \"DECM   %J2,%0\";
      } ")

;; double integer
(define_insn "addhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
                 (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    DAR    R%0,R%2
    DA     R%0,%2 ")

(define_insn "addhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
                 (match_operand:HF 2 "general_operand" "m,r")))]
  ""
  "@
    FA     R%0,%2
    FAR    R%0,R%2 ")

(define_insn "addtqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
                 (match_operand:TQF 2 "general_operand" "m,r")))]
  ""
  "@
    EFA    R%0,%2
    EFAR   R%0,R%2 ")


;; subtract instructions

;; single integer
(define_insn "subqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
        (minus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0")
                  (match_operand:QI 2 "general_operand"  "I,i,r,m,I")))]
  ""
  "@
    SISP   R%0,%2
    SIM    R%0,%2
    SR     R%0,R%2
    S      R%0,%2
    DECM   %2,%0 ")

;; double integer
(define_insn "subhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (minus:HI (match_operand:HI 1 "register_operand" "0,0")
                  (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    DSR    R%0,R%2
    DS     R%0,%2 ")

(define_insn "subhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (minus:HF (match_operand:HF 1 "register_operand" "0,0")
                  (match_operand:HF 2 "general_operand" "r,m")))]
  ""
  "@
    FSR    R%0,R%2
    FS     R%0,%2 ")

(define_insn "subtqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
                  (match_operand:TQF 2 "general_operand" "r,m")))]
  ""
  "@
    EFSR   R%0,R%2
    EFS    R%0,%2 ")


;; multiply instructions

(define_insn "mulqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
        (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
                 (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))]
  ""
  "@
     MISP   R%0,%2
     MISN   R%0,%J2
     MSIM   R%0,%2
     MSR    R%0,R%2
     MS     R%0,%2  ")


; 32-bit product
(define_insn "mulqihi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
        (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0")
                 (match_operand:QI 2 "general_operand" "M,r,m")))]
  ""
  "@
    MIM    R%0,%1
    MR     R%0,R%2
    M      R%0,%2 ")

(define_insn "mulhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
                 (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    DMR    R%0,R%2
    DM     R%0,%2 ")

; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)

(define_insn "mulhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
                 (match_operand:HF 2 "general_operand" "r,m")))]
  ""
  "@
    FMR    R%0,R%2
    FM     R%0,%2 ")

(define_insn "multqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
                 (match_operand:TQF 2 "general_operand" "r,m")))]
  ""
  "@
    EFMR   R%0,R%2
    EFM    R%0,%2 ")


;; divide instructions
;; The 1750 16bit integer division instructions deliver a 16-bit
;; quotient and a 16-bit remainder, where the remainder is in the next higher
;; register number above the quotient. For now, we haven't found a way
;; to give the reload pass knowledge of this property. So we make do with
;; whatever registers the allocator wants, and willy-nilly output a pair of
;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
;; A comment in the description of `divmodM4' suggests that one leave the divM3
;; undefined when there is a divmodM4 available.

(define_insn "divmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
        (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
                (match_operand:QI 2 "general_operand"  "I,J,M,r,m")))
   (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
        (mod:QI (match_dup 1) (match_dup 2)))]
  ""
  "*
   {
     char *istr;
     switch(which_alternative)
       {
       case 0:
         istr = \"DISP\";
         break;
       case 1:
         INTVAL(operands[2]) = - INTVAL(operands[2]); /* to be corrected */
         istr = \"DISN\";
         break;
       case 2:
         istr = \"DVIM\";
         break;
       case 3:
         istr = \"DVR \";
         break;
       case 4:
         istr = \"DV  \";
         break;
      }
      return (char *)mod_regno_adjust(istr,operands);
     }")

;; Division for other types is straightforward.

(define_insn "divhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (div:HI (match_operand:HI 1 "register_operand" "0,0")
                (match_operand:HI 2 "general_operand" "r,m")))]
  ""
  "@
    DDR    R%0,R%2
    DD     R%0,%2 ")

(define_insn "divhf3"
  [(set (match_operand:HF 0 "register_operand" "=r,r")
        (div:HF (match_operand:HF 1 "register_operand" "0,0")
                (match_operand:HF 2 "general_operand" "r,m")))]
  ""
  "@
    FDR    R%0,R%2
    FD     R%0,%2 ")

(define_insn "divtqf3"
  [(set (match_operand:TQF 0 "register_operand" "=r,r")
        (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
                (match_operand:TQF 2 "general_operand" "r,m")))]
  ""
  "@
    EFDR   R%0,R%2
    EFD    R%0,%2 ")


;; Other arithmetic instructions:

;; Absolute value

(define_insn "absqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (abs:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "ABS    R%0,R%1")

(define_insn "abshi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (abs:HI (match_operand:HI 1 "register_operand" "r")))]
  ""
  "DABS   R%0,R%1")

(define_insn "abshf2"
  [(set (match_operand:HF 0 "register_operand" "=r")
        (abs:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "FABS   R%0,R%1")


;; Negation

(define_insn "negqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (neg:QI (match_operand:QI 1 "register_operand" "r")))]
  ""
  "NEG    R%0,R%1")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (neg:HI (match_operand:HI 1 "register_operand" "r")))]
  ""
  "DNEG   R%0,R%1")

(define_insn "neghf2"
  [(set (match_operand:HF 0 "register_operand" "=r")
        (neg:HF (match_operand:HF 1 "register_operand" "r")))]
  ""
  "FNEG   R%0,R%1")

; The 1750A does not have an extended float negate instruction, so simulate.
;(define_expand "negtqf2"
;  [(set (match_operand:TQF 0 "register_operand" "=&r")
;        (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
;  ""
;  "
;   emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
;   emit_insn(gen_rtx(SET,VOIDmode,operands[0],
;             gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
;   DONE;
;  ")


;; bit-logical instructions

;; AND

(define_insn "andqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r")
        (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
                (match_operand:QI 2 "general_operand" "M,r,m")))]
  ""
  "@
    ANDM   R%0,%2
    ANDR   R%0,R%2
    AND    R%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "andhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (and:HI (match_operand:HI 1 "register_operand" "%0")
                (match_operand:HI 2 "register_operand" "r")))]
  ""
  "DANR.M %0,%2")

;; OR

(define_insn "iorqi3"
  [(set (match_operand:QI 0 "general_operand" "=r,r,r")
        (ior:QI  (match_operand:QI 1 "general_operand" "%0,0,0")
                (match_operand:QI 2 "general_operand" "M,r,m")))]
  ""
  "@
    ORIM   R%0,%2
    ORR    R%0,R%2
    OR     R%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "iorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (ior:HI (match_operand:HI 1 "register_operand" "%0")
                (match_operand:HI 2 "register_operand" "r")))]
  ""
  "DORR.M %0,%2")

;; XOR

(define_insn "xorqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
        (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
                (match_operand:QI 2 "general_operand"  "M,r,m")))]
  ""
  "@
    XORM   R%0,%2
    XORR   R%0,R%2
    XOR    R%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (xor:HI (match_operand:HI 1 "register_operand" "%0")
                (match_operand:HI 2 "register_operand" "r")))]
  ""
  "DXRR.M %0,%2")

;; NAND

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
	(ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
		(not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
  ""
  "@
    NIM    R%0,%2
    NR     R%0,R%2
    N      R%0,%2 ")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
		(not:HI (match_operand:HI 2 "register_operand" "r"))))]
  ""
  "DNR.M  %0,%2")

;; NOT

(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
        (not:QI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "NR     R%0,R%0")

; This sets incorrect condition codes. See notice_update_cc()
(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (not:HI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "DNR.M  %0,%0")


;; Shift instructions

; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
(define_insn "ashlqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r,r")
        (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0")
                   (match_operand:QI 2 "general_operand" "O,I,r")))]
  ""
  "@
    ; optimized away an SLL R%0,0
    SLL    R%0,%2
    SLR    R%0,R%2 ")

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
                   (match_operand:QI 2 "general_operand" "L,r")))]
  ""                        ; the 'L' constraint is a slight imprecise...
  "@
     DSLL   R%0,%2
     DSLR   R%0,R%2 ")

(define_insn "lshrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
                     (match_operand:QI 2 "general_operand" "I,r")))]
  ""
  "@
    SRL    R%0,%2
    NEG    R%2,R%2\;SLR    R%0,R%2 ")

(define_insn "lshrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
                     (match_operand:QI 2 "general_operand" "L,r")))]
  ""                        ; the 'L' constraint is a slight imprecise...
  "@
    DSRL   R%0,%2
    NEG    R%2,R%2\;DSLR   R%0,R%2 ")

(define_insn "ashrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
                     (match_operand:QI 2 "general_operand" "I,r")))]
  ""
  "@
     SRA    R%0,%2
     NEG    R%2,R%2\;SAR    R%0,R%2 ")

(define_insn "ashrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
                     (match_operand:QI 2 "general_operand" "I,r")))]
  ""
  "@
     DSRA   R%0,%2
     NEG    R%2,R%2\;DSAR   R%0,R%2 ")


;; rotate instructions

(define_insn "rotlqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
                   (match_operand:QI 2 "general_operand" "I,r")))]
  ""
  "@
    SLC    R%0,%2
    SCR    R%0,R%2 ")

(define_insn "rotlhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
                   (match_operand:QI 2 "general_operand" "I,r")))]
  ""
  "@
    DSLC   R%0,%2
    DSCR   R%0,R%2 ")

(define_insn "rotrqi3"
  [(set (match_operand:QI 0 "register_operand" "=r,r")
        (rotatert:QI (match_operand:QI 1 "register_operand" "0,0")
                     (match_operand:QI 2 "general_operand" "I,r")))]
  ""
  "@
    SLC    R%0,%2
    NEG    R%2,R%2\;SCR    R%0,R%2 ")

(define_insn "rotrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
        (rotatert:HI (match_operand:HI 1 "register_operand" "0,0")
                     (match_operand:QI 2 "general_operand" "I,r")))]
  ""
  "@
    DSLC   R%0,%2
    NEG    R%2,R%2\;DSCR   R%0,R%2 ")



;; Special cases of bit-field insns which we should
;; recognize in preference to the general case.
;; These handle aligned 8-bit and 16-bit fields,
;; which can usually be done with move instructions.
;    1750: t.b.d.
;********************

;; Bit field instructions, general cases.
;; "o,d" constraint causes a nonoffsetable memref to match the "o"
;; so that its address is reloaded.

;; (define_insn "extv" ...

;; (define_insn "extzv" ...

;; (define_insn "insv" ...

;; Now recognize bit field insns that operate on registers
;; (or at least were intended to do so).
;[unnamed only]

;; Special patterns for optimizing bit-field instructions.
;**************************************

; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
;  [(set (match_operand:QI 0 "general_operand" "=d")
;        (leu (cc0) (const_int 0)))]
;  ""
;  "* cc_status = cc_prev_status;
;     return \"sls %0\"; ")


;; Basic conditional jump instructions.

(define_insn "beq"
  [(set (pc)
        (if_then_else (eq (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"EZ\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "bne"
  [(set (pc)
        (if_then_else (ne (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"NZ\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "bgt"
  [(set (pc)
        (if_then_else (gt (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"GT\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "blt"
  [(set (pc)
        (if_then_else (lt (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"LT\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "bge"
  [(set (pc)
        (if_then_else (ge (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"GE\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn "ble"
  [(set (pc)
        (if_then_else (le (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "* return (char *)branch_or_jump(\"LE\",CODE_LABEL_NUMBER(operands[0]));
  ")


; no unsigned branches available on 1750. But GCC still needs them, so faking:

(define_insn "bgtu"
  [(set (pc)
        (if_then_else (gtu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "JC     GT,%l0 ; Warning: this should be an *unsigned* test!")

(define_insn "bltu"
  [(set (pc)
        (if_then_else (ltu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "JC     LT,%l0 ; Warning: this should be an *unsigned* test!")

(define_insn "bgeu"
  [(set (pc)
        (if_then_else (geu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "JC     GE,%l0 ; Warning: this should be an *unsigned* test!")

(define_insn "bleu"
  [(set (pc)
        (if_then_else (leu (cc0)
                          (const_int 0))
                      (label_ref (match_operand 0 "" ""))
                      (pc)))]
  ""
  "JC     LE,%l0 ; Warning: this should be an *unsigned* test!")


;; Negated conditional jump instructions.

(define_insn ""
  [(set (pc)
        (if_then_else (eq (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"NZ\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"EZ\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (gt (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"LE\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (lt (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"GE\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (ge (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"LT\",CODE_LABEL_NUMBER(operands[0]));
  ")

(define_insn ""
  [(set (pc)
        (if_then_else (le (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return (char *)branch_or_jump(\"GT\",CODE_LABEL_NUMBER(operands[0]));
  ")


;; Negated unsigned conditional jump instructions (faked for 1750).

(define_insn ""
  [(set (pc)
        (if_then_else (gtu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "JC     LE,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

(define_insn ""
  [(set (pc)
        (if_then_else (ltu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "JC     GE,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

(define_insn ""
  [(set (pc)
        (if_then_else (geu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "JC     LT,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

(define_insn ""
  [(set (pc)
        (if_then_else (leu (cc0)
                          (const_int 0))
                      (pc)
                      (label_ref (match_operand 0 "" ""))))]
  ""
  "JC     GT,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")

;; Tablejump 
;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
(define_insn "tablejump"
  [(set (pc)
        (match_operand:QI 0 "register_operand" "b"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "JC     15,0,R%0   ; tablejump label_ref=%1")


;; Unconditional jump
(define_insn "jump"
  [(set (pc)
        (label_ref (match_operand 0 "" "")))]
  ""
  "JC     UC,%0")

;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
(define_insn "call_value"
  [(set (match_operand 0 "register_operand" "r")
        (call (match_operand:QI 1 "memory_operand" "m")
              (match_operand:QI 2 "general_operand" "g")))]
  ;; Operand 2 not really used for 1750.
  ""
  "SJS    R15,%1   ; return value in R0")

;; Call subroutine with no return value.

;;  Operand 1 not really used in MIL-STD-1750.
(define_insn ""
  [(call (match_operand:QI 0 "memory_operand" "mp")
         (match_operand:QI 1 "general_operand" ""))]
  ""
  "SJS    R15,%0   ; no return value")

;;;;;;;;;;;; 1750: NOT READY YET.
(define_insn "call"
  [(call (match_operand:QI 0 "" "")
         (match_operand:QI 1 "" ""))]
  ""
  "ANYCALL %0")


; (define_insn "return"
;   [(return)]
;   ""
;   "*
;    { 
;         rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size());
;         output_asm_insn(\"RET.M  %0\",&oprnd);
;         return \"\;\";
;    } ")

(define_insn "indirect_jump"
  [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
  ""
  "JCI   15,%0")

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop")


;; Subtract One and Jump (if non-zero)
(define_peephole 
  [(set (match_operand:QI 0 "register_operand" "=r")
        (plus:QI (match_operand:QI 1 "register_operand" "%0")
                 (match_operand:QI 2 "immediate_operand" "J")))
   (set (cc0) (match_dup 0))
   (set (pc)
        (if_then_else (ne (cc0) (const_int 0))
         (label_ref (match_operand 3 "" ""))
         (pc)))
   ]
  "INTVAL(operands[2]) == -1"
  "SOJ    R%0,%3")

;;;End.

