[PATCH][AArch64] Allow CMP+SHIFT when comparing with zero

gcc/

	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
	comparision with zero.

gcc/testsuite/

	* gcc.target/aarch64/cmp_shifted_reg_1.c: New.

From-SVN: r248836

gcc/ChangeLog

+2017-06-02  Sudakshina Das  <sudi.das@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
+	comparision with zero.
+
 2017-06-02  Will Schmidt  <will_schmidt@vnet.ibm.com>
 	* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling
 	for early expansion of vec_min and vec_max builtins.

gcc/config/aarch64/aarch64.c

@@ -4767,7 +4767,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
      the comparison will have to be swapped when we emit the assembly
      code.  */
   if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
-      && (REG_P (y) || GET_CODE (y) == SUBREG)
+      && (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx)
       && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
 	  || GET_CODE (x) == LSHIFTRT
 	  || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND))

gcc/testsuite/ChangeLog

+2017-06-02  Sudakshina Das  <sudi.das@arm.com>
+
+	* gcc.target/aarch64/cmp_shifted_reg_1.c: New.
+
 2017-06-02  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
 	* gcc.target/powerpc/fold-vec-minmax-char.c: New.

gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c

+/* { dg-do compile } */
+/* { dg-options "-O2 " } */
+
+int f3 (int x, int y)
+{
+  int res = x << 3;
+  return res != 0;
+}
+
+/* We should combine the shift and compare */
+/* { dg-final { scan-assembler "cmp\.*\twzr, w\[0-9\]+, lsl 3" } } */