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riscv-gcc-1
Commit fdc54592 by Uros Bizjak
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alpha.md (FMODE): New mode iterator. 

	* config/alpha/alpha.md (FMODE): New mode iterator.
	(modesuffix): Handle SF and DF modes.
	(opmode): New mode attribute.
	(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
	(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
	FMODE mode iterator.
	(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
	(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
	FMODE mode iterator.
	(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
	FMODE mode iterator.
	(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
	FMODE mode iterator.
	(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
	(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
	FMODE mode iterator.
	(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
	(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
	FMODE mode iterator.
	(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
	(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
	FMODE mode iterator.
	(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
	(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
	FMODE mode iterator.
	(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
	using FMODE mode iterator.
	(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
	using FMODE mode iterator.
	(mov<mode>cc): Macroize expander from mov{sf,df}cc
	using FMODE mode iterator.

From-SVN: r192421
parent c4648c1d
Showing with 294 additions and 425 deletions
gcc/ChangeLog
2012-10-13 Uros Bizjak <ubizjak@gmail.com>
* config/alpha/alpha.md (FMODE): New mode iterator.
(modesuffix): Handle SF and DF modes.
(opmode): New mode attribute.
(abs<mode>2): Macroize insn from abs{sf,df}2 using FMODE mode iterator.
(*nabs<mode>2): Macroize insn from *nabs{sf,df}2 using
FMODE mode iterator.
(neg<mode>2): Macroize insn from neg{sf,df}2 using FMODE mode iterator.
(copysign<mode>3): Macroize insn from copysign{sf,df}3 using
FMODE mode iterator.
(*ncopysign<mode>3): Macroize insn from *ncopysign{sf,df}3 using
FMODE mode iterator.
(*add<mode>3_ieee): Macroize insn from *add{sf,df}_ieee using
FMODE mode iterator.
(add<mode>3): Macroize insn from add{sf,df}3 using FMODE mode iterator.
(*sub<mode>3_ieee): Macroize insn from *sub{sf,df}3_ieee using
FMODE mode iterator.
(sub<mode>3): Macroize insn from sub{sf,df}3 using FMODE mode iterator.
(*mul<mode>3_ieee): Macroize insn from *mul{sf,df}3_ieee using
FMODE mode iterator.
(mul<mode>3): Macroize insn from mul{sf,df}3 using FMODE mode iterator.
(*div<mode>3_ieee): Macroize insn from *div{sf,df}3_ieee using
FMODE mode iterator.
(div<mode>3): Macroize insn from div{sf,df}3 using FMODE mode iterator.
(*sqrt<mode>2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using
FMODE mode iterator.
(sqrt<mode>2): Macroize insn from sqrt{sf,df}2
using FMODE mode iterator.
(*mov<mode>cc_internal): Macroize insn from *mov{sf,df}cc_internal
using FMODE mode iterator.
(mov<mode>cc): Macroize expander from mov{sf,df}cc
using FMODE mode iterator.
2012-10-12 Oleg Endo <olegendo@gcc.gnu.org> 2012-10-12 Oleg Endo <olegendo@gcc.gnu.org>
PR target/54602 PR target/54602
...@@ -12,8 +46,8 @@ ...@@ -12,8 +46,8 @@
* config/sh/predicates.md (fpul_operand): Add comment. * config/sh/predicates.md (fpul_operand): Add comment.
(fpul_fsca_operand, fsca_scale_factor): New predicates. (fpul_fsca_operand, fsca_scale_factor): New predicates.
* config/sh/sh.md (fsca): Move below sincossf3 expander. Convert to * config/sh/sh.md (fsca): Move below sincossf3 expander. Convert to
insn_and_split. Use fpul_fsca_operand and fsca_scale_factor predicates. insn_and_split. Use fpul_fsca_operand and fsca_scale_factor
Simplify fpul operand in splitter. predicates. Simplify fpul operand in splitter.
2012-10-12 Jan Hubicka <jh@suse.cz> 2012-10-12 Jan Hubicka <jh@suse.cz>
...@@ -33,8 +67,7 @@ ...@@ -33,8 +67,7 @@
protected, private, template, operator, friend, &, ~. protected, private, template, operator, friend, &, ~.
(TYPEDEF): New. Support typedef. (TYPEDEF): New. Support typedef.
* gengtype-parser.c: updated 'token_names[]' * gengtype-parser.c: updated 'token_names[]'
(direct_declarator): Add support for parsing functions (direct_declarator): Add support for parsing functions and ctors.
and ctors.
2012-10-12 Diego Novillo <dnovillo@google.com> 2012-10-12 Diego Novillo <dnovillo@google.com>
...@@ -54,23 +87,22 @@ ...@@ -54,23 +87,22 @@
Add argument IN_STRUCT. Add argument IN_STRUCT.
If the token following ID is a '(', consider ID a If the token following ID is a '(', consider ID a
function and return NULL. function and return NULL.
If the token following '(' is not a '*', and IN_STRUCT is If the token following '(' is not a '*', and IN_STRUCT is true,
true, conclude that this is a ctor and return NULL. conclude that this is a ctor and return NULL.
If the token is IGNORABLE_CXX_KEYWORD, return NULL. If the token is IGNORABLE_CXX_KEYWORD, return NULL.
(inner_declarator): Add argument IN_STRUCT. (inner_declarator): Add argument IN_STRUCT.
Update all callers. Update all callers.
(declarator): Add argument IN_STRUCT with default value (declarator): Add argument IN_STRUCT with default value false.
false. Update all callers. Update all callers.
(type): Document argument NESTED. (type): Document argument NESTED.
Skip over C++ inheritance specifiers. Skip over C++ inheritance specifiers.
If a token TYPEDEF is found, emit an error. If a token TYPEDEF is found, emit an error.
If an enum is found inside a class/structure, emit an If an enum is found inside a class/structure, emit an error.
error.
(typedefs, structures, param_structs, variables): Initialize. (typedefs, structures, param_structs, variables): Initialize.
(new_structure): Do not complain about duplicate (new_structure): Do not complain about duplicate
structures if S has a line location set. structures if S has a line location set.
* gengtype-state.c (write_state_type): Remove default * gengtype-state.c (write_state_type): Remove default handler.
handler. Add handler for TYPE_NONE. Add handler for TYPE_NONE.
(read_state_scalar_char_type): (read_state_scalar_char_type):
* gengtype.c: Fix spacing. * gengtype.c: Fix spacing.
* gengtype.h (enum gty_token): Add name. Add token * gengtype.h (enum gty_token): Add name. Add token
gcc/config/alpha/alpha.md
...@@ -98,7 +98,8 @@ ...@@ -98,7 +98,8 @@
(define_mode_attr DWI [(SI "DI") (DI "TI")]) (define_mode_attr DWI [(SI "DI") (DI "TI")])
(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")
(V8QI "b8") (V4HI "w4")]) (V8QI "b8") (V4HI "w4")
(SF "%,") (DF "%-")])
(define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) (define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")])
(define_code_iterator any_maxmin [smax smin umax umin]) (define_code_iterator any_maxmin [smax smin umax umin])
...@@ -1666,30 +1667,21 @@ ...@@ -1666,30 +1667,21 @@
;; from single, so indicate that. The exception are the ones that simply ;; from single, so indicate that. The exception are the ones that simply
;; play with the sign bits; it's not clear what to do there. ;; play with the sign bits; it's not clear what to do there.
(define_insn "abssf2" (define_mode_iterator FMODE [SF DF])
[(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cpys $f31,%R1,%0"
[(set_attr "type" "fcpys")])
(define_insn "*nabssf2" (define_mode_attr opmode [(SF "si") (DF "di")])
[(set (match_operand:SF 0 "register_operand" "=f")
(neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP"
"cpysn $f31,%R1,%0"
[(set_attr "type" "fadd")])
(define_insn "absdf2" (define_insn "abs<mode>2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:FMODE 0 "register_operand" "=f")
(abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
"TARGET_FP" "TARGET_FP"
"cpys $f31,%R1,%0" "cpys $f31,%R1,%0"
[(set_attr "type" "fcpys")]) [(set_attr "type" "fcpys")])
(define_insn "*nabsdf2" (define_insn "*nabs<mode>2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:FMODE 0 "register_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))] (neg:FMODE
(abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))]
"TARGET_FP" "TARGET_FP"
"cpysn $f31,%R1,%0" "cpysn $f31,%R1,%0"
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")])
...@@ -1717,16 +1709,9 @@ ...@@ -1717,16 +1709,9 @@
[(const_int 0)] [(const_int 0)]
"alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
(define_insn "negsf2" (define_insn "neg<mode>2"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:FMODE 0 "register_operand" "=f")
(neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"cpysn %R1,%R1,%0"
[(set_attr "type" "fadd")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP" "TARGET_FP"
"cpysn %R1,%R1,%0" "cpysn %R1,%R1,%0"
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")])
...@@ -1754,117 +1739,285 @@ ...@@ -1754,117 +1739,285 @@
[(const_int 0)] [(const_int 0)]
"alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
(define_insn "copysignsf3" (define_insn "copysign<mode>3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:FMODE 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG") (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")] (match_operand:FMODE 2 "reg_or_0_operand" "fG")]
UNSPEC_COPYSIGN))] UNSPEC_COPYSIGN))]
"TARGET_FP" "TARGET_FP"
"cpys %R2,%R1,%0" "cpys %R2,%R1,%0"
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")])
(define_insn "*ncopysignsf3" (define_insn "*ncopysign<mode>3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:FMODE 0 "register_operand" "=f")
(neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG") (neg:FMODE
(match_operand:SF 2 "reg_or_0_operand" "fG")] (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG")
UNSPEC_COPYSIGN)))] (match_operand:FMODE 2 "reg_or_0_operand" "fG")]
UNSPEC_COPYSIGN)))]
"TARGET_FP" "TARGET_FP"
"cpysn %R2,%R1,%0" "cpysn %R2,%R1,%0"
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")])
(define_insn "copysigndf3" (define_insn "*add<mode>3_ieee"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:FMODE 0 "register_operand" "=&f")
(unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG") (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")] (match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
UNSPEC_COPYSIGN))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"add<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "add<mode>3"
[(set (match_operand:FMODE 0 "register_operand" "=f")
(plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
"TARGET_FP" "TARGET_FP"
"cpys %R2,%R1,%0" "add<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*ncopysigndf3" (define_insn "*adddf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG") (plus:DF (float_extend:DF
(match_operand:DF 2 "reg_or_0_operand" "fG")] (match_operand:SF 1 "reg_or_0_operand" "fG"))
UNSPEC_COPYSIGN)))] (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"cpysn %R2,%R1,%0" "add%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")]) [(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*addsf_ieee" (define_insn "*adddf_ext2"
[(set (match_operand:SF 0 "register_operand" "=&f") [(set (match_operand:DF 0 "register_operand" "=f")
(plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") (plus:DF (float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG")))] (match_operand:SF 1 "reg_or_0_operand" "%fG"))
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"add%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "addtf3"
[(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))
(use (match_operand:TF 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (PLUS, operands); DONE;")
(define_insn "*sub<mode>3_ieee"
[(set (match_operand:FMODE 0 "register_operand" "=&f")
(minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"add%,%/ %R1,%R2,%0" "sub<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes") (set_attr "trap" "yes")
(set_attr "round_suffix" "normal") (set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_insn "addsf3" (define_insn "sub<mode>3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:FMODE 0 "register_operand" "=f")
(plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")))] (match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
"TARGET_FP" "TARGET_FP"
"add%,%/ %R1,%R2,%0" "sub<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes") (set_attr "trap" "yes")
(set_attr "round_suffix" "normal") (set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_insn "*adddf_ieee" (define_insn "*subdf_ext1"
[(set (match_operand:DF 0 "register_operand" "=&f") [(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") (minus:DF (float_extend:DF
(match_operand:DF 2 "reg_or_0_operand" "fG")))] (match_operand:SF 1 "reg_or_0_operand" "fG"))
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"add%-%/ %R1,%R2,%0" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes") (set_attr "trap" "yes")
(set_attr "round_suffix" "normal") (set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_insn "adddf3" (define_insn "*subdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")))] (float_extend:DF
"TARGET_FP" (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"add%-%/ %R1,%R2,%0" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd") [(set_attr "type" "fadd")
(set_attr "trap" "yes") (set_attr "trap" "yes")
(set_attr "round_suffix" "normal") (set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_insn "*adddf_ext1" (define_insn "*subdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (float_extend:DF (minus:DF (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "subtf3"
[(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))
(use (match_operand:TF 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
(define_insn "*mul<mode>3_ieee"
[(set (match_operand:FMODE 0 "register_operand" "=&f")
(mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"mul<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "mul<mode>3"
[(set (match_operand:FMODE 0 "register_operand" "=f")
(mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG")
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"mul<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*muldf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG")) (match_operand:SF 1 "reg_or_0_operand" "fG"))
(match_operand:DF 2 "reg_or_0_operand" "fG")))] (match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"add%-%/ %R1,%R2,%0" "mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd") [(set_attr "type" "fmul")
(set_attr "trap" "yes") (set_attr "trap" "yes")
(set_attr "round_suffix" "normal") (set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_insn "*adddf_ext2" (define_insn "*muldf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (float_extend:DF (mult:DF (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "%fG")) (match_operand:SF 1 "reg_or_0_operand" "%fG"))
(float_extend:DF (float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))] (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"add%-%/ %R1,%R2,%0" "mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd") [(set_attr "type" "fmul")
(set_attr "trap" "yes") (set_attr "trap" "yes")
(set_attr "round_suffix" "normal") (set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")]) (set_attr "trap_suffix" "u_su_sui")])
(define_expand "addtf3" (define_expand "multf3"
[(use (match_operand:TF 0 "register_operand" "")) [(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" "")) (use (match_operand:TF 1 "general_operand" ""))
(use (match_operand:TF 2 "general_operand" ""))] (use (match_operand:TF 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS" "TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (PLUS, operands); DONE;") "alpha_emit_xfloating_arith (MULT, operands); DONE;")
(define_insn "*div<mode>3_ieee"
[(set (match_operand:FMODE 0 "register_operand" "=&f")
(div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"div<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "opsize" "<opmode>")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "div<mode>3"
[(set (match_operand:FMODE 0 "register_operand" "=f")
(div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")
(match_operand:FMODE 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"div<modesuffix>%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "opsize" "<opmode>")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*divdf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*divdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*divdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
(float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "divtf3"
[(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))
(use (match_operand:TF 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (DIV, operands); DONE;")
(define_insn "*sqrt<mode>2_ieee"
[(set (match_operand:FMODE 0 "register_operand" "=&f")
(sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
"sqrt<modesuffix>%/ %R1,%0"
[(set_attr "type" "fsqrt")
(set_attr "opsize" "<opmode>")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "sqrt<mode>2"
[(set (match_operand:FMODE 0 "register_operand" "=f")
(sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX"
"sqrt<modesuffix>%/ %R1,%0"
[(set_attr "type" "fsqrt")
(set_attr "opsize" "<opmode>")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
;; Define conversion operators between DFmode and SImode, using the cvtql ;; Define conversion operators between DFmode and SImode, using the cvtql
;; instruction. To allow combine et al to do useful things, we keep the ;; instruction. To allow combine et al to do useful things, we keep the
...@@ -2270,299 +2423,6 @@ ...@@ -2270,299 +2423,6 @@
emit_insn (gen_truncdfsf2 (operands[0], tmpf)); emit_insn (gen_truncdfsf2 (operands[0], tmpf));
DONE; DONE;
}) })
(define_insn "*divsf3_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
(div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"div%,%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "opsize" "si")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "divsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"div%,%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "opsize" "si")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*divdf3_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "divdf3"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*divdf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*divdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*divdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
(float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "divtf3"
[(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))
(use (match_operand:TF 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (DIV, operands); DONE;")
(define_insn "*mulsf3_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
(mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"mul%,%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"mul%,%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*muldf3_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
(mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "muldf3"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*muldf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*muldf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "%fG"))
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"mul%-%/ %R1,%R2,%0"
[(set_attr "type" "fmul")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "multf3"
[(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))
(use (match_operand:TF 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MULT, operands); DONE;")
(define_insn "*subsf3_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
(minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"sub%,%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "subsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
(match_operand:SF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"sub%,%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*subdf3_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
(minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "subdf3"
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*subdf_ext1"
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))
(match_operand:DF 2 "reg_or_0_operand" "fG")))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*subdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*subdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "reg_or_0_operand" "fG"))
(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"sub%-%/ %R1,%R2,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "subtf3"
[(use (match_operand:TF 0 "register_operand" ""))
(use (match_operand:TF 1 "general_operand" ""))
(use (match_operand:TF 2 "general_operand" ""))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
(define_insn "*sqrtsf2_ieee"
[(set (match_operand:SF 0 "register_operand" "=&f")
(sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
"sqrt%,%/ %R1,%0"
[(set_attr "type" "fsqrt")
(set_attr "opsize" "si")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX"
"sqrt%,%/ %R1,%0"
[(set_attr "type" "fsqrt")
(set_attr "opsize" "si")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "*sqrtdf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=&f")
(sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
"sqrt%-%/ %R1,%0"
[(set_attr "type" "fsqrt")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX"
"sqrt%-%/ %R1,%0"
[(set_attr "type" "fsqrt")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(set_attr "trap_suffix" "u_su_sui")])
;; Next are all the integer comparisons, and conditional moves and branches ;; Next are all the integer comparisons, and conditional moves and branches
;; and some of the related define_expand's and define_split's. ;; and some of the related define_expand's and define_split's.
...@@ -2979,28 +2839,14 @@ ...@@ -2979,28 +2839,14 @@
(set_attr "trap" "yes") (set_attr "trap" "yes")
(set_attr "trap_suffix" "su")]) (set_attr "trap_suffix" "su")])
(define_insn "*movdfcc_internal" (define_insn "*mov<mode>cc_internal"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:FMODE 0 "register_operand" "=f,f")
(if_then_else:DF (if_then_else:FMODE
(match_operator 3 "signed_comparison_operator"
[(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
(match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:DF 1 "reg_or_0_operand" "fG,0")
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
[(set_attr "type" "fcmov")])
(define_insn "*movsfcc_internal"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
(match_operator 3 "signed_comparison_operator" (match_operator 3 "signed_comparison_operator"
[(match_operand:DF 4 "reg_or_0_operand" "fG,fG") [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
(match_operand:DF 2 "const0_operand" "G,G")]) (match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:SF 1 "reg_or_0_operand" "fG,0") (match_operand:FMODE 1 "reg_or_0_operand" "fG,0")
(match_operand:SF 5 "reg_or_0_operand" "0,fG")))] (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))]
"TARGET_FP" "TARGET_FP"
"@ "@
fcmov%C3 %R4,%R1,%0 fcmov%C3 %R4,%R1,%0
...@@ -3209,25 +3055,16 @@ ...@@ -3209,25 +3055,16 @@
FAIL; FAIL;
}) })
(define_expand "movsfcc" (define_expand "mov<mode>cc"
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:FMODE 0 "register_operand" "")
(if_then_else:SF (match_operand 1 "comparison_operator" "") (if_then_else:FMODE
(match_operand:SF 2 "reg_or_8bit_operand" "") (match_operand 1 "comparison_operator" "")
(match_operand:SF 3 "reg_or_8bit_operand" "")))] (match_operand:FMODE 2 "reg_or_8bit_operand" "")
"" (match_operand:FMODE 3 "reg_or_8bit_operand" "")))]
{
if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
FAIL;
})
(define_expand "movdfcc"
[(set (match_operand:DF 0 "register_operand" "")
(if_then_else:DF (match_operand 1 "comparison_operator" "")
(match_operand:DF 2 "reg_or_8bit_operand" "")
(match_operand:DF 3 "reg_or_8bit_operand" "")))]
"" ""
{ {
if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0) operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
if (operands[1] == 0)
FAIL; FAIL;
}) })
......
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