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Commit f9d53c27 by Tejas Belagod Committed by Tejas Belagod
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[AArch64] Restructure arm_neon.h vector types. 

2014-11-05  Tejas Belagod  <tejas.belagod@arm.com>

	* config/aarch64/aarch64-builtins.c
	(aarch64_build_scalar_type): Remove.
	(aarch64_scalar_builtin_types, aarch64_simd_type,
	aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
	aarch64_mangle_builtin_vector_type,
	aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
	aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
	aarch64_init_simd_builtin_types,
	aarch64_init_simd_builtin_scalar_types): New.
	(aarch64_init_simd_builtins): Refactor.
	(aarch64_init_crc32_builtins): Fixup with qualifier.
	* config/aarch64/aarch64-protos.h
	(aarch64_mangle_builtin_type): Export.
	* config/aarch64/aarch64-simd-builtin-types.def: New.
	* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
	(aarch64_mangle_type): Refactor.
	* config/aarch64/arm_neon.h: Declare vector types based on
	internal types.
	* config/aarch64/t-aarch64: Update dependency.

From-SVN: r217114
parent 3cbdd831
Showing with 108 additions and 121 deletions
gcc/ChangeLog
2014-11-05 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_build_scalar_type): Remove.
(aarch64_scalar_builtin_types, aarch64_simd_type,
aarch64_simd_type, aarch64_mangle_builtin_scalar_type,
aarch64_mangle_builtin_vector_type,
aarch64_mangle_builtin_type, aarch64_simd_builtin_std_type,
aarch64_lookup_simd_builtin_type, aarch64_simd_builtin_type,
aarch64_init_simd_builtin_types,
aarch64_init_simd_builtin_scalar_types): New.
(aarch64_init_simd_builtins): Refactor.
(aarch64_init_crc32_builtins): Fixup with qualifier.
* config/aarch64/aarch64-protos.h
(aarch64_mangle_builtin_type): Export.
* config/aarch64/aarch64-simd-builtin-types.def: New.
* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Remove.
(aarch64_mangle_type): Refactor.
* config/aarch64/arm_neon.h: Declare vector types based on
internal types.
* config/aarch64/t-aarch64: Update dependency.
2014-11-04 Pat Haugen <pthaugen@us.ibm.com> 2014-11-04 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/rs6000.c (atomic_hold_decl, atomic_clear_decl, * config/rs6000/rs6000.c (atomic_hold_decl, atomic_clear_decl,
gcc/config/aarch64/aarch64-protos.h
...@@ -214,6 +214,7 @@ bool aarch64_simd_valid_immediate (rtx, machine_mode, bool, ...@@ -214,6 +214,7 @@ bool aarch64_simd_valid_immediate (rtx, machine_mode, bool,
bool aarch64_symbolic_address_p (rtx); bool aarch64_symbolic_address_p (rtx);
bool aarch64_uimm12_shift (HOST_WIDE_INT); bool aarch64_uimm12_shift (HOST_WIDE_INT);
bool aarch64_use_return_insn_p (void); bool aarch64_use_return_insn_p (void);
const char *aarch64_mangle_builtin_type (const_tree);
const char *aarch64_output_casesi (rtx *); const char *aarch64_output_casesi (rtx *);
const char *aarch64_rewrite_selected_cpu (const char *name); const char *aarch64_rewrite_selected_cpu (const char *name);
......
gcc/config/aarch64/aarch64-simd-builtin-types.def 0 → 100644
/* Builtin AdvSIMD types.
Copyright (C) 2014 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
ENTRY (Int8x8_t, V8QI, none, 10)
ENTRY (Int8x16_t, V16QI, none, 11)
ENTRY (Int16x4_t, V4HI, none, 11)
ENTRY (Int16x8_t, V8HI, none, 11)
ENTRY (Int32x2_t, V2SI, none, 11)
ENTRY (Int32x4_t, V4SI, none, 11)
ENTRY (Int64x1_t, DI, none, 11)
ENTRY (Int64x2_t, V2DI, none, 11)
ENTRY (Uint8x8_t, V8QI, unsigned, 11)
ENTRY (Uint8x16_t, V16QI, unsigned, 12)
ENTRY (Uint16x4_t, V4HI, unsigned, 12)
ENTRY (Uint16x8_t, V8HI, unsigned, 12)
ENTRY (Uint32x2_t, V2SI, unsigned, 12)
ENTRY (Uint32x4_t, V4SI, unsigned, 12)
ENTRY (Uint64x1_t, DI, unsigned, 12)
ENTRY (Uint64x2_t, V2DI, unsigned, 12)
ENTRY (Poly8_t, QI, poly, 9)
ENTRY (Poly16_t, HI, poly, 10)
ENTRY (Poly64_t, DI, poly, 10)
ENTRY (Poly128_t, TI, poly, 11)
ENTRY (Poly8x8_t, V8QI, poly, 11)
ENTRY (Poly8x16_t, V16QI, poly, 12)
ENTRY (Poly16x4_t, V4HI, poly, 12)
ENTRY (Poly16x8_t, V8HI, poly, 12)
ENTRY (Poly64x1_t, DI, poly, 12)
ENTRY (Poly64x2_t, V2DI, poly, 12)
ENTRY (Float32x2_t, V2SF, none, 13)
ENTRY (Float32x4_t, V4SF, none, 13)
ENTRY (Float64x1_t, V1DF, none, 13)
ENTRY (Float64x2_t, V2DF, none, 13)
gcc/config/aarch64/aarch64.c
...@@ -7597,54 +7597,6 @@ aarch64_autovectorize_vector_sizes (void) ...@@ -7597,54 +7597,6 @@ aarch64_autovectorize_vector_sizes (void)
return (16 | 8); return (16 | 8);
} }
/* A table to help perform AArch64-specific name mangling for AdvSIMD
vector types in order to conform to the AAPCS64 (see "Procedure
Call Standard for the ARM 64-bit Architecture", Appendix A). To
qualify for emission with the mangled names defined in that document,
a vector type must not only be of the correct mode but also be
composed of AdvSIMD vector element types (e.g.
_builtin_aarch64_simd_qi); these types are registered by
aarch64_init_simd_builtins (). In other words, vector types defined
in other ways e.g. via vector_size attribute will get default
mangled names. */
typedef struct
{
machine_mode mode;
const char *element_type_name;
const char *mangled_name;
} aarch64_simd_mangle_map_entry;
static aarch64_simd_mangle_map_entry aarch64_simd_mangle_map[] = {
/* 64-bit containerized types. */
{ V8QImode, "__builtin_aarch64_simd_qi", "10__Int8x8_t" },
{ V8QImode, "__builtin_aarch64_simd_uqi", "11__Uint8x8_t" },
{ V4HImode, "__builtin_aarch64_simd_hi", "11__Int16x4_t" },
{ V4HImode, "__builtin_aarch64_simd_uhi", "12__Uint16x4_t" },
{ V2SImode, "__builtin_aarch64_simd_si", "11__Int32x2_t" },
{ V2SImode, "__builtin_aarch64_simd_usi", "12__Uint32x2_t" },
{ V2SFmode, "__builtin_aarch64_simd_sf", "13__Float32x2_t" },
{ DImode, "__builtin_aarch64_simd_di", "11__Int64x1_t" },
{ DImode, "__builtin_aarch64_simd_udi", "12__Uint64x1_t" },
{ V1DFmode, "__builtin_aarch64_simd_df", "13__Float64x1_t" },
{ V8QImode, "__builtin_aarch64_simd_poly8", "11__Poly8x8_t" },
{ V4HImode, "__builtin_aarch64_simd_poly16", "12__Poly16x4_t" },
/* 128-bit containerized types. */
{ V16QImode, "__builtin_aarch64_simd_qi", "11__Int8x16_t" },
{ V16QImode, "__builtin_aarch64_simd_uqi", "12__Uint8x16_t" },
{ V8HImode, "__builtin_aarch64_simd_hi", "11__Int16x8_t" },
{ V8HImode, "__builtin_aarch64_simd_uhi", "12__Uint16x8_t" },
{ V4SImode, "__builtin_aarch64_simd_si", "11__Int32x4_t" },
{ V4SImode, "__builtin_aarch64_simd_usi", "12__Uint32x4_t" },
{ V2DImode, "__builtin_aarch64_simd_di", "11__Int64x2_t" },
{ V2DImode, "__builtin_aarch64_simd_udi", "12__Uint64x2_t" },
{ V4SFmode, "__builtin_aarch64_simd_sf", "13__Float32x4_t" },
{ V2DFmode, "__builtin_aarch64_simd_df", "13__Float64x2_t" },
{ V16QImode, "__builtin_aarch64_simd_poly8", "12__Poly8x16_t" },
{ V8HImode, "__builtin_aarch64_simd_poly16", "12__Poly16x8_t" },
{ V2DImode, "__builtin_aarch64_simd_poly64", "12__Poly64x2_t" },
{ VOIDmode, NULL, NULL }
};
/* Implement TARGET_MANGLE_TYPE. */ /* Implement TARGET_MANGLE_TYPE. */
static const char * static const char *
...@@ -7655,25 +7607,10 @@ aarch64_mangle_type (const_tree type) ...@@ -7655,25 +7607,10 @@ aarch64_mangle_type (const_tree type)
if (lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) if (lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type))
return "St9__va_list"; return "St9__va_list";
/* Check the mode of the vector type, and the name of the vector /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
element type, against the table. */ builtin types. */
if (TREE_CODE (type) == VECTOR_TYPE) if (TYPE_NAME (type) != NULL)
{ return aarch64_mangle_builtin_type (type);
aarch64_simd_mangle_map_entry *pos = aarch64_simd_mangle_map;
while (pos->mode != VOIDmode)
{
tree elt_type = TREE_TYPE (type);
if (pos->mode == TYPE_MODE (type)
&& TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL
&& !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))),
pos->element_type_name))
return pos->mangled_name;
pos++;
}
}
/* Use the default mangling. */ /* Use the default mangling. */
return NULL; return NULL;
......
gcc/config/aarch64/arm_neon.h
...@@ -32,63 +32,39 @@ ...@@ -32,63 +32,39 @@
#define __AARCH64_UINT64_C(__C) ((uint64_t) __C) #define __AARCH64_UINT64_C(__C) ((uint64_t) __C)
#define __AARCH64_INT64_C(__C) ((int64_t) __C) #define __AARCH64_INT64_C(__C) ((int64_t) __C)
typedef __builtin_aarch64_simd_qi int8x8_t typedef __Int8x8_t int8x8_t;
__attribute__ ((__vector_size__ (8))); typedef __Int16x4_t int16x4_t;
typedef __builtin_aarch64_simd_hi int16x4_t typedef __Int32x2_t int32x2_t;
__attribute__ ((__vector_size__ (8))); typedef __Int64x1_t int64x1_t;
typedef __builtin_aarch64_simd_si int32x2_t typedef __Float32x2_t float32x2_t;
__attribute__ ((__vector_size__ (8))); typedef __Poly8x8_t poly8x8_t;
typedef __builtin_aarch64_simd_di int64x1_t typedef __Poly16x4_t poly16x4_t;
__attribute__ ((__vector_size__ (8))); typedef __Uint8x8_t uint8x8_t;
typedef __builtin_aarch64_simd_df float64x1_t typedef __Uint16x4_t uint16x4_t;
__attribute__ ((__vector_size__ (8))); typedef __Uint32x2_t uint32x2_t;
typedef __builtin_aarch64_simd_sf float32x2_t typedef __Float64x1_t float64x1_t;
__attribute__ ((__vector_size__ (8))); typedef __Uint64x1_t uint64x1_t;
typedef __builtin_aarch64_simd_poly8 poly8x8_t typedef __Int8x16_t int8x16_t;
__attribute__ ((__vector_size__ (8))); typedef __Int16x8_t int16x8_t;
typedef __builtin_aarch64_simd_poly16 poly16x4_t typedef __Int32x4_t int32x4_t;
__attribute__ ((__vector_size__ (8))); typedef __Int64x2_t int64x2_t;
typedef __builtin_aarch64_simd_uqi uint8x8_t typedef __Float32x4_t float32x4_t;
__attribute__ ((__vector_size__ (8))); typedef __Float64x2_t float64x2_t;
typedef __builtin_aarch64_simd_uhi uint16x4_t typedef __Poly8x16_t poly8x16_t;
__attribute__ ((__vector_size__ (8))); typedef __Poly16x8_t poly16x8_t;
typedef __builtin_aarch64_simd_usi uint32x2_t typedef __Poly64x2_t poly64x2_t;
__attribute__ ((__vector_size__ (8))); typedef __Uint8x16_t uint8x16_t;
typedef __builtin_aarch64_simd_udi uint64x1_t typedef __Uint16x8_t uint16x8_t;
__attribute__ ((__vector_size__ (8))); typedef __Uint32x4_t uint32x4_t;
typedef __builtin_aarch64_simd_qi int8x16_t typedef __Uint64x2_t uint64x2_t;
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_hi int16x8_t typedef __Poly8_t poly8_t;
__attribute__ ((__vector_size__ (16))); typedef __Poly16_t poly16_t;
typedef __builtin_aarch64_simd_si int32x4_t typedef __Poly64_t poly64_t;
__attribute__ ((__vector_size__ (16))); typedef __Poly128_t poly128_t;
typedef __builtin_aarch64_simd_di int64x2_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_sf float32x4_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_df float64x2_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_poly8 poly8x16_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_poly16 poly16x8_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_poly64 poly64x2_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_uqi uint8x16_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_uhi uint16x8_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_usi uint32x4_t
__attribute__ ((__vector_size__ (16)));
typedef __builtin_aarch64_simd_udi uint64x2_t
__attribute__ ((__vector_size__ (16)));
typedef float float32_t; typedef float float32_t;
typedef double float64_t; typedef double float64_t;
typedef __builtin_aarch64_simd_poly8 poly8_t;
typedef __builtin_aarch64_simd_poly16 poly16_t;
typedef __builtin_aarch64_simd_poly64 poly64_t;
typedef __builtin_aarch64_simd_poly128 poly128_t;
typedef struct int8x8x2_t typedef struct int8x8x2_t
{ {
......
gcc/config/aarch64/t-aarch64
...@@ -32,6 +32,7 @@ aarch64-builtins.o: $(srcdir)/config/aarch64/aarch64-builtins.c $(CONFIG_H) \ ...@@ -32,6 +32,7 @@ aarch64-builtins.o: $(srcdir)/config/aarch64/aarch64-builtins.c $(CONFIG_H) \
$(RTL_H) $(TREE_H) expr.h $(TM_P_H) $(RECOG_H) langhooks.h \ $(RTL_H) $(TREE_H) expr.h $(TM_P_H) $(RECOG_H) langhooks.h \
$(DIAGNOSTIC_CORE_H) $(OPTABS_H) \ $(DIAGNOSTIC_CORE_H) $(OPTABS_H) \
$(srcdir)/config/aarch64/aarch64-simd-builtins.def \ $(srcdir)/config/aarch64/aarch64-simd-builtins.def \
$(srcdir)/config/aarch64/aarch64-simd-builtin-types.def \
aarch64-builtin-iterators.h aarch64-builtin-iterators.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/aarch64/aarch64-builtins.c $(srcdir)/config/aarch64/aarch64-builtins.c
......
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