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Commit f9669294 by Richard Henderson Committed by Richard Henderson
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pa: Use the FMA rtx code. 

        * config/pa/pa.md (fmadf4): Rename from unnamed; use FMA.
        (fmasf4, fnmadf4, fnmasf4): Likewise.
        (unnamed plus+mult insns and splitters): Delete.

From-SVN: r166834
parent 23c819b5
Showing with 25 additions and 231 deletions
gcc/ChangeLog
2010-11-16 Richard Henderson <rth@redhat.com> 2010-11-16 Richard Henderson <rth@redhat.com>
* config/pa/pa.md (fmadf4): Rename from unnamed; use FMA.
(fmasf4, fnmadf4, fnmasf4): Likewise.
(unnamed plus+mult insns and splitters): Delete.
2010-11-16 Richard Henderson <rth@redhat.com>
* config/spu/spu.md (fma<VSF>4): Rename from fma_<VSF>. * config/spu/spu.md (fma<VSF>4): Rename from fma_<VSF>.
(fnma<VSF>4): Rename from fnms_<VSF>. (fnma<VSF>4): Rename from fnms_<VSF>.
(fms<VSF>4): Rename from fms_<VSF>. (fms<VSF>4): Rename from fms_<VSF>.
gcc/config/pa/pa.md
...@@ -6090,64 +6090,44 @@ ...@@ -6090,64 +6090,44 @@
;; PA 2.0 floating point instructions ;; PA 2.0 floating point instructions
; fmpyfadd patterns ; fmpyfadd patterns
(define_insn "" (define_insn "fmadf4"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f") (fma:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")) (match_operand:DF 2 "register_operand" "f")
(match_operand:DF 3 "register_operand" "f")))] (match_operand:DF 3 "register_operand" "f")))]
"TARGET_PA_20 && ! TARGET_SOFT_FLOAT" "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
"fmpyfadd,dbl %1,%2,%3,%0" "fmpyfadd,dbl %1,%2,%3,%0"
[(set_attr "type" "fpmuldbl") [(set_attr "type" "fpmuldbl")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "" (define_insn "fmasf4"
[(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (match_operand:DF 1 "register_operand" "f")
(mult:DF (match_operand:DF 2 "register_operand" "f")
(match_operand:DF 3 "register_operand" "f"))))]
"TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
"fmpyfadd,dbl %2,%3,%1,%0"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f") (fma:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")) (match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f")))] (match_operand:SF 3 "register_operand" "f")))]
"TARGET_PA_20 && ! TARGET_SOFT_FLOAT" "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
"fmpyfadd,sgl %1,%2,%3,%0" "fmpyfadd,sgl %1,%2,%3,%0"
[(set_attr "type" "fpmulsgl") [(set_attr "type" "fpmulsgl")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
(plus:SF (match_operand:SF 1 "register_operand" "f")
(mult:SF (match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f"))))]
"TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
"fmpyfadd,sgl %2,%3,%1,%0"
[(set_attr "type" "fpmulsgl")
(set_attr "length" "4")])
; fmpynfadd patterns ; fmpynfadd patterns
(define_insn "" (define_insn "fnmadf4"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (match_operand:DF 1 "register_operand" "f") (fma:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
(mult:DF (match_operand:DF 2 "register_operand" "f") (match_operand:DF 2 "register_operand" "f")
(match_operand:DF 3 "register_operand" "f"))))] (match_operand:DF 3 "register_operand" "f")))]
"TARGET_PA_20 && ! TARGET_SOFT_FLOAT" "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
"fmpynfadd,dbl %2,%3,%1,%0" "fmpynfadd,dbl %1,%2,%3,%0"
[(set_attr "type" "fpmuldbl") [(set_attr "type" "fpmuldbl")
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "" (define_insn "fnmasf4"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(minus:SF (match_operand:SF 1 "register_operand" "f") (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
(mult:SF (match_operand:SF 2 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f"))))] (match_operand:SF 3 "register_operand" "f")))]
"TARGET_PA_20 && ! TARGET_SOFT_FLOAT" "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
"fmpynfadd,sgl %2,%3,%1,%0" "fmpynfadd,sgl %1,%2,%3,%0"
[(set_attr "type" "fpmulsgl") [(set_attr "type" "fpmulsgl")
(set_attr "length" "4")]) (set_attr "length" "4")])
...@@ -6168,72 +6148,9 @@ ...@@ -6168,72 +6148,9 @@
[(set_attr "type" "fpalu") [(set_attr "type" "fpalu")
(set_attr "length" "4")]) (set_attr "length" "4")])
;; Generating a fused multiply sequence is a win for this case as it will
;; reduce the latency for the fused case without impacting the plain
;; multiply case.
;;
;; Similar possibilities exist for fnegabs, shadd and other insns which
;; perform two operations with the result of the first feeding the second.
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))
(match_operand:DF 3 "register_operand" "f")))
(set (match_operand:DF 4 "register_operand" "=&f")
(mult:DF (match_dup 1) (match_dup 2)))]
"(! TARGET_SOFT_FLOAT && TARGET_PA_20
&& ! (reg_overlap_mentioned_p (operands[4], operands[1])
|| reg_overlap_mentioned_p (operands[4], operands[2])))"
"#"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "8")])
;; We want to split this up during scheduling since we want both insns
;; to schedule independently.
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "register_operand" ""))
(match_operand:DF 3 "register_operand" "")))
(set (match_operand:DF 4 "register_operand" "")
(mult:DF (match_dup 1) (match_dup 2)))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
[(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
(match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))
(set (match_operand:SF 4 "register_operand" "=&f")
(mult:SF (match_dup 1) (match_dup 2)))]
"(! TARGET_SOFT_FLOAT && TARGET_PA_20
&& ! (reg_overlap_mentioned_p (operands[4], operands[1])
|| reg_overlap_mentioned_p (operands[4], operands[2])))"
"#"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "8")])
;; We want to split this up during scheduling since we want both insns
;; to schedule independently.
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "register_operand" ""))
(match_operand:SF 3 "register_operand" "")))
(set (match_operand:SF 4 "register_operand" "")
(mult:SF (match_dup 1) (match_dup 2)))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
[(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
(match_dup 3)))]
"")
;; Negating a multiply can be faked by adding zero in a fused multiply-add ;; Negating a multiply can be faked by adding zero in a fused multiply-add
;; instruction. ;; instruction.
;; ??? Only if we add -0.0 or can ignore the sign of zero.
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f") (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
...@@ -6300,135 +6217,6 @@ ...@@ -6300,135 +6217,6 @@
(set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))] (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
"") "")
;; Now fused multiplies with the result of the multiply negated.
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))
(match_operand:DF 3 "register_operand" "f")))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
"fmpynfadd,dbl %1,%2,%3,%0"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
(plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))
(match_operand:SF 3 "register_operand" "f")))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
"fmpynfadd,sgl %1,%2,%3,%0"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "4")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))
(match_operand:DF 3 "register_operand" "f")))
(set (match_operand:DF 4 "register_operand" "=&f")
(mult:DF (match_dup 1) (match_dup 2)))]
"(! TARGET_SOFT_FLOAT && TARGET_PA_20
&& ! (reg_overlap_mentioned_p (operands[4], operands[1])
|| reg_overlap_mentioned_p (operands[4], operands[2])))"
"#"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "8")])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "register_operand" "")))
(match_operand:DF 3 "register_operand" "")))
(set (match_operand:DF 4 "register_operand" "")
(mult:DF (match_dup 1) (match_dup 2)))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
[(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
(match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
(plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))
(match_operand:SF 3 "register_operand" "f")))
(set (match_operand:SF 4 "register_operand" "=&f")
(mult:SF (match_dup 1) (match_dup 2)))]
"(! TARGET_SOFT_FLOAT && TARGET_PA_20
&& ! (reg_overlap_mentioned_p (operands[4], operands[1])
|| reg_overlap_mentioned_p (operands[4], operands[2])))"
"#"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "8")])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "register_operand" "")))
(match_operand:SF 3 "register_operand" "")))
(set (match_operand:SF 4 "register_operand" "")
(mult:SF (match_dup 1) (match_dup 2)))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
[(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
(match_dup 3)))]
"")
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(minus:DF (match_operand:DF 3 "register_operand" "f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f"))))
(set (match_operand:DF 4 "register_operand" "=&f")
(mult:DF (match_dup 1) (match_dup 2)))]
"(! TARGET_SOFT_FLOAT && TARGET_PA_20
&& ! (reg_overlap_mentioned_p (operands[4], operands[1])
|| reg_overlap_mentioned_p (operands[4], operands[2])))"
"#"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "8")])
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(minus:DF (match_operand:DF 3 "register_operand" "")
(mult:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "register_operand" ""))))
(set (match_operand:DF 4 "register_operand" "")
(mult:DF (match_dup 1) (match_dup 2)))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
[(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
(set (match_dup 0) (minus:DF (match_dup 3)
(mult:DF (match_dup 1) (match_dup 2))))]
"")
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
(minus:SF (match_operand:SF 3 "register_operand" "f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))))
(set (match_operand:SF 4 "register_operand" "=&f")
(mult:SF (match_dup 1) (match_dup 2)))]
"(! TARGET_SOFT_FLOAT && TARGET_PA_20
&& ! (reg_overlap_mentioned_p (operands[4], operands[1])
|| reg_overlap_mentioned_p (operands[4], operands[2])))"
"#"
[(set_attr "type" "fpmuldbl")
(set_attr "length" "8")])
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(minus:SF (match_operand:SF 3 "register_operand" "")
(mult:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "register_operand" ""))))
(set (match_operand:SF 4 "register_operand" "")
(mult:SF (match_dup 1) (match_dup 2)))]
"! TARGET_SOFT_FLOAT && TARGET_PA_20"
[(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
(set (match_dup 0) (minus:SF (match_dup 3)
(mult:SF (match_dup 1) (match_dup 2))))]
"")
(define_insn "" (define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
......
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