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riscv-gcc-1
Commit f8a1ebc6 by Jan Hubicka Committed by Jan Hubicka
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real.c (encode_ieee_extended): Initialize whole array. 

	* real.c (encode_ieee_extended): Initialize whole array.
	* reg-stack.c (move_for_stack_reg0: Use always XFmode.
	* i386-modes.def: Change definitions of TFmode and XFmode.
	* i386.c (classify_argument): Rename TFmodes to XFmodes; add new TFmode code.
	(construct_container): Allow constructing of TFmode integer containers.
	(ix86_return_in_memory):  XFmode is not returned in memory.
	(init_ext_80387_constants): Always use XFmode.
	(print_operand): Likewise.
	(ix86_prepare_fp_compare_regs): Likewise.
	(split_to_parts): Deal with TFmode.
	(split_long_move): Simplify.
	(ix86_init_mmx_sse_builtins): Add __float80, __float128.
	(ix86_memory_move_cost): Do not confuse TFmode.
	* i386.h (LONG_DOUBLE_TYPE_SIZE): Set to 96.
	(IS_STACK_MODE): TFmode is not stack mode.
	(HARD_REGNO_NREGS, CLASS_MAX_NREGS): Deal nicely with XFmode.
	(VALID_SSE_REG_MODE): Allow TFmode.
	(VALID_FP_MODE_P): Disallow TFmode.
	(VALID_INT_MODE_P): Allow TFmode in 64bit mode.
	* i386.md (TFmode patterns): Kill.
	(movtf, motf_rex64): New patterns.

From-SVN: r73099
parent 27eb8ab1
Showing with 293 additions and 1162 deletions
gcc/ChangeLog
2003-10-30 Jan Hubicka <jh@suse.cz>
* real.c (encode_ieee_extended): Initialize whole array.
* reg-stack.c (move_for_stack_reg0: Use always XFmode.
* i386-modes.def: Change definitions of TFmode and XFmode.
* i386.c (classify_argument): Rename TFmodes to XFmodes; add new TFmode code.
(construct_container): Allow constructing of TFmode integer containers.
(ix86_return_in_memory): XFmode is not returned in memory.
(init_ext_80387_constants): Always use XFmode.
(print_operand): Likewise.
(ix86_prepare_fp_compare_regs): Likewise.
(split_to_parts): Deal with TFmode.
(split_long_move): Simplify.
(ix86_init_mmx_sse_builtins): Add __float80, __float128.
(ix86_memory_move_cost): Do not confuse TFmode.
* i386.h (LONG_DOUBLE_TYPE_SIZE): Set to 96.
(IS_STACK_MODE): TFmode is not stack mode.
(HARD_REGNO_NREGS, CLASS_MAX_NREGS): Deal nicely with XFmode.
(VALID_SSE_REG_MODE): Allow TFmode.
(VALID_FP_MODE_P): Disallow TFmode.
(VALID_INT_MODE_P): Allow TFmode in 64bit mode.
* i386.md (TFmode patterns): Kill.
(movtf, motf_rex64): New patterns.
2003-10-30 Richard Sandiford <rsandifo@redhat.com> 2003-10-30 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (adddi3): Fix typo in mips16 stack pointer code. * config/mips/mips.md (adddi3): Fix typo in mips16 stack pointer code.
......
gcc/config/i386/i386-modes.def
...@@ -18,11 +18,18 @@ along with GCC; see the file COPYING. If not, write to ...@@ -18,11 +18,18 @@ along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330, the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */ Boston, MA 02111-1307, USA. */
/* By default our XFmode is the 80-bit extended format. If we use /* x86_64 ABI specifies both XF and TF modes.
TFmode instead, it's also the 80-bit format, but with padding. */ XFmode is __float80 is IEEE extended; TFmode is __float128
is IEEE quad.
IEEE extended is 128 bits wide, except in ILP32 mode, but we
have to say it's 12 bytes so that the bitsize and wider_mode
tables are correctly set up. We correct its size below. */
FLOAT_MODE (XF, 12, ieee_extended_intel_96_format); FLOAT_MODE (XF, 12, ieee_extended_intel_96_format);
FLOAT_MODE (TF, 16, ieee_extended_intel_128_format); ADJUST_BYTESIZE (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12);
ADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4);
FLOAT_MODE (TF, 16, ieee_quad_format);
/* Add any extra modes needed to represent the condition code. /* Add any extra modes needed to represent the condition code.
......
gcc/config/i386/i386.c
...@@ -1374,6 +1374,7 @@ override_options (void) ...@@ -1374,6 +1374,7 @@ override_options (void)
if (TARGET_SSE2) if (TARGET_SSE2)
target_flags |= MASK_SSE; target_flags |= MASK_SSE;
target_flags |= (MASK_128BIT_LONG_DOUBLE);
if (TARGET_64BIT) if (TARGET_64BIT)
{ {
if (TARGET_ALIGN_DOUBLE) if (TARGET_ALIGN_DOUBLE)
...@@ -2182,6 +2183,7 @@ classify_argument (enum machine_mode mode, tree type, ...@@ -2182,6 +2183,7 @@ classify_argument (enum machine_mode mode, tree type,
return 1; return 1;
case CDImode: case CDImode:
case TImode: case TImode:
case TCmode:
classes[0] = classes[1] = X86_64_INTEGER_CLASS; classes[0] = classes[1] = X86_64_INTEGER_CLASS;
return 2; return 2;
case CTImode: case CTImode:
...@@ -2197,11 +2199,15 @@ classify_argument (enum machine_mode mode, tree type, ...@@ -2197,11 +2199,15 @@ classify_argument (enum machine_mode mode, tree type,
case DFmode: case DFmode:
classes[0] = X86_64_SSEDF_CLASS; classes[0] = X86_64_SSEDF_CLASS;
return 1; return 1;
case TFmode: case XFmode:
classes[0] = X86_64_X87_CLASS; classes[0] = X86_64_X87_CLASS;
classes[1] = X86_64_X87UP_CLASS; classes[1] = X86_64_X87UP_CLASS;
return 2; return 2;
case TCmode: case TFmode:
classes[0] = X86_64_INTEGER_CLASS;
classes[1] = X86_64_INTEGER_CLASS;
return 2;
case XCmode:
classes[0] = X86_64_X87_CLASS; classes[0] = X86_64_X87_CLASS;
classes[1] = X86_64_X87UP_CLASS; classes[1] = X86_64_X87UP_CLASS;
classes[2] = X86_64_X87_CLASS; classes[2] = X86_64_X87_CLASS;
...@@ -2338,16 +2344,16 @@ construct_container (enum machine_mode mode, tree type, int in_return, ...@@ -2338,16 +2344,16 @@ construct_container (enum machine_mode mode, tree type, int in_return,
return gen_rtx_REG (mode, SSE_REGNO (sse_regno)); return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
if (n == 2 if (n == 2
&& class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS) && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
return gen_rtx_REG (TFmode, FIRST_STACK_REG); return gen_rtx_REG (XFmode, FIRST_STACK_REG);
if (n == 2 && class[0] == X86_64_INTEGER_CLASS if (n == 2 && class[0] == X86_64_INTEGER_CLASS
&& class[1] == X86_64_INTEGER_CLASS && class[1] == X86_64_INTEGER_CLASS
&& (mode == CDImode || mode == TImode) && (mode == CDImode || mode == TImode || mode == TFmode)
&& intreg[0] + 1 == intreg[1]) && intreg[0] + 1 == intreg[1])
return gen_rtx_REG (mode, intreg[0]); return gen_rtx_REG (mode, intreg[0]);
if (n == 4 if (n == 4
&& class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS
&& class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS) && class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS)
return gen_rtx_REG (TCmode, FIRST_STACK_REG); return gen_rtx_REG (XCmode, FIRST_STACK_REG);
/* Otherwise figure out the entries of the PARALLEL. */ /* Otherwise figure out the entries of the PARALLEL. */
for (i = 0; i < n; i++) for (i = 0; i < n; i++)
...@@ -2779,8 +2785,9 @@ ix86_return_in_memory (tree type) ...@@ -2779,8 +2785,9 @@ ix86_return_in_memory (tree type)
} }
} }
if (mode == TFmode) if (mode == TFmode || mode == XFmode)
return 0; return 0;
if (size > 12) if (size > 12)
return 1; return 1;
return 0; return 0;
...@@ -2800,9 +2807,24 @@ ix86_libcall_value (enum machine_mode mode) ...@@ -2800,9 +2807,24 @@ ix86_libcall_value (enum machine_mode mode)
case DFmode: case DFmode:
case DCmode: case DCmode:
return gen_rtx_REG (mode, FIRST_SSE_REG); return gen_rtx_REG (mode, FIRST_SSE_REG);
case XFmode:
case XCmode:
return gen_rtx_REG (mode, FIRST_FLOAT_REG);
case TFmode: case TFmode:
{
rtx ret = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
XVECEXP (ret, 0, 0) = gen_rtx_EXPR_LIST
(VOIDmode,
gen_rtx_REG (DImode, x86_64_int_parameter_registers [0]),
const0_rtx);
XVECEXP (ret, 0, 1) = gen_rtx_EXPR_LIST
(VOIDmode,
gen_rtx_REG (DImode, x86_64_int_parameter_registers [1]),
GEN_INT (64));
return ret;
}
case TCmode: case TCmode:
return gen_rtx_REG (mode, FIRST_FLOAT_REG); return NULL;
default: default:
return gen_rtx_REG (mode, 0); return gen_rtx_REG (mode, 0);
} }
...@@ -4257,8 +4279,7 @@ init_ext_80387_constants (void) ...@@ -4257,8 +4279,7 @@ init_ext_80387_constants (void)
real_from_string (&ext_80387_constants_table[i], cst[i]); real_from_string (&ext_80387_constants_table[i], cst[i]);
/* Ensure each constant is rounded to XFmode precision. */ /* Ensure each constant is rounded to XFmode precision. */
real_convert (&ext_80387_constants_table[i], real_convert (&ext_80387_constants_table[i],
TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode, XFmode, &ext_80387_constants_table[i]);
&ext_80387_constants_table[i]);
} }
ext_80387_constants_init = 1; ext_80387_constants_init = 1;
...@@ -4280,7 +4301,7 @@ standard_80387_constant_p (rtx x) ...@@ -4280,7 +4301,7 @@ standard_80387_constant_p (rtx x)
/* For XFmode constants, try to find a special 80387 instruction on /* For XFmode constants, try to find a special 80387 instruction on
those CPUs that benefit from them. */ those CPUs that benefit from them. */
if ((GET_MODE (x) == XFmode || GET_MODE (x) == TFmode) if (GET_MODE (x) == XFmode
&& x86_ext_80387_constants & TUNEMASK) && x86_ext_80387_constants & TUNEMASK)
{ {
REAL_VALUE_TYPE r; REAL_VALUE_TYPE r;
...@@ -4351,7 +4372,7 @@ standard_80387_constant_rtx (int idx) ...@@ -4351,7 +4372,7 @@ standard_80387_constant_rtx (int idx)
} }
return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i], return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode); XFmode);
} }
/* Return 1 if X is FP constant we can load to SSE register w/o using memory. /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
...@@ -7450,7 +7471,7 @@ print_operand (FILE *file, rtx x, int code) ...@@ -7450,7 +7471,7 @@ print_operand (FILE *file, rtx x, int code)
} }
else if (GET_CODE (x) == CONST_DOUBLE else if (GET_CODE (x) == CONST_DOUBLE
&& (GET_MODE (x) == XFmode || GET_MODE (x) == TFmode)) && GET_MODE (x) == XFmode)
{ {
char dstr[30]; char dstr[30];
...@@ -8690,7 +8711,6 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1) ...@@ -8690,7 +8711,6 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
if (!is_sse if (!is_sse
&& (fpcmp_mode == CCFPUmode && (fpcmp_mode == CCFPUmode
|| op_mode == XFmode || op_mode == XFmode
|| op_mode == TFmode
|| ix86_use_fcomi_compare (code))) || ix86_use_fcomi_compare (code)))
{ {
op0 = force_reg (op_mode, op0); op0 = force_reg (op_mode, op0);
...@@ -9165,7 +9185,6 @@ ix86_expand_branch (enum rtx_code code, rtx label) ...@@ -9165,7 +9185,6 @@ ix86_expand_branch (enum rtx_code code, rtx label)
case SFmode: case SFmode:
case DFmode: case DFmode:
case XFmode: case XFmode:
case TFmode:
{ {
rtvec vec; rtvec vec;
int use_fcomi; int use_fcomi;
...@@ -10356,7 +10375,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) ...@@ -10356,7 +10375,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
int size; int size;
if (!TARGET_64BIT) if (!TARGET_64BIT)
size = mode == TFmode ? 3 : (GET_MODE_SIZE (mode) / 4); size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
else else
size = (GET_MODE_SIZE (mode) + 4) / 8; size = (GET_MODE_SIZE (mode) + 4) / 8;
...@@ -10416,7 +10435,6 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) ...@@ -10416,7 +10435,6 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
switch (mode) switch (mode)
{ {
case XFmode: case XFmode:
case TFmode:
REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
parts[2] = gen_int_mode (l[2], SImode); parts[2] = gen_int_mode (l[2], SImode);
break; break;
...@@ -10439,18 +10457,19 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) ...@@ -10439,18 +10457,19 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
split_ti (&operand, 1, &parts[0], &parts[1]); split_ti (&operand, 1, &parts[0], &parts[1]);
if (mode == XFmode || mode == TFmode) if (mode == XFmode || mode == TFmode)
{ {
enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
if (REG_P (operand)) if (REG_P (operand))
{ {
if (!reload_completed) if (!reload_completed)
abort (); abort ();
parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0); parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1); parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
} }
else if (offsettable_memref_p (operand)) else if (offsettable_memref_p (operand))
{ {
operand = adjust_address (operand, DImode, 0); operand = adjust_address (operand, DImode, 0);
parts[0] = operand; parts[0] = operand;
parts[1] = adjust_address (operand, SImode, 8); parts[1] = adjust_address (operand, upper_mode, 8);
} }
else if (GET_CODE (operand) == CONST_DOUBLE) else if (GET_CODE (operand) == CONST_DOUBLE)
{ {
...@@ -10468,7 +10487,16 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) ...@@ -10468,7 +10487,16 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
DImode); DImode);
else else
parts[0] = immed_double_const (l[0], l[1], DImode); parts[0] = immed_double_const (l[0], l[1], DImode);
if (upper_mode == SImode)
parts[1] = gen_int_mode (l[2], SImode); parts[1] = gen_int_mode (l[2], SImode);
else if (HOST_BITS_PER_WIDE_INT >= 64)
parts[1]
= gen_int_mode
((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
+ ((((HOST_WIDE_INT) l[3]) << 31) << 1),
DImode);
else
parts[1] = immed_double_const (l[2], l[3], DImode);
} }
else else
abort (); abort ();
...@@ -10589,12 +10617,8 @@ ix86_split_long_move (rtx operands[]) ...@@ -10589,12 +10617,8 @@ ix86_split_long_move (rtx operands[])
{ {
if (nparts == 3) if (nparts == 3)
{ {
/* We use only first 12 bytes of TFmode value, but for pushing we if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
are required to adjust stack as if we were pushing real 16byte emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
value. */
if (mode == TFmode && !TARGET_64BIT)
emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
GEN_INT (-4)));
emit_move_insn (part[0][2], part[1][2]); emit_move_insn (part[0][2], part[1][2]);
} }
} }
...@@ -13305,6 +13329,27 @@ ix86_init_mmx_sse_builtins (void) ...@@ -13305,6 +13329,27 @@ ix86_init_mmx_sse_builtins (void)
tree v2di_ftype_v2di tree v2di_ftype_v2di
= build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE); = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
tree float80_type;
tree float128_type;
/* The __float80 type. */
if (TYPE_MODE (long_double_type_node) == XFmode)
(*lang_hooks.types.register_builtin_type) (long_double_type_node,
"__float80");
else
{
/* The __float80 type. */
float80_type = make_node (REAL_TYPE);
TYPE_PRECISION (float80_type) = 96;
layout_type (float80_type);
(*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
}
float128_type = make_node (REAL_TYPE);
TYPE_PRECISION (float128_type) = 128;
layout_type (float128_type);
(*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
/* Add all builtins that are more or less simple operations on two /* Add all builtins that are more or less simple operations on two
operands. */ operands. */
for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
...@@ -14745,7 +14790,6 @@ ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in) ...@@ -14745,7 +14790,6 @@ ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
index = 1; index = 1;
break; break;
case XFmode: case XFmode:
case TFmode:
index = 2; index = 2;
break; break;
default: default:
......
gcc/config/i386/i386.h
...@@ -721,16 +721,7 @@ extern int x86_prefetch_sse; ...@@ -721,16 +721,7 @@ extern int x86_prefetch_sse;
/* target machine storage layout */ /* target machine storage layout */
/* Define for XFmode or TFmode extended real floating point support. #define LONG_DOUBLE_TYPE_SIZE 96
The XFmode is specified by i386 ABI, while TFmode may be faster
due to alignment and simplifications in the address calculations. */
#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
#define MAX_LONG_DOUBLE_TYPE_SIZE 128
#ifdef __x86_64__
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
#else
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
#endif
/* Set the value of FLT_EVAL_METHOD in float.h. When using only the /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
FPU, assume that the fpcw is set to extended precision; when using FPU, assume that the fpcw is set to extended precision; when using
...@@ -900,8 +891,7 @@ extern int x86_prefetch_sse; ...@@ -900,8 +891,7 @@ extern int x86_prefetch_sse;
#define STACK_REGS #define STACK_REGS
#define IS_STACK_MODE(MODE) \ #define IS_STACK_MODE(MODE) \
((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \
|| (MODE) == TFmode)
/* Number of actual hardware registers. /* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler The hardware registers are assigned numbers for the compiler
...@@ -1049,9 +1039,9 @@ do { \ ...@@ -1049,9 +1039,9 @@ do { \
#define HARD_REGNO_NREGS(REGNO, MODE) \ #define HARD_REGNO_NREGS(REGNO, MODE) \
(FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
: ((MODE) == TFmode \ : ((MODE) == XFmode \
? (TARGET_64BIT ? 2 : 3) \ ? (TARGET_64BIT ? 2 : 3) \
: (MODE) == TCmode \ : (MODE) == XCmode \
? (TARGET_64BIT ? 4 : 6) \ ? (TARGET_64BIT ? 4 : 6) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
...@@ -1061,7 +1051,7 @@ do { \ ...@@ -1061,7 +1051,7 @@ do { \
#define VALID_SSE_REG_MODE(MODE) \ #define VALID_SSE_REG_MODE(MODE) \
((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
|| (MODE) == SFmode \ || (MODE) == SFmode || (MODE) == TFmode \
/* Always accept SSE2 modes so that xmmintrin.h compiles. */ \ /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
|| VALID_SSE2_REG_MODE (MODE) \ || VALID_SSE2_REG_MODE (MODE) \
|| (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
...@@ -1079,21 +1069,20 @@ do { \ ...@@ -1079,21 +1069,20 @@ do { \
: VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
#define VALID_FP_MODE_P(MODE) \ #define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
|| (!TARGET_64BIT && (MODE) == XFmode) \ || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
|| (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
|| (!TARGET_64BIT && (MODE) == XCmode))
#define VALID_INT_MODE_P(MODE) \ #define VALID_INT_MODE_P(MODE) \
((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
|| (MODE) == DImode \ || (MODE) == DImode \
|| (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
|| (MODE) == CDImode \ || (MODE) == CDImode \
|| (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
|| (MODE) == TFmode || (MODE) == TCmode)))
/* Return true for modes passed in SSE registers. */ /* Return true for modes passed in SSE registers. */
#define SSE_REG_MODE_P(MODE) \ #define SSE_REG_MODE_P(MODE) \
((MODE) == TImode || (MODE) == V16QImode \ ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
|| (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
|| (MODE) == V4SFmode || (MODE) == V4SImode) || (MODE) == V4SFmode || (MODE) == V4SImode)
...@@ -1568,14 +1557,11 @@ enum reg_class ...@@ -1568,14 +1557,11 @@ enum reg_class
/* Return the maximum number of consecutive registers /* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */ needed to represent mode MODE in a register of class CLASS. */
/* On the 80386, this is the size of MODE in words, /* On the 80386, this is the size of MODE in words,
except in the FP regs, where a single reg is always enough. except in the FP regs, where a single reg is always enough. */
The TFmodes are really just 80bit values, so we use only 3 registers
to hold them, instead of 4, as the size would suggest.
*/
#define CLASS_MAX_NREGS(CLASS, MODE) \ #define CLASS_MAX_NREGS(CLASS, MODE) \
(!MAYBE_INTEGER_CLASS_P (CLASS) \ (!MAYBE_INTEGER_CLASS_P (CLASS) \
? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
: ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
+ UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* A C expression whose value is nonzero if pseudos that have been /* A C expression whose value is nonzero if pseudos that have been
......
gcc/config/i386/i386.md
...@@ -716,17 +716,6 @@ ...@@ -716,17 +716,6 @@
[(set (reg:CC 17) [(set (reg:CC 17)
(compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "") (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
(match_operand:XF 1 "cmp_fp_expander_operand" "")))] (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
{
ix86_compare_op0 = operands[0];
ix86_compare_op1 = operands[1];
DONE;
})
(define_expand "cmptf"
[(set (reg:CC 17)
(compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
(match_operand:TF 1 "cmp_fp_expander_operand" "")))]
"TARGET_80387" "TARGET_80387"
{ {
ix86_compare_op0 = operands[0]; ix86_compare_op0 = operands[0];
...@@ -850,16 +839,6 @@ ...@@ -850,16 +839,6 @@
(compare:CCFP (compare:CCFP
(match_operand:XF 0 "register_operand" "f") (match_operand:XF 0 "register_operand" "f")
(match_operand:XF 1 "register_operand" "f")))] (match_operand:XF 1 "register_operand" "f")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "fcmp")
(set_attr "mode" "XF")])
(define_insn "*cmpfp_2_tf"
[(set (reg:CCFP 18)
(compare:CCFP
(match_operand:TF 0 "register_operand" "f")
(match_operand:TF 1 "register_operand" "f")))]
"TARGET_80387" "TARGET_80387"
"* return output_fp_compare (insn, operands, 0, 0);" "* return output_fp_compare (insn, operands, 0, 0);"
[(set_attr "type" "fcmp") [(set_attr "type" "fcmp")
...@@ -872,18 +851,6 @@ ...@@ -872,18 +851,6 @@
(match_operand:XF 1 "register_operand" "f") (match_operand:XF 1 "register_operand" "f")
(match_operand:XF 2 "register_operand" "f"))] (match_operand:XF 2 "register_operand" "f"))]
UNSPEC_FNSTSW))] UNSPEC_FNSTSW))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi")
(set_attr "mode" "XF")])
(define_insn "*cmpfp_2_tf_1"
[(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI
[(compare:CCFP
(match_operand:TF 1 "register_operand" "f")
(match_operand:TF 2 "register_operand" "f"))]
UNSPEC_FNSTSW))]
"TARGET_80387" "TARGET_80387"
"* return output_fp_compare (insn, operands, 2, 0);" "* return output_fp_compare (insn, operands, 2, 0);"
[(set_attr "type" "multi") [(set_attr "type" "multi")
...@@ -2744,14 +2711,8 @@ ...@@ -2744,14 +2711,8 @@
(define_expand "movxf" (define_expand "movxf"
[(set (match_operand:XF 0 "nonimmediate_operand" "") [(set (match_operand:XF 0 "nonimmediate_operand" "")
(match_operand:XF 1 "general_operand" ""))] (match_operand:XF 1 "general_operand" ""))]
"!TARGET_128BIT_LONG_DOUBLE"
"ix86_expand_move (XFmode, operands); DONE;")
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "general_operand" ""))]
"" ""
"ix86_expand_move (TFmode, operands); DONE;") "ix86_expand_move (XFmode, operands); DONE;")
;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size. ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
;; Size of pushdf using integer instructions is 3+3*memory operand size ;; Size of pushdf using integer instructions is 3+3*memory operand size
...@@ -2763,17 +2724,6 @@ ...@@ -2763,17 +2724,6 @@
(define_insn "*pushxf_nointeger" (define_insn "*pushxf_nointeger"
[(set (match_operand:XF 0 "push_operand" "=X,X,X") [(set (match_operand:XF 0 "push_operand" "=X,X,X")
(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))] (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
"!TARGET_128BIT_LONG_DOUBLE && optimize_size"
{
/* This insn should be already splitted before reg-stack. */
abort ();
}
[(set_attr "type" "multi")
(set_attr "mode" "XF,SI,SI")])
(define_insn "*pushtf_nointeger"
[(set (match_operand:TF 0 "push_operand" "=<,<,<")
(match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
"optimize_size" "optimize_size"
{ {
/* This insn should be already splitted before reg-stack. */ /* This insn should be already splitted before reg-stack. */
...@@ -2785,17 +2735,6 @@ ...@@ -2785,17 +2735,6 @@
(define_insn "*pushxf_integer" (define_insn "*pushxf_integer"
[(set (match_operand:XF 0 "push_operand" "=<,<") [(set (match_operand:XF 0 "push_operand" "=<,<")
(match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))] (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
"!TARGET_128BIT_LONG_DOUBLE && !optimize_size"
{
/* This insn should be already splitted before reg-stack. */
abort ();
}
[(set_attr "type" "multi")
(set_attr "mode" "XF,SI")])
(define_insn "*pushtf_integer"
[(set (match_operand:TF 0 "push_operand" "=<,<")
(match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
"!optimize_size" "!optimize_size"
{ {
/* This insn should be already splitted before reg-stack. */ /* This insn should be already splitted before reg-stack. */
...@@ -2809,7 +2748,6 @@ ...@@ -2809,7 +2748,6 @@
(match_operand 1 "general_operand" ""))] (match_operand 1 "general_operand" ""))]
"reload_completed "reload_completed
&& (GET_MODE (operands[0]) == XFmode && (GET_MODE (operands[0]) == XFmode
|| GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == DFmode) || GET_MODE (operands[0]) == DFmode)
&& !ANY_FP_REG_P (operands[1])" && !ANY_FP_REG_P (operands[1])"
[(const_int 0)] [(const_int 0)]
...@@ -2818,30 +2756,24 @@ ...@@ -2818,30 +2756,24 @@
(define_split (define_split
[(set (match_operand:XF 0 "push_operand" "") [(set (match_operand:XF 0 "push_operand" "")
(match_operand:XF 1 "any_fp_register_operand" ""))] (match_operand:XF 1 "any_fp_register_operand" ""))]
"!TARGET_128BIT_LONG_DOUBLE"
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
(set (mem:XF (reg:SI 7)) (match_dup 1))])
(define_split
[(set (match_operand:TF 0 "push_operand" "")
(match_operand:TF 1 "any_fp_register_operand" ""))]
"!TARGET_64BIT" "!TARGET_64BIT"
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16))) [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
(set (mem:TF (reg:SI 7)) (match_dup 1))]) (set (mem:XF (reg:SI 7)) (match_dup 1))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_split (define_split
[(set (match_operand:TF 0 "push_operand" "") [(set (match_operand:XF 0 "push_operand" "")
(match_operand:TF 1 "any_fp_register_operand" ""))] (match_operand:XF 1 "any_fp_register_operand" ""))]
"TARGET_64BIT" "TARGET_64BIT"
[(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
(set (mem:TF (reg:DI 7)) (match_dup 1))]) (set (mem:XF (reg:DI 7)) (match_dup 1))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
;; Do not use integer registers when optimizing for size ;; Do not use integer registers when optimizing for size
(define_insn "*movxf_nointeger" (define_insn "*movxf_nointeger"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o") [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))] (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
"!TARGET_128BIT_LONG_DOUBLE "optimize_size
&& optimize_size
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& (reload_in_progress || reload_completed && (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE || GET_CODE (operands[1]) != CONST_DOUBLE
...@@ -2882,56 +2814,10 @@ ...@@ -2882,56 +2814,10 @@
[(set_attr "type" "fmov,fmov,fmov,multi,multi") [(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")]) (set_attr "mode" "XF,XF,XF,SI,SI")])
(define_insn "*movtf_nointeger"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
(match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& optimize_size
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| memory_operand (operands[0], TFmode))"
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
{
if (REGNO (operands[0]) == FIRST_STACK_REG
&& TARGET_USE_FFREEP)
return "ffreep\t%y0";
return "fstp\t%y0";
}
else if (STACK_TOP_P (operands[0]))
return "fld%z1\t%y1";
else
return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0\;fld%z0\t%y0";
else
return "fstp%z0\t%y0";
case 2:
return standard_80387_constant_opcode (operands[1]);
case 3: case 4:
return "#";
}
abort();
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
(define_insn "*movxf_integer" (define_insn "*movxf_integer"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o") [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
(match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))] (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
"!TARGET_128BIT_LONG_DOUBLE "!optimize_size
&& !optimize_size
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& (reload_in_progress || reload_completed && (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE || GET_CODE (operands[1]) != CONST_DOUBLE
...@@ -2972,57 +2858,12 @@ ...@@ -2972,57 +2858,12 @@
[(set_attr "type" "fmov,fmov,fmov,multi,multi") [(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")]) (set_attr "mode" "XF,XF,XF,SI,SI")])
(define_insn "*movtf_integer"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
(match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& !optimize_size
&& (reload_in_progress || reload_completed
|| GET_CODE (operands[1]) != CONST_DOUBLE
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| memory_operand (operands[0], TFmode))"
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
{
if (REGNO (operands[0]) == FIRST_STACK_REG
&& TARGET_USE_FFREEP)
return "ffreep\t%y0";
return "fstp\t%y0";
}
else if (STACK_TOP_P (operands[0]))
return "fld%z1\t%y1";
else
return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0\;fld%z0\t%y0";
else
return "fstp%z0\t%y0";
case 2:
return standard_80387_constant_opcode (operands[1]);
case 3: case 4:
return "#";
}
abort();
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi")
(set_attr "mode" "XF,XF,XF,SI,SI")])
(define_split (define_split
[(set (match_operand 0 "nonimmediate_operand" "") [(set (match_operand 0 "nonimmediate_operand" "")
(match_operand 1 "general_operand" ""))] (match_operand 1 "general_operand" ""))]
"reload_completed "reload_completed
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode) && GET_MODE (operands[0]) == XFmode
&& ! (ANY_FP_REG_P (operands[0]) || && ! (ANY_FP_REG_P (operands[0]) ||
(GET_CODE (operands[0]) == SUBREG (GET_CODE (operands[0]) == SUBREG
&& ANY_FP_REG_P (SUBREG_REG (operands[0])))) && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
...@@ -3037,7 +2878,7 @@ ...@@ -3037,7 +2878,7 @@
(match_operand 1 "memory_operand" ""))] (match_operand 1 "memory_operand" ""))]
"reload_completed "reload_completed
&& GET_CODE (operands[1]) == MEM && GET_CODE (operands[1]) == MEM
&& (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode && (GET_MODE (operands[0]) == XFmode
|| GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode) || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)) && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
...@@ -3068,21 +2909,6 @@ ...@@ -3068,21 +2909,6 @@
[(set_attr "type" "fxch") [(set_attr "type" "fxch")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
(define_insn "swaptf"
[(set (match_operand:TF 0 "register_operand" "+f")
(match_operand:TF 1 "register_operand" "+f"))
(set (match_dup 1)
(match_dup 0))]
""
{
if (STACK_TOP_P (operands[0]))
return "fxch\t%1";
else
return "fxch\t%0";
}
[(set_attr "type" "fxch")
(set_attr "mode" "XF")])
;; Zero extension instructions ;; Zero extension instructions
(define_expand "zero_extendhisi2" (define_expand "zero_extendhisi2"
...@@ -3632,62 +3458,34 @@ ...@@ -3632,62 +3458,34 @@
(define_split (define_split
[(set (match_operand:XF 0 "push_operand" "") [(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))] (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE" ""
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
(set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_insn "*dummy_extendsftf2"
[(set (match_operand:TF 0 "push_operand" "=<")
(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
"0"
"#")
(define_split
[(set (match_operand:TF 0 "push_operand" "")
(float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
"!TARGET_64BIT"
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
(define_split (define_split
[(set (match_operand:TF 0 "push_operand" "") [(set (match_operand:XF 0 "push_operand" "")
(float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))] (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
"TARGET_64BIT" "TARGET_64BIT"
[(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
(set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_insn "*dummy_extenddfxf2"
[(set (match_operand:XF 0 "push_operand" "=<")
(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
"0"
"#")
(define_split (define_split
[(set (match_operand:XF 0 "push_operand" "") [(set (match_operand:XF 0 "push_operand" "")
(float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))] (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE" ""
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12))) [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
(set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]) (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_insn "*dummy_extenddftf2"
[(set (match_operand:TF 0 "push_operand" "=<")
(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
"0"
"#")
(define_split
[(set (match_operand:TF 0 "push_operand" "")
(float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
"!TARGET_64BIT"
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
(define_split (define_split
[(set (match_operand:TF 0 "push_operand" "") [(set (match_operand:XF 0 "push_operand" "")
(float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))] (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
"TARGET_64BIT" "TARGET_64BIT"
[(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
(set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))]) (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
(define_expand "extendsfdf2" (define_expand "extendsfdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "") [(set (match_operand:DF 0 "nonimmediate_operand" "")
...@@ -3747,7 +3545,7 @@ ...@@ -3747,7 +3545,7 @@
(define_expand "extendsfxf2" (define_expand "extendsfxf2"
[(set (match_operand:XF 0 "nonimmediate_operand" "") [(set (match_operand:XF 0 "nonimmediate_operand" "")
(float_extend:XF (match_operand:SF 1 "general_operand" "")))] (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
{ {
/* ??? Needed for compress_float_constant since all fp constants /* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */ are LEGITIMATE_CONSTANT_P. */
...@@ -3760,51 +3558,6 @@ ...@@ -3760,51 +3558,6 @@
(define_insn "*extendsfxf2_1" (define_insn "*extendsfxf2_1"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))] (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
return "fld%z1\t%y1";
else
return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0\n\tfld%z0\t%y0";
else
return "fstp%z0\t%y0";
default:
abort ();
}
}
[(set_attr "type" "fmov")
(set_attr "mode" "SF,XF")])
(define_expand "extendsftf2"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(float_extend:TF (match_operand:SF 1 "general_operand" "")))]
"TARGET_80387"
{
/* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */
if (GET_CODE (operands[1]) == CONST_DOUBLE)
operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (SFmode, operands[1]);
})
(define_insn "*extendsftf2_1"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387 "TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{ {
...@@ -3837,7 +3590,7 @@ ...@@ -3837,7 +3590,7 @@
(define_expand "extenddfxf2" (define_expand "extenddfxf2"
[(set (match_operand:XF 0 "nonimmediate_operand" "") [(set (match_operand:XF 0 "nonimmediate_operand" "")
(float_extend:XF (match_operand:DF 1 "general_operand" "")))] (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
{ {
/* ??? Needed for compress_float_constant since all fp constants /* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */ are LEGITIMATE_CONSTANT_P. */
...@@ -3850,51 +3603,6 @@ ...@@ -3850,51 +3603,6 @@
(define_insn "*extenddfxf2_1" (define_insn "*extenddfxf2_1"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m") [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))] (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
{
case 0:
if (REG_P (operands[1])
&& find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp\t%y0";
else if (STACK_TOP_P (operands[0]))
return "fld%z1\t%y1";
else
return "fst\t%y0";
case 1:
/* There is no non-popping store to memory for XFmode. So if
we need one, follow the store with a load. */
if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0\n\tfld%z0\t%y0";
else
return "fstp%z0\t%y0";
default:
abort ();
}
}
[(set_attr "type" "fmov")
(set_attr "mode" "DF,XF")])
(define_expand "extenddftf2"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(float_extend:TF (match_operand:DF 1 "general_operand" "")))]
"TARGET_80387"
{
/* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */
if (GET_CODE (operands[1]) == CONST_DOUBLE)
operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
operands[1] = force_reg (DFmode, operands[1]);
})
(define_insn "*extenddftf2_1"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387 "TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{ {
...@@ -4139,105 +3847,43 @@ ...@@ -4139,105 +3847,43 @@
(match_operand:DF 1 "nonimmediate_operand" "")))] (match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_80387 && reload_completed "TARGET_80387 && reload_completed
&& SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
[(const_int 0)] [(const_int 0)]
{ {
rtx src, dest; rtx src, dest;
dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0); src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
/* simplify_gen_subreg refuses to widen memory references. */ /* simplify_gen_subreg refuses to widen memory references. */
if (GET_CODE (src) == SUBREG) if (GET_CODE (src) == SUBREG)
alter_subreg (&src); alter_subreg (&src);
if (reg_overlap_mentioned_p (operands[0], operands[1])) if (reg_overlap_mentioned_p (operands[0], operands[1]))
abort (); abort ();
emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode))); emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
emit_insn (gen_cvtsd2ss (dest, dest, src)); emit_insn (gen_cvtsd2ss (dest, dest, src));
DONE; DONE;
}) })
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF
(match_operand:DF 1 "fp_register_operand" "")))
(clobber (match_operand:SF 2 "memory_operand" ""))]
"TARGET_80387 && reload_completed"
[(set (match_dup 2) (float_truncate:SF (match_dup 1)))
(set (match_dup 0) (match_dup 2))]
"")
(define_expand "truncxfsf2"
[(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
(float_truncate:SF
(match_operand:XF 1 "register_operand" "")))
(clobber (match_dup 2))])]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"operands[2] = assign_386_stack_local (SFmode, 0);")
(define_insn "*truncxfsf2_1"
[(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
(float_truncate:SF
(match_operand:XF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
default:
abort();
}
}
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "SF")])
(define_insn "*truncxfsf2_2"
[(set (match_operand:SF 0 "memory_operand" "=m")
(float_truncate:SF
(match_operand:XF 1 "register_operand" "f")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
}
[(set_attr "type" "fmov")
(set_attr "mode" "SF")])
(define_split
[(set (match_operand:SF 0 "memory_operand" "")
(float_truncate:SF
(match_operand:XF 1 "register_operand" "")))
(clobber (match_operand:SF 2 "memory_operand" ""))]
"TARGET_80387"
[(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
"")
(define_split (define_split
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (float_truncate:SF
(match_operand:XF 1 "register_operand" ""))) (match_operand:DF 1 "fp_register_operand" "")))
(clobber (match_operand:SF 2 "memory_operand" ""))] (clobber (match_operand:SF 2 "memory_operand" ""))]
"TARGET_80387 && reload_completed" "TARGET_80387 && reload_completed"
[(set (match_dup 2) (float_truncate:SF (match_dup 1))) [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
(set (match_dup 0) (match_dup 2))] (set (match_dup 0) (match_dup 2))]
"") "")
(define_expand "trunctfsf2" (define_expand "truncxfsf2"
[(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
(float_truncate:SF (float_truncate:SF
(match_operand:TF 1 "register_operand" ""))) (match_operand:XF 1 "register_operand" "")))
(clobber (match_dup 2))])] (clobber (match_dup 2))])]
"TARGET_80387" "TARGET_80387"
"operands[2] = assign_386_stack_local (SFmode, 0);") "operands[2] = assign_386_stack_local (SFmode, 0);")
(define_insn "*trunctfsf2_1" (define_insn "*truncxfsf2_1"
[(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf") [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
(float_truncate:SF (float_truncate:SF
(match_operand:TF 1 "register_operand" "f,f,f,f"))) (match_operand:XF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))] (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_80387" "TARGET_80387"
{ {
...@@ -4255,10 +3901,10 @@ ...@@ -4255,10 +3901,10 @@
[(set_attr "type" "fmov,multi,multi,multi") [(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*trunctfsf2_2" (define_insn "*truncxfsf2_2"
[(set (match_operand:SF 0 "memory_operand" "=m") [(set (match_operand:SF 0 "memory_operand" "=m")
(float_truncate:SF (float_truncate:SF
(match_operand:TF 1 "register_operand" "f")))] (match_operand:XF 1 "register_operand" "f")))]
"TARGET_80387" "TARGET_80387"
{ {
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
...@@ -4272,7 +3918,7 @@ ...@@ -4272,7 +3918,7 @@
(define_split (define_split
[(set (match_operand:SF 0 "memory_operand" "") [(set (match_operand:SF 0 "memory_operand" "")
(float_truncate:SF (float_truncate:SF
(match_operand:TF 1 "register_operand" ""))) (match_operand:XF 1 "register_operand" "")))
(clobber (match_operand:SF 2 "memory_operand" ""))] (clobber (match_operand:SF 2 "memory_operand" ""))]
"TARGET_80387" "TARGET_80387"
[(set (match_dup 0) (float_truncate:SF (match_dup 1)))] [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
...@@ -4281,20 +3927,19 @@ ...@@ -4281,20 +3927,19 @@
(define_split (define_split
[(set (match_operand:SF 0 "register_operand" "") [(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (float_truncate:SF
(match_operand:TF 1 "register_operand" ""))) (match_operand:XF 1 "register_operand" "")))
(clobber (match_operand:SF 2 "memory_operand" ""))] (clobber (match_operand:SF 2 "memory_operand" ""))]
"TARGET_80387 && reload_completed" "TARGET_80387 && reload_completed"
[(set (match_dup 2) (float_truncate:SF (match_dup 1))) [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
(set (match_dup 0) (match_dup 2))] (set (match_dup 0) (match_dup 2))]
"") "")
(define_expand "truncxfdf2" (define_expand "truncxfdf2"
[(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
(float_truncate:DF (float_truncate:DF
(match_operand:XF 1 "register_operand" ""))) (match_operand:XF 1 "register_operand" "")))
(clobber (match_dup 2))])] (clobber (match_dup 2))])]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
"operands[2] = assign_386_stack_local (DFmode, 0);") "operands[2] = assign_386_stack_local (DFmode, 0);")
(define_insn "*truncxfdf2_1" (define_insn "*truncxfdf2_1"
...@@ -4302,7 +3947,7 @@ ...@@ -4302,7 +3947,7 @@
(float_truncate:DF (float_truncate:DF
(match_operand:XF 1 "register_operand" "f,f,f,f"))) (match_operand:XF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))] (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
{ {
switch (which_alternative) switch (which_alternative)
{ {
...@@ -4323,7 +3968,7 @@ ...@@ -4323,7 +3968,7 @@
[(set (match_operand:DF 0 "memory_operand" "=m") [(set (match_operand:DF 0 "memory_operand" "=m")
(float_truncate:DF (float_truncate:DF
(match_operand:XF 1 "register_operand" "f")))] (match_operand:XF 1 "register_operand" "f")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
{ {
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0"; return "fstp%z0\t%y0";
...@@ -4352,69 +3997,6 @@ ...@@ -4352,69 +3997,6 @@
(set (match_dup 0) (match_dup 2))] (set (match_dup 0) (match_dup 2))]
"") "")
(define_expand "trunctfdf2"
[(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
(float_truncate:DF
(match_operand:TF 1 "register_operand" "")))
(clobber (match_dup 2))])]
"TARGET_80387"
"operands[2] = assign_386_stack_local (DFmode, 0);")
(define_insn "*trunctfdf2_1"
[(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
(float_truncate:DF
(match_operand:TF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
"TARGET_80387"
{
switch (which_alternative)
{
case 0:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
default:
abort();
}
abort ();
}
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "DF")])
(define_insn "*trunctfdf2_2"
[(set (match_operand:DF 0 "memory_operand" "=m")
(float_truncate:DF
(match_operand:TF 1 "register_operand" "f")))]
"TARGET_80387"
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
}
[(set_attr "type" "fmov")
(set_attr "mode" "DF")])
(define_split
[(set (match_operand:DF 0 "memory_operand" "")
(float_truncate:DF
(match_operand:TF 1 "register_operand" "")))
(clobber (match_operand:DF 2 "memory_operand" ""))]
"TARGET_80387"
[(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
"")
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF
(match_operand:TF 1 "register_operand" "")))
(clobber (match_operand:DF 2 "memory_operand" ""))]
"TARGET_80387 && reload_completed"
[(set (match_dup 2) (float_truncate:DF (match_dup 1)))
(set (match_dup 0) (match_dup 2))]
"")
;; %%% Break up all these bad boys. ;; %%% Break up all these bad boys.
...@@ -4423,12 +4005,6 @@ ...@@ -4423,12 +4005,6 @@
(define_expand "fix_truncxfdi2" (define_expand "fix_truncxfdi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "") [(set (match_operand:DI 0 "nonimmediate_operand" "")
(fix:DI (match_operand:XF 1 "register_operand" "")))] (fix:DI (match_operand:XF 1 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"")
(define_expand "fix_trunctfdi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(fix:DI (match_operand:TF 1 "register_operand" "")))]
"TARGET_80387" "TARGET_80387"
"") "")
...@@ -4590,12 +4166,6 @@ ...@@ -4590,12 +4166,6 @@
(define_expand "fix_truncxfsi2" (define_expand "fix_truncxfsi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "") [(set (match_operand:SI 0 "nonimmediate_operand" "")
(fix:SI (match_operand:XF 1 "register_operand" "")))] (fix:SI (match_operand:XF 1 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"")
(define_expand "fix_trunctfsi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(fix:SI (match_operand:TF 1 "register_operand" "")))]
"TARGET_80387" "TARGET_80387"
"") "")
...@@ -4751,12 +4321,6 @@ ...@@ -4751,12 +4321,6 @@
(define_expand "fix_truncxfhi2" (define_expand "fix_truncxfhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "") [(set (match_operand:HI 0 "nonimmediate_operand" "")
(fix:HI (match_operand:XF 1 "register_operand" "")))] (fix:HI (match_operand:XF 1 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"")
(define_expand "fix_trunctfhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(fix:HI (match_operand:TF 1 "register_operand" "")))]
"TARGET_80387" "TARGET_80387"
"") "")
...@@ -5103,17 +4667,6 @@ ...@@ -5103,17 +4667,6 @@
(define_insn "floathixf2" (define_insn "floathixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(set_attr "fp_int_src" "true")])
(define_insn "floathitf2"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387" "TARGET_80387"
"@ "@
fild%z1\t%1 fild%z1\t%1
...@@ -5125,17 +4678,6 @@ ...@@ -5125,17 +4678,6 @@
(define_insn "floatsixf2" (define_insn "floatsixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(set_attr "fp_int_src" "true")])
(define_insn "floatsitf2"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387" "TARGET_80387"
"@ "@
fild%z1\t%1 fild%z1\t%1
...@@ -5147,17 +4689,6 @@ ...@@ -5147,17 +4689,6 @@
(define_insn "floatdixf2" (define_insn "floatdixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"@
fild%z1\t%1
#"
[(set_attr "type" "fmov,multi")
(set_attr "mode" "XF")
(set_attr "fp_int_src" "true")])
(define_insn "floatditf2"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
"TARGET_80387" "TARGET_80387"
"@ "@
fild%z1\t%1 fild%z1\t%1
...@@ -6858,13 +6389,6 @@ ...@@ -6858,13 +6389,6 @@
[(set (match_operand:XF 0 "register_operand" "") [(set (match_operand:XF 0 "register_operand" "")
(plus:XF (match_operand:XF 1 "register_operand" "") (plus:XF (match_operand:XF 1 "register_operand" "")
(match_operand:XF 2 "register_operand" "")))] (match_operand:XF 2 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"")
(define_expand "addtf3"
[(set (match_operand:TF 0 "register_operand" "")
(plus:TF (match_operand:TF 1 "register_operand" "")
(match_operand:TF 2 "register_operand" "")))]
"TARGET_80387" "TARGET_80387"
"") "")
...@@ -7211,13 +6735,6 @@ ...@@ -7211,13 +6735,6 @@
[(set (match_operand:XF 0 "register_operand" "") [(set (match_operand:XF 0 "register_operand" "")
(minus:XF (match_operand:XF 1 "register_operand" "") (minus:XF (match_operand:XF 1 "register_operand" "")
(match_operand:XF 2 "register_operand" "")))] (match_operand:XF 2 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"")
(define_expand "subtf3"
[(set (match_operand:TF 0 "register_operand" "")
(minus:TF (match_operand:TF 1 "register_operand" "")
(match_operand:TF 2 "register_operand" "")))]
"TARGET_80387" "TARGET_80387"
"") "")
...@@ -7729,13 +7246,6 @@ ...@@ -7729,13 +7246,6 @@
[(set (match_operand:XF 0 "register_operand" "") [(set (match_operand:XF 0 "register_operand" "")
(mult:XF (match_operand:XF 1 "register_operand" "") (mult:XF (match_operand:XF 1 "register_operand" "")
(match_operand:XF 2 "register_operand" "")))] (match_operand:XF 2 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"")
(define_expand "multf3"
[(set (match_operand:TF 0 "register_operand" "")
(mult:TF (match_operand:TF 1 "register_operand" "")
(match_operand:TF 2 "register_operand" "")))]
"TARGET_80387" "TARGET_80387"
"") "")
...@@ -7783,13 +7293,6 @@ ...@@ -7783,13 +7293,6 @@
[(set (match_operand:XF 0 "register_operand" "") [(set (match_operand:XF 0 "register_operand" "")
(div:XF (match_operand:XF 1 "register_operand" "") (div:XF (match_operand:XF 1 "register_operand" "")
(match_operand:XF 2 "register_operand" "")))] (match_operand:XF 2 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"")
(define_expand "divtf3"
[(set (match_operand:TF 0 "register_operand" "")
(div:TF (match_operand:TF 1 "register_operand" "")
(match_operand:TF 2 "register_operand" "")))]
"TARGET_80387" "TARGET_80387"
"") "")
...@@ -10018,8 +9521,7 @@ ...@@ -10018,8 +9521,7 @@
{ {
int size = GET_MODE_SIZE (GET_MODE (operands[1])); int size = GET_MODE_SIZE (GET_MODE (operands[1]));
/* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ if (GET_MODE (operands[1]) == XFmode)
if (size >= 12)
size = 10; size = 10;
operands[0] = adjust_address (operands[0], QImode, size - 1); operands[0] = adjust_address (operands[0], QImode, size - 1);
operands[1] = gen_int_mode (0x80, QImode); operands[1] = gen_int_mode (0x80, QImode);
...@@ -10196,15 +9698,8 @@ ...@@ -10196,15 +9698,8 @@
[(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
(clobber (reg:CC 17))])] (clobber (reg:CC 17))])]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
(define_expand "negtf2"
[(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
(neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
(clobber (reg:CC 17))])]
"TARGET_80387" "TARGET_80387"
"ix86_expand_unary_operator (NEG, TFmode, operands); DONE;") "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
;; Keep 'f' and 'r' in separate alternatives to avoid reload problems ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
;; because of secondary memory needed to reload from class FLOAT_INT_REGS ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
...@@ -10213,7 +9708,7 @@ ...@@ -10213,7 +9708,7 @@
[(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 "TARGET_80387
&& ix86_unary_operator_ok (NEG, XFmode, operands)" && ix86_unary_operator_ok (NEG, XFmode, operands)"
"#") "#")
...@@ -10237,36 +9732,6 @@ ...@@ -10237,36 +9732,6 @@
operands[0] = gen_rtx_REG (SImode, operands[0] = gen_rtx_REG (SImode,
true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
;; because of secondary memory needed to reload from class FLOAT_INT_REGS
;; to itself.
(define_insn "*negtf2_if"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
(neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
(clobber (reg:CC 17))]
"TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
"#")
(define_split
[(set (match_operand:TF 0 "fp_register_operand" "")
(neg:TF (match_operand:TF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(neg:TF (match_dup 1)))]
"")
(define_split
[(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
(neg:TF (match_operand:TF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (0x8000);
operands[0] = gen_rtx_REG (SImode,
true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
;; Conditionalize these after reload. If they matches before reload, we ;; Conditionalize these after reload. If they matches before reload, we
;; lose the clobber and ability to use integer instructions. ;; lose the clobber and ability to use integer instructions.
...@@ -10301,7 +9766,7 @@ ...@@ -10301,7 +9766,7 @@
(define_insn "*negxf2_1" (define_insn "*negxf2_1"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(neg:XF (match_operand:XF 1 "register_operand" "0")))] (neg:XF (match_operand:XF 1 "register_operand" "0")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed" "TARGET_80387 && reload_completed"
"fchs" "fchs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "mode" "XF") (set_attr "mode" "XF")
...@@ -10311,7 +9776,7 @@ ...@@ -10311,7 +9776,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(neg:XF (float_extend:XF (neg:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))] (match_operand:DF 1 "register_operand" "0"))))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
"fchs" "fchs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "mode" "XF") (set_attr "mode" "XF")
...@@ -10321,35 +9786,6 @@ ...@@ -10321,35 +9786,6 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(neg:XF (float_extend:XF (neg:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))] (match_operand:SF 1 "register_operand" "0"))))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"fchs"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")
(set_attr "ppro_uops" "few")])
(define_insn "*negtf2_1"
[(set (match_operand:TF 0 "register_operand" "=f")
(neg:TF (match_operand:TF 1 "register_operand" "0")))]
"TARGET_80387 && reload_completed"
"fchs"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")
(set_attr "ppro_uops" "few")])
(define_insn "*negextenddftf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(neg:TF (float_extend:TF
(match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387"
"fchs"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")
(set_attr "ppro_uops" "few")])
(define_insn "*negextendsftf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(neg:TF (float_extend:TF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387" "TARGET_80387"
"fchs" "fchs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
...@@ -10491,8 +9927,7 @@ ...@@ -10491,8 +9927,7 @@
{ {
int size = GET_MODE_SIZE (GET_MODE (operands[1])); int size = GET_MODE_SIZE (GET_MODE (operands[1]));
/* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */ if (GET_MODE (operands[1]) == XFmode)
if (size >= 12)
size = 10; size = 10;
operands[0] = adjust_address (operands[0], QImode, size - 1); operands[0] = adjust_address (operands[0], QImode, size - 1);
operands[1] = gen_int_mode (~0x80, QImode); operands[1] = gen_int_mode (~0x80, QImode);
...@@ -10658,15 +10093,8 @@ ...@@ -10658,15 +10093,8 @@
[(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
(neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
(clobber (reg:CC 17))])] (clobber (reg:CC 17))])]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
(define_expand "abstf2"
[(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
(neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
(clobber (reg:CC 17))])]
"TARGET_80387" "TARGET_80387"
"ix86_expand_unary_operator (ABS, TFmode, operands); DONE;") "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
;; Keep 'f' and 'r' in separate alternatives to avoid reload problems ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
;; because of secondary memory needed to reload from class FLOAT_INT_REGS ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
...@@ -10675,7 +10103,7 @@ ...@@ -10675,7 +10103,7 @@
[(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
(abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 "TARGET_80387
&& ix86_unary_operator_ok (ABS, XFmode, operands)" && ix86_unary_operator_ok (ABS, XFmode, operands)"
"#") "#")
...@@ -10699,33 +10127,6 @@ ...@@ -10699,33 +10127,6 @@
operands[0] = gen_rtx_REG (SImode, operands[0] = gen_rtx_REG (SImode,
true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
(define_insn "*abstf2_if"
[(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
(abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
(clobber (reg:CC 17))]
"TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
"#")
(define_split
[(set (match_operand:TF 0 "fp_register_operand" "")
(abs:TF (match_operand:TF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed"
[(set (match_dup 0)
(abs:TF (match_dup 1)))]
"")
(define_split
[(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
(abs:TF (match_operand:TF 1 "register_operand" "")))
(clobber (reg:CC 17))]
"TARGET_80387 && reload_completed"
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
(clobber (reg:CC 17))])]
"operands[1] = GEN_INT (~0x8000);
operands[0] = gen_rtx_REG (SImode,
true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
(define_insn "*abssf2_1" (define_insn "*abssf2_1"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(abs:SF (match_operand:SF 1 "register_operand" "0")))] (abs:SF (match_operand:SF 1 "register_operand" "0")))]
...@@ -10754,7 +10155,7 @@ ...@@ -10754,7 +10155,7 @@
(define_insn "*absxf2_1" (define_insn "*absxf2_1"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(abs:XF (match_operand:XF 1 "register_operand" "0")))] (abs:XF (match_operand:XF 1 "register_operand" "0")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed" "TARGET_80387 && reload_completed"
"fabs" "fabs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
...@@ -10763,7 +10164,7 @@ ...@@ -10763,7 +10164,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(abs:XF (float_extend:XF (abs:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))] (match_operand:DF 1 "register_operand" "0"))))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
"fabs" "fabs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
...@@ -10772,32 +10173,6 @@ ...@@ -10772,32 +10173,6 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(abs:XF (float_extend:XF (abs:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))] (match_operand:SF 1 "register_operand" "0"))))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
"fabs"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
(define_insn "*abstf2_1"
[(set (match_operand:TF 0 "register_operand" "=f")
(abs:TF (match_operand:TF 1 "register_operand" "0")))]
"TARGET_80387 && reload_completed"
"fabs"
[(set_attr "type" "fsgn")
(set_attr "mode" "DF")])
(define_insn "*absextenddftf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(abs:TF (float_extend:TF
(match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387"
"fabs"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
(define_insn "*absextendsftf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(abs:TF (float_extend:TF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_80387" "TARGET_80387"
"fabs" "fabs"
[(set_attr "type" "fsgn") [(set_attr "type" "fsgn")
...@@ -14841,7 +14216,7 @@ ...@@ -14841,7 +14216,7 @@
(match_operator:XF 3 "binary_fp_operator" (match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "%0") [(match_operand:XF 1 "register_operand" "%0")
(match_operand:XF 2 "register_operand" "f")]))] (match_operand:XF 2 "register_operand" "f")]))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 "TARGET_80387
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);" "* return output_387_binary_op (insn, operands);"
[(set (attr "type") [(set (attr "type")
...@@ -14850,19 +14225,6 @@ ...@@ -14850,19 +14225,6 @@
(const_string "fop"))) (const_string "fop")))
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
(define_insn "*fop_tf_comm"
[(set (match_operand:TF 0 "register_operand" "=f")
(match_operator:TF 3 "binary_fp_operator"
[(match_operand:TF 1 "register_operand" "%0")
(match_operand:TF 2 "register_operand" "f")]))]
"TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (match_operand:TF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop")))
(set_attr "mode" "XF")])
(define_insn "*fop_sf_1_nosse" (define_insn "*fop_sf_1_nosse"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(match_operator:SF 3 "binary_fp_operator" (match_operator:SF 3 "binary_fp_operator"
...@@ -15117,7 +14479,7 @@ ...@@ -15117,7 +14479,7 @@
(match_operator:XF 3 "binary_fp_operator" (match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,f") [(match_operand:XF 1 "register_operand" "0,f")
(match_operand:XF 2 "register_operand" "f,0")]))] (match_operand:XF 2 "register_operand" "f,0")]))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 "TARGET_80387
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'" && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);" "* return output_387_binary_op (insn, operands);"
[(set (attr "type") [(set (attr "type")
...@@ -15129,65 +14491,12 @@ ...@@ -15129,65 +14491,12 @@
(const_string "fop"))) (const_string "fop")))
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
(define_insn "*fop_tf_1"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(match_operator:TF 3 "binary_fp_operator"
[(match_operand:TF 1 "register_operand" "0,f")
(match_operand:TF 2 "register_operand" "f,0")]))]
"TARGET_80387
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:TF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:TF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "mode" "XF")])
(define_insn "*fop_xf_2" (define_insn "*fop_xf_2"
[(set (match_operand:XF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator" (match_operator:XF 3 "binary_fp_operator"
[(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")) [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:XF 2 "register_operand" "0,0")]))] (match_operand:XF 2 "register_operand" "0,0")]))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP" "TARGET_80387 && TARGET_USE_FIOP"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:XF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")
(set_attr "ppro_uops" "many")])
(define_insn "*fop_tf_2"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(match_operator:TF 3 "binary_fp_operator"
[(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:TF 2 "register_operand" "0,0")]))]
"TARGET_80387 && TARGET_USE_FIOP"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:TF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:TF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")
(set_attr "ppro_uops" "many")])
(define_insn "*fop_xf_3"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,0")
(float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type") [(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "") (cond [(match_operand:XF 3 "mult_operator" "")
...@@ -15200,17 +14509,17 @@ ...@@ -15200,17 +14509,17 @@
(set_attr "mode" "SI") (set_attr "mode" "SI")
(set_attr "ppro_uops" "many")]) (set_attr "ppro_uops" "many")])
(define_insn "*fop_tf_3" (define_insn "*fop_xf_3"
[(set (match_operand:TF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:TF 3 "binary_fp_operator" (match_operator:XF 3 "binary_fp_operator"
[(match_operand:TF 1 "register_operand" "0,0") [(match_operand:XF 1 "register_operand" "0,0")
(float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))] (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
"TARGET_80387 && TARGET_USE_FIOP" "TARGET_80387 && TARGET_USE_FIOP"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type") [(set (attr "type")
(cond [(match_operand:TF 3 "mult_operator" "") (cond [(match_operand:XF 3 "mult_operator" "")
(const_string "fmul") (const_string "fmul")
(match_operand:TF 3 "div_operator" "") (match_operand:XF 3 "div_operator" "")
(const_string "fdiv") (const_string "fdiv")
] ]
(const_string "fop"))) (const_string "fop")))
...@@ -15223,7 +14532,7 @@ ...@@ -15223,7 +14532,7 @@
(match_operator:XF 3 "binary_fp_operator" (match_operator:XF 3 "binary_fp_operator"
[(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0")) [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
(match_operand:XF 2 "register_operand" "0,f")]))] (match_operand:XF 2 "register_operand" "0,f")]))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
"* return output_387_binary_op (insn, operands);" "* return output_387_binary_op (insn, operands);"
[(set (attr "type") [(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "") (cond [(match_operand:XF 3 "mult_operator" "")
...@@ -15234,29 +14543,13 @@ ...@@ -15234,29 +14543,13 @@
(const_string "fop"))) (const_string "fop")))
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*fop_tf_4"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(match_operator:TF 3 "binary_fp_operator"
[(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
(match_operand:TF 2 "register_operand" "0,f")]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:TF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:TF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "mode" "SF")])
(define_insn "*fop_xf_5" (define_insn "*fop_xf_5"
[(set (match_operand:XF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator" (match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,f") [(match_operand:XF 1 "register_operand" "0,f")
(float_extend:XF (float_extend:XF
(match_operand 2 "nonimmediate_operand" "fm,0"))]))] (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
"* return output_387_binary_op (insn, operands);" "* return output_387_binary_op (insn, operands);"
[(set (attr "type") [(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "") (cond [(match_operand:XF 3 "mult_operator" "")
...@@ -15267,23 +14560,6 @@ ...@@ -15267,23 +14560,6 @@
(const_string "fop"))) (const_string "fop")))
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*fop_tf_5"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(match_operator:TF 3 "binary_fp_operator"
[(match_operand:TF 1 "register_operand" "0,f")
(float_extend:TF
(match_operand 2 "nonimmediate_operand" "fm,0"))]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:TF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:TF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "mode" "SF")])
(define_insn "*fop_xf_6" (define_insn "*fop_xf_6"
[(set (match_operand:XF 0 "register_operand" "=f,f") [(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator" (match_operator:XF 3 "binary_fp_operator"
...@@ -15291,7 +14567,7 @@ ...@@ -15291,7 +14567,7 @@
(match_operand 1 "register_operand" "0,f")) (match_operand 1 "register_operand" "0,f"))
(float_extend:XF (float_extend:XF
(match_operand 2 "nonimmediate_operand" "fm,0"))]))] (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387" "TARGET_80387"
"* return output_387_binary_op (insn, operands);" "* return output_387_binary_op (insn, operands);"
[(set (attr "type") [(set (attr "type")
(cond [(match_operand:XF 3 "mult_operator" "") (cond [(match_operand:XF 3 "mult_operator" "")
...@@ -15302,24 +14578,6 @@ ...@@ -15302,24 +14578,6 @@
(const_string "fop"))) (const_string "fop")))
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*fop_tf_6"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(match_operator:TF 3 "binary_fp_operator"
[(float_extend:TF
(match_operand 1 "register_operand" "0,f"))
(float_extend:TF
(match_operand 2 "nonimmediate_operand" "fm,0"))]))]
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:TF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:TF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "mode" "SF")])
(define_split (define_split
[(set (match_operand 0 "register_operand" "") [(set (match_operand 0 "register_operand" "")
(match_operator 3 "binary_fp_operator" (match_operator 3 "binary_fp_operator"
...@@ -15457,17 +14715,7 @@ ...@@ -15457,17 +14715,7 @@
(define_insn "sqrtxf2" (define_insn "sqrtxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (match_operand:XF 1 "register_operand" "0")))] (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
&& (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
(set_attr "athlon_decode" "direct")])
(define_insn "sqrttf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& (TARGET_IEEE_FP || flag_unsafe_math_optimizations) " && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15478,17 +14726,7 @@ ...@@ -15478,17 +14726,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF (sqrt:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))] (match_operand:DF 1 "register_operand" "0"))))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
(set_attr "athlon_decode" "direct")])
(define_insn "*sqrtextenddftf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(sqrt:TF (float_extend:TF
(match_operand:DF 1 "register_operand" "0"))))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF") (set_attr "mode" "XF")
...@@ -15498,17 +14736,7 @@ ...@@ -15498,17 +14736,7 @@
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF (sqrt:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))] (match_operand:SF 1 "register_operand" "0"))))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
(set_attr "athlon_decode" "direct")])
(define_insn "*sqrtextendsftf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(sqrt:TF (float_extend:TF
(match_operand:SF 1 "register_operand" "0"))))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
"fsqrt" "fsqrt"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF") (set_attr "mode" "XF")
...@@ -15546,16 +14774,7 @@ ...@@ -15546,16 +14774,7 @@
(define_insn "sinxf2" (define_insn "sinxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))] (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_insn "sintf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fsin" "fsin"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
...@@ -15593,15 +14812,6 @@ ...@@ -15593,15 +14812,6 @@
(define_insn "cosxf2" (define_insn "cosxf2"
[(set (match_operand:XF 0 "register_operand" "=f") [(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))] (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
"!TARGET_128BIT_LONG_DOUBLE && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_insn "costf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations" && flag_unsafe_math_optimizations"
"fcos" "fcos"
...@@ -15665,7 +14875,7 @@ ...@@ -15665,7 +14875,7 @@
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=1"))] (clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
"fpatan" "fpatan"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
...@@ -15675,7 +14885,7 @@ ...@@ -15675,7 +14885,7 @@
(use (match_operand:XF 2 "register_operand" "0")) (use (match_operand:XF 2 "register_operand" "0"))
(use (match_operand:XF 1 "register_operand" "u"))] (use (match_operand:XF 1 "register_operand" "u"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
{ {
rtx copy = gen_reg_rtx (XFmode); rtx copy = gen_reg_rtx (XFmode);
emit_move_insn (copy, operands[1]); emit_move_insn (copy, operands[1]);
...@@ -15683,40 +14893,14 @@ ...@@ -15683,40 +14893,14 @@
DONE; DONE;
}) })
(define_insn "atan2tf3_1"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 2 "register_operand" "0")
(match_operand:TF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:TF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_expand "atan2tf3"
[(use (match_operand:TF 0 "register_operand" "=f"))
(use (match_operand:TF 2 "register_operand" "0"))
(use (match_operand:TF 1 "register_operand" "u"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
{
rtx copy = gen_reg_rtx (TFmode);
emit_move_insn (copy, operands[1]);
emit_insn (gen_atan2tf3_1 (operands[0], copy, operands[2]));
DONE;
})
(define_insn "*fyl2x_sfxf3" (define_insn "*fyl2x_sfxf3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0") (unspec:SF [(match_operand:SF 2 "register_operand" "0")
(match_operand 1 "register_operand" "u")] (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X)) UNSPEC_FYL2X))
(clobber (match_scratch:SF 3 "=1"))] (clobber (match_scratch:SF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && flag_unsafe_math_optimizations"
&& GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
"fyl2x" "fyl2x"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
...@@ -15724,12 +14908,11 @@ ...@@ -15724,12 +14908,11 @@
(define_insn "*fyl2x_dfxf3" (define_insn "*fyl2x_dfxf3"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0") (unspec:DF [(match_operand:DF 2 "register_operand" "0")
(match_operand 1 "register_operand" "u")] (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X)) UNSPEC_FYL2X))
(clobber (match_scratch:DF 3 "=1"))] (clobber (match_scratch:DF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && flag_unsafe_math_optimizations"
&& GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
"fyl2x" "fyl2x"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
...@@ -15741,19 +14924,7 @@ ...@@ -15741,19 +14924,7 @@
UNSPEC_FYL2X)) UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 "=1"))] (clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_insn "*fyl2x_tfxf3"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 2 "register_operand" "0")
(match_operand:TF 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_scratch:TF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"fyl2x" "fyl2x"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
...@@ -15768,7 +14939,7 @@ ...@@ -15768,7 +14939,7 @@
{ {
rtx temp; rtx temp;
operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode); operands[2] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (4); /* fldln2 */ temp = standard_80387_constant_rtx (4); /* fldln2 */
emit_move_insn (operands[2], temp); emit_move_insn (operands[2], temp);
}) })
...@@ -15783,7 +14954,7 @@ ...@@ -15783,7 +14954,7 @@
{ {
rtx temp; rtx temp;
operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode); operands[2] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (4); /* fldln2 */ temp = standard_80387_constant_rtx (4); /* fldln2 */
emit_move_insn (operands[2], temp); emit_move_insn (operands[2], temp);
}) })
...@@ -15794,7 +14965,7 @@ ...@@ -15794,7 +14965,7 @@
(match_dup 2)] UNSPEC_FYL2X)) (match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])] (clobber (match_scratch:XF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
...@@ -15803,45 +14974,26 @@ ...@@ -15803,45 +14974,26 @@
emit_move_insn (operands[2], temp); emit_move_insn (operands[2], temp);
}) })
(define_expand "logtf2"
[(parallel [(set (match_operand:TF 0 "register_operand" "")
(unspec:TF [(match_operand:TF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:TF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
{
rtx temp;
operands[2] = gen_reg_rtx (TFmode);
temp = standard_80387_constant_rtx (4); /* fldln2 */
emit_move_insn (operands[2], temp);
})
(define_insn "*fscale_sfxf3" (define_insn "*fscale_sfxf3"
[(set (match_operand:SF 0 "register_operand" "=f") [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand 2 "register_operand" "0") (unspec:SF [(match_operand:XF 2 "register_operand" "0")
(match_operand 1 "register_operand" "u")] (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FSCALE)) UNSPEC_FSCALE))
(clobber (match_scratch:SF 3 "=1"))] (clobber (match_scratch:SF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && flag_unsafe_math_optimizations"
&& GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)
&& GET_MODE (operands[2]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
"fscale\;fstp\t%y1" "fscale\;fstp\t%y1"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "*fscale_dfxf3" (define_insn "*fscale_dfxf3"
[(set (match_operand:DF 0 "register_operand" "=f") [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand 2 "register_operand" "0") (unspec:DF [(match_operand:XF 2 "register_operand" "0")
(match_operand 1 "register_operand" "u")] (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FSCALE)) UNSPEC_FSCALE))
(clobber (match_scratch:DF 3 "=1"))] (clobber (match_scratch:DF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && flag_unsafe_math_optimizations"
&& GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)
&& GET_MODE (operands[2]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
"fscale\;fstp\t%y1" "fscale\;fstp\t%y1"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
...@@ -15853,19 +15005,7 @@ ...@@ -15853,19 +15005,7 @@
UNSPEC_FSCALE)) UNSPEC_FSCALE))
(clobber (match_scratch:XF 3 "=1"))] (clobber (match_scratch:XF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
"fscale\;fstp\t%y1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_insn "*fscale_tf3"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 2 "register_operand" "0")
(match_operand:TF 1 "register_operand" "u")]
UNSPEC_FSCALE))
(clobber (match_scratch:TF 3 "=1"))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"fscale\;fstp\t%y1" "fscale\;fstp\t%y1"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
...@@ -15875,17 +15015,7 @@ ...@@ -15875,17 +15015,7 @@
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT))] UNSPEC_FRNDINT))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
"frndint"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_insn "*frndinttf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "register_operand" "0")]
UNSPEC_FRNDINT))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"frndint" "frndint"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
...@@ -15895,17 +15025,7 @@ ...@@ -15895,17 +15025,7 @@
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_F2XM1))] UNSPEC_F2XM1))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
"f2xm1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(define_insn "*f2xm1tf2"
[(set (match_operand:TF 0 "register_operand" "=f")
(unspec:TF [(match_operand:TF 1 "register_operand" "0")]
UNSPEC_F2XM1))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"f2xm1" "f2xm1"
[(set_attr "type" "fpspc") [(set_attr "type" "fpspc")
(set_attr "mode" "XF")]) (set_attr "mode" "XF")])
...@@ -15927,12 +15047,6 @@ ...@@ -15927,12 +15047,6 @@
rtx temp; rtx temp;
int i; int i;
if (TARGET_128BIT_LONG_DOUBLE)
{
emit_insn (gen_expsf2_tf (operands[0], operands[1]));
DONE;
}
for (i=2; i<10; i++) for (i=2; i<10; i++)
operands[i] = gen_reg_rtx (XFmode); operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */ temp = standard_80387_constant_rtx (5); /* fldl2e */
...@@ -15940,29 +15054,6 @@ ...@@ -15940,29 +15054,6 @@
emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */ emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
}) })
(define_expand "expsf2_tf"
[(set (match_dup 2)
(float_extend:TF (match_operand:SF 1 "register_operand" "")))
(set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
(set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
(set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
(set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
(set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
(parallel [(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
(clobber (match_scratch:SF 5 ""))])]
""
{
rtx temp;
int i;
for (i=2; i<10; i++)
operands[i] = gen_reg_rtx (TFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
emit_move_insn (operands[3], temp);
emit_move_insn (operands[8], CONST1_RTX (TFmode)); /* fld1 */
})
(define_expand "expdf2" (define_expand "expdf2"
[(set (match_dup 2) [(set (match_dup 2)
(float_extend:XF (match_operand:DF 1 "register_operand" ""))) (float_extend:XF (match_operand:DF 1 "register_operand" "")))
...@@ -15980,12 +15071,6 @@ ...@@ -15980,12 +15071,6 @@
rtx temp; rtx temp;
int i; int i;
if (TARGET_128BIT_LONG_DOUBLE)
{
emit_insn (gen_expdf2_tf (operands[0], operands[1]));
DONE;
}
for (i=2; i<10; i++) for (i=2; i<10; i++)
operands[i] = gen_reg_rtx (XFmode); operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */ temp = standard_80387_constant_rtx (5); /* fldl2e */
...@@ -15993,30 +15078,6 @@ ...@@ -15993,30 +15078,6 @@
emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */ emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
}) })
(define_expand "expdf2_tf"
[(set (match_dup 2)
(float_extend:TF (match_operand:DF 1 "register_operand" "")))
(set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
(set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
(set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
(set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
(set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
(parallel [(set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
(clobber (match_scratch:DF 5 ""))])]
""
{
rtx temp;
int i;
for (i=2; i<10; i++)
operands[i] = gen_reg_rtx (TFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
emit_move_insn (operands[3], temp);
emit_move_insn (operands[8], CONST1_RTX (TFmode)); /* fld1 */
})
(define_expand "expxf2" (define_expand "expxf2"
[(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "") [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
(match_dup 2))) (match_dup 2)))
...@@ -16028,7 +15089,7 @@ ...@@ -16028,7 +15089,7 @@
(unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE)) (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
(clobber (match_scratch:XF 5 ""))])] (clobber (match_scratch:XF 5 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
{ {
rtx temp; rtx temp;
int i; int i;
...@@ -16053,29 +15114,6 @@ ...@@ -16053,29 +15114,6 @@
emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */ emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
}) })
(define_expand "exptf2"
[(set (match_dup 3) (mult:TF (match_operand:TF 1 "register_operand" "")
(match_dup 2)))
(set (match_dup 4) (unspec:TF [(match_dup 3)] UNSPEC_FRNDINT))
(set (match_dup 5) (minus:TF (match_dup 3) (match_dup 4)))
(set (match_dup 6) (unspec:TF [(match_dup 5)] UNSPEC_F2XM1))
(set (match_dup 8) (plus:TF (match_dup 6) (match_dup 7)))
(parallel [(set (match_operand:TF 0 "register_operand" "")
(unspec:TF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
(clobber (match_scratch:TF 5 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
{
rtx temp;
int i;
for (i=2; i<9; i++)
operands[i] = gen_reg_rtx (TFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
emit_move_insn (operands[2], temp);
emit_move_insn (operands[7], CONST1_RTX (TFmode)); /* fld1 */
})
(define_expand "atandf2" (define_expand "atandf2"
[(parallel [(set (match_operand:DF 0 "register_operand" "") [(parallel [(set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 2) (unspec:DF [(match_dup 2)
...@@ -16096,25 +15134,12 @@ ...@@ -16096,25 +15134,12 @@
UNSPEC_FPATAN)) UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 ""))])] (clobber (match_scratch:XF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE" && flag_unsafe_math_optimizations"
{ {
operands[2] = gen_reg_rtx (XFmode); operands[2] = gen_reg_rtx (XFmode);
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
}) })
(define_expand "atantf2"
[(parallel [(set (match_operand:TF 0 "register_operand" "")
(unspec:TF [(match_dup 2)
(match_operand:TF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:TF 3 ""))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
{
operands[2] = gen_reg_rtx (TFmode);
emit_move_insn (operands[2], CONST1_RTX (TFmode)); /* fld1 */
})
;; Block operation instructions ;; Block operation instructions
(define_insn "cld" (define_insn "cld"
...@@ -17364,14 +16389,6 @@ ...@@ -17364,14 +16389,6 @@
(if_then_else:XF (match_operand 1 "comparison_operator" "") (if_then_else:XF (match_operand 1 "comparison_operator" "")
(match_operand:XF 2 "register_operand" "") (match_operand:XF 2 "register_operand" "")
(match_operand:XF 3 "register_operand" "")))] (match_operand:XF 3 "register_operand" "")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
"if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
(define_expand "movtfcc"
[(set (match_operand:TF 0 "register_operand" "")
(if_then_else:TF (match_operand 1 "comparison_operator" "")
(match_operand:TF 2 "register_operand" "")
(match_operand:TF 3 "register_operand" "")))]
"TARGET_CMOVE" "TARGET_CMOVE"
"if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;") "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
...@@ -17381,19 +16398,6 @@ ...@@ -17381,19 +16398,6 @@
[(reg 17) (const_int 0)]) [(reg 17) (const_int 0)])
(match_operand:XF 2 "register_operand" "f,0") (match_operand:XF 2 "register_operand" "f,0")
(match_operand:XF 3 "register_operand" "0,f")))] (match_operand:XF 3 "register_operand" "0,f")))]
"!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
"@
fcmov%F1\t{%2, %0|%0, %2}
fcmov%f1\t{%3, %0|%0, %3}"
[(set_attr "type" "fcmov")
(set_attr "mode" "XF")])
(define_insn "*movtfcc_1"
[(set (match_operand:TF 0 "register_operand" "=f,f")
(if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
[(reg 17) (const_int 0)])
(match_operand:TF 2 "register_operand" "f,0")
(match_operand:TF 3 "register_operand" "0,f")))]
"TARGET_CMOVE" "TARGET_CMOVE"
"@ "@
fcmov%F1\t{%2, %0|%0, %2} fcmov%F1\t{%2, %0|%0, %2}
...@@ -19534,6 +18538,18 @@ ...@@ -19534,6 +18538,18 @@
DONE; DONE;
}) })
(define_expand "movtf"
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "nonimmediate_operand" ""))]
"TARGET_64BIT"
{
if (TARGET_64BIT)
ix86_expand_move (TFmode, operands);
else
ix86_expand_vector_move (TFmode, operands);
DONE;
})
(define_insn "movv2df_internal" (define_insn "movv2df_internal"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m") [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
(match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))] (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
...@@ -19919,6 +18935,50 @@ ...@@ -19919,6 +18935,50 @@
(const_string "TI"))] (const_string "TI"))]
(const_string "DI")))]) (const_string "DI")))])
(define_insn "*movtf_rex64"
[(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
(match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
"TARGET_64BIT
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
{
case 0:
case 1:
return "#";
case 2:
if (get_attr_mode (insn) == MODE_V4SF)
return "xorps\t%0, %0";
else
return "pxor\t%0, %0";
case 3:
case 4:
if (get_attr_mode (insn) == MODE_V4SF)
return "movaps\t{%1, %0|%0, %1}";
else
return "movdqa\t{%1, %0|%0, %1}";
default:
abort ();
}
}
[(set_attr "type" "*,*,ssemov,ssemov,ssemov")
(set (attr "mode")
(cond [(eq_attr "alternative" "2,3")
(if_then_else
(ne (symbol_ref "optimize_size")
(const_int 0))
(const_string "V4SF")
(const_string "TI"))
(eq_attr "alternative" "4")
(if_then_else
(ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
(const_int 0))
(ne (symbol_ref "optimize_size")
(const_int 0)))
(const_string "V4SF")
(const_string "TI"))]
(const_string "DI")))])
(define_split (define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "") [(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))] (match_operand:TI 1 "general_operand" ""))]
...@@ -19927,6 +18987,14 @@ ...@@ -19927,6 +18987,14 @@
[(const_int 0)] [(const_int 0)]
"ix86_split_long_move (operands); DONE;") "ix86_split_long_move (operands); DONE;")
(define_split
[(set (match_operand:TF 0 "nonimmediate_operand" "")
(match_operand:TF 1 "general_operand" ""))]
"reload_completed && !SSE_REG_P (operands[0])
&& !SSE_REG_P (operands[1])"
[(const_int 0)]
"ix86_split_long_move (operands); DONE;")
;; These two patterns are useful for specifying exactly whether to use ;; These two patterns are useful for specifying exactly whether to use
;; movaps or movups ;; movaps or movups
(define_expand "sse_movaps" (define_expand "sse_movaps"
......
gcc/real.c
...@@ -3032,6 +3032,11 @@ encode_ieee_extended (const struct real_format *fmt, long *buf, ...@@ -3032,6 +3032,11 @@ encode_ieee_extended (const struct real_format *fmt, long *buf,
buf[0] = image_hi << 16, buf[1] = sig_hi, buf[2] = sig_lo; buf[0] = image_hi << 16, buf[1] = sig_hi, buf[2] = sig_lo;
else else
buf[0] = sig_lo, buf[1] = sig_hi, buf[2] = image_hi; buf[0] = sig_lo, buf[1] = sig_hi, buf[2] = image_hi;
/* Avoid uninitialized data to be output by compiler when XFmode is extended
to 128 bits. */
if (GET_MODE_SIZE (XFmode) == 16)
buf[3] = 0;
} }
static void static void
......
gcc/reg-stack.c
...@@ -1124,7 +1124,7 @@ move_for_stack_reg (rtx insn, stack regstack, rtx pat) ...@@ -1124,7 +1124,7 @@ move_for_stack_reg (rtx insn, stack regstack, rtx pat)
regstack->top--; regstack->top--;
CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src)); CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src));
} }
else if ((GET_MODE (src) == XFmode || GET_MODE (src) == TFmode) else if ((GET_MODE (src) == XFmode)
&& regstack->top < REG_STACK_SIZE - 1) && regstack->top < REG_STACK_SIZE - 1)
{ {
/* A 387 cannot write an XFmode value to a MEM without /* A 387 cannot write an XFmode value to a MEM without
...@@ -1137,9 +1137,6 @@ move_for_stack_reg (rtx insn, stack regstack, rtx pat) ...@@ -1137,9 +1137,6 @@ move_for_stack_reg (rtx insn, stack regstack, rtx pat)
rtx push_rtx, push_insn; rtx push_rtx, push_insn;
rtx top_stack_reg = FP_MODE_REG (FIRST_STACK_REG, GET_MODE (src)); rtx top_stack_reg = FP_MODE_REG (FIRST_STACK_REG, GET_MODE (src));
if (GET_MODE (src) == TFmode)
push_rtx = gen_movtf (top_stack_reg, top_stack_reg);
else
push_rtx = gen_movxf (top_stack_reg, top_stack_reg); push_rtx = gen_movxf (top_stack_reg, top_stack_reg);
push_insn = emit_insn_before (push_rtx, insn); push_insn = emit_insn_before (push_rtx, insn);
REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, top_stack_reg, REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, top_stack_reg,
......
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