pa.h (VAL_U6_BITS_P): Define.

	* config/pa/pa.h (VAL_U6_BITS_P): Define.
	(INT_U6_BITS): Likewise.
	* config/pa/predicates.md (uint6_operand): New predicate.
	(shift5_operand, shift6_operand): Likewise.
	* config/pa/pa.md (lshrsi3, rotrsi3): Use shift5_operand instead of
	arith32_operand.
	(lshrdi3): Use shift6_operand.
	(shrpsi4, shrpdi4): New insn patterns.
	(extzv): Delete expander.
	(extzvsi, extzvdi): New expanders.  Use uint5_operand and uint6_operand
	predicates in unamed zero extract patterns.  Tighten common constraint.
	(extv): Delete expander.
	(extvsi, extvdi): New expanders.  Use uint5_operand and uint6_operand
	predicates in unamed sign extract patterns.  Tighten common constraint.
	(insv): Delete expander.
	(insvsi, insvdi): New expanders.  Use uint5_operand and uint6_operand
	predicates in unamed insert patterns.  Tighten common constraint.
	Change uint32_operand predicate to uint6_operand predicate in unamed
	DImode pattern to insert constant values of type 1...1xxxx.

From-SVN: r195045

gcc/ChangeLog

+2013-01-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config/pa/pa.h (VAL_U6_BITS_P): Define.
+	(INT_U6_BITS): Likewise.
+	* config/pa/predicates.md (uint6_operand): New predicate.
+	(shift5_operand, shift6_operand): Likewise.
+	* config/pa/pa.md (lshrsi3, rotrsi3): Use shift5_operand instead of
+	arith32_operand.
+	(lshrdi3): Use shift6_operand.
+	(shrpsi4, shrpdi4): New insn patterns.
+	(extzv): Delete expander.
+	(extzvsi, extzvdi): New expanders.  Use uint5_operand and uint6_operand
+	predicates in unamed zero extract patterns.  Tighten common constraint.
+	(extv): Delete expander.
+	(extvsi, extvdi): New expanders.  Use uint5_operand and uint6_operand
+	predicates in unamed sign extract patterns.  Tighten common constraint.
+	(insv): Delete expander.
+	(insvsi, insvdi): New expanders.  Use uint5_operand and uint6_operand
+	predicates in unamed insert patterns.  Tighten common constraint.
+	Change uint32_operand predicate to uint6_operand predicate in unamed
+	DImode pattern to insert constant values of type 1...1xxxx.
+
 2013-01-04  Jan Hubicka  <jh@suse.cz>
 
 	PR tree-optimization/55823

gcc/config/pa/pa.h

@@ -956,6 +956,9 @@ extern int may_call_alloca;
 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
 
+#define VAL_U6_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x40)
+#define INT_U6_BITS(X) VAL_U6_BITS_P (INTVAL (X))
+
 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
 

gcc/config/pa/predicates.md

@@ -32,6 +32,13 @@
        (match_test "INT_U5_BITS (op)")))
 
 ;; Return truth value of whether OP is an integer which fits the range
+;; constraining 6-bit unsigned immediate operands in three-address insns.
+
+(define_predicate "uint6_operand"
+  (and (match_code "const_int")
+       (match_test "INT_U6_BITS (op)")))
+
+;; Return truth value of whether OP is an integer which fits the range
 ;; constraining 11-bit signed immediate operands in three-address insns.
 
 (define_predicate "int11_operand"
@@ -125,6 +132,20 @@
   (ior (match_operand 0 "register_operand")
        (match_code "const_int")))
 
+;; Return truth value of whether OP can be used as a shift operand in
+;; a shift insn that accepts registers of mode MODE or 5-bit shift amounts.
+
+(define_predicate "shift5_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "uint5_operand")))
+
+;; Return truth value of whether OP can be used as a shift operand in
+;; a shift insn that accepts registers of mode MODE or 6-bit shift amounts.
+
+(define_predicate "shift6_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "uint6_operand")))
+
 ;; True iff OP can be used as an operand in an adddi3 insn.
 
 (define_predicate "adddi3_operand"