Commit f6e0013a by Wilco Dijkstra Committed by Wilco Dijkstra

Remove aarch64_cannot_change_mode_class as the underlying issue (PR67609) has been resolved.

Remove aarch64_cannot_change_mode_class as the underlying issue
(PR67609) has been resolved.  This avoids a few unnecessary lane
widening operations like:

faddp   d18, v18.2d
mov     d18, v18.d[0]

    gcc/
	PR67609
	* config/aarch64/aarch64.h (CANNOT_CHANGE_MODE_CLASS): Remove.
	* config/aarch64/aarch64.c
	(aarch64_cannot_change_mode_class): Remove function.
	* config/aarch64/aarch64-protos.h
	(aarch64_cannot_change_mode_class): Remove.

From-SVN: r236817
parent 105e29c5
2016-05-27 Wilco Dijkstra <wdijkstr@arm.com>
PR67609
* config/aarch64/aarch64.h (CANNOT_CHANGE_MODE_CLASS): Remove.
* config/aarch64/aarch64.c
(aarch64_cannot_change_mode_class): Remove function.
* config/aarch64/aarch64-protos.h
(aarch64_cannot_change_mode_class): Remove.
2016-05-27 Jan Hubicka <hubicka@ucw.cz> 2016-05-27 Jan Hubicka <hubicka@ucw.cz>
* cfgloop.c (record_niter_bound): Record likely upper bounds. * cfgloop.c (record_niter_bound): Record likely upper bounds.
......
...@@ -282,9 +282,6 @@ int aarch64_get_condition_code (rtx); ...@@ -282,9 +282,6 @@ int aarch64_get_condition_code (rtx);
bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode); bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
int aarch64_branch_cost (bool, bool); int aarch64_branch_cost (bool, bool);
enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx); enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
bool aarch64_cannot_change_mode_class (machine_mode,
machine_mode,
enum reg_class);
bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT); bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
bool aarch64_constant_address_p (rtx); bool aarch64_constant_address_p (rtx);
bool aarch64_expand_movmem (rtx *); bool aarch64_expand_movmem (rtx *);
......
...@@ -12615,24 +12615,6 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, ...@@ -12615,24 +12615,6 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
return ret; return ret;
} }
/* Implement target hook CANNOT_CHANGE_MODE_CLASS. */
bool
aarch64_cannot_change_mode_class (machine_mode from,
machine_mode to,
enum reg_class rclass)
{
/* We cannot allow word_mode subregs of full vector modes.
Otherwise the middle-end will assume it's ok to store to
(subreg:DI (reg:TI 100) 0) in order to modify only the low 64 bits
of the 128-bit register. However, after reload the subreg will
be dropped leaving a plain DImode store. See PR67609 for a more
detailed dicussion. In all other cases, we want to be permissive
and return false. */
return (reg_classes_intersect_p (FP_REGS, rclass)
&& GET_MODE_SIZE (to) == UNITS_PER_WORD
&& GET_MODE_SIZE (from) > UNITS_PER_WORD);
}
rtx rtx
aarch64_reverse_mask (enum machine_mode mode) aarch64_reverse_mask (enum machine_mode mode)
{ {
......
...@@ -832,9 +832,6 @@ typedef struct ...@@ -832,9 +832,6 @@ typedef struct
extern void __aarch64_sync_cache_range (void *, void *); \ extern void __aarch64_sync_cache_range (void *, void *); \
__aarch64_sync_cache_range (beg, end) __aarch64_sync_cache_range (beg, end)
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
aarch64_cannot_change_mode_class (FROM, TO, CLASS)
#define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD) #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
/* Choose appropriate mode for caller saves, so we do the minimum /* Choose appropriate mode for caller saves, so we do the minimum
......
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