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riscv-gcc-1
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lvzhengyang
riscv-gcc-1
Commits
f6176c64
Commit
f6176c64
authored
Nov 04, 1995
by
Richard Kenner
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(casesi_worker): Change constraint from = to +.
From-SVN: r10548
parent
f6ab52f8
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gcc/config/sh/sh.md
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f6176c64
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@@ -1572,7 +1572,7 @@
[
(set (reg:SI 0)
(plus:SI (reg:SI 0)
(mem:HI (plus:SI (reg:SI 0)
(match_operand:SI 0 "arith_reg_operand" "
=
r")))))
(match_operand:SI 0 "arith_reg_operand" "
+
r")))))
(set (match_dup 0) (mem:HI (plus:SI (reg:SI 0)
(match_dup 0))))]
""
...
...
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