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riscv-gcc-1
Commit f56e86bd by Jan Hubicka Committed by Jan Hubicka
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re PR target/8343 ([m68k] [3.2 regression] m68k-elf/rtems ICE at instantiate_virtual_regs_1) 

	* i386.md (*mul*): FIx constraints; remove confused comment; fix
	athlon_decode attributes
	(imul/k8 optimization peep2s): New.

	* athlon.md (athlon_ssecmp*): Handle ssecomi as well.
	* i386.md (type attribute): Add ssecomi.
	(unit, memory, prefix attributes): Handle ssecomi.
	(cvt?2? patterns): Fix athlon_decode attribute
	(comi patterns): Set attribute to ssecomi.

	PR target/8343
	* m68k.md (umulsidi, mulsidi expanders): Use register operand.

From-SVN: r61098
parent 98c29f71
Showing with 323 additions and 120 deletions
gcc/ChangeLog
Thu Jan 9 12:00:36 CET 2003 Jan Hubicka <jh@suse.cz>
* i386.md (*mul*): FIx constraints; remove confused comment; fix
athlon_decode attributes
(imul/k8 optimization peep2s): New.
* athlon.md (athlon_ssecmp*): Handle ssecomi as well.
* i386.md (type attribute): Add ssecomi.
(unit, memory, prefix attributes): Handle ssecomi.
(cvt?2? patterns): Fix athlon_decode attribute
(comi patterns): Set attribute to ssecomi.
PR target/8343
* m68k.md (umulsidi, mulsidi expanders): Use register operand.
2003-01-09 Richard Sandiford <rsandifo@redhat.com> 2003-01-09 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (PREDICATE_CODES): Add ADDRESSOF for predicates * config/mips/mips.h (PREDICATE_CODES): Add ADDRESSOF for predicates
......
gcc/config/i386/athlon.md
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
;; The load/store queue unit is not attached to the schedulers but ;; The load/store queue unit is not attached to the schedulers but
;; communicates with all the execution units separately instead. ;; communicates with all the execution units separately instead.
(define_attr "athlon_decode" "direct,vector" (define_attr "athlon_decode" "direct,vector,double"
(cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,leave") (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,leave")
(const_string "vector") (const_string "vector")
(and (eq_attr "type" "push") (and (eq_attr "type" "push")
...@@ -496,32 +496,32 @@ ...@@ -496,32 +496,32 @@
"athlon-double,athlon-fmul") "athlon-double,athlon-fmul")
(define_insn_reservation "athlon_ssecmp_load" 5 (define_insn_reservation "athlon_ssecmp_load" 5
(and (eq_attr "cpu" "athlon,k8") (and (eq_attr "cpu" "athlon,k8")
(and (eq_attr "type" "ssecmp") (and (eq_attr "type" "ssecmp,ssecomi")
(and (eq_attr "mode" "SF,DF") (and (eq_attr "mode" "SF,DF")
(eq_attr "memory" "load")))) (eq_attr "memory" "load"))))
"athlon-vector,athlon-load,athlon-fadd") "athlon-vector,athlon-load,athlon-fadd")
(define_insn_reservation "athlon_ssecmp" 2 (define_insn_reservation "athlon_ssecmp" 2
(and (eq_attr "cpu" "athlon,k8") (and (eq_attr "cpu" "athlon,k8")
(and (eq_attr "type" "ssecmp") (and (eq_attr "type" "ssecmp,ssecomi")
(eq_attr "mode" "SF,DF"))) (eq_attr "mode" "SF,DF")))
"athlon-direct,athlon-fadd") "athlon-direct,athlon-fadd")
(define_insn_reservation "athlon_ssecmpvector_load" 6 (define_insn_reservation "athlon_ssecmpvector_load" 6
(and (eq_attr "cpu" "athlon") (and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "ssecmp") (and (eq_attr "type" "ssecmp,ssecomi")
(eq_attr "memory" "load"))) (eq_attr "memory" "load")))
"athlon-vector,athlon-fadd") "athlon-vector,athlon-fadd")
(define_insn_reservation "athlon_ssecmpvector_load_k8" 5 (define_insn_reservation "athlon_ssecmpvector_load_k8" 5
(and (eq_attr "cpu" "k8") (and (eq_attr "cpu" "k8")
(and (eq_attr "type" "ssecmp") (and (eq_attr "type" "ssecmp,ssecomi")
(eq_attr "memory" "load"))) (eq_attr "memory" "load")))
"athlon-double,athlon-fadd") "athlon-double,athlon-fadd")
(define_insn_reservation "athlon_ssecmpvector" 3 (define_insn_reservation "athlon_ssecmpvector" 3
(and (eq_attr "cpu" "athlon") (and (eq_attr "cpu" "athlon")
(eq_attr "type" "ssecmp")) (eq_attr "type" "ssecmp,ssecomi"))
"athlon-vector,athlon-fadd") "athlon-vector,athlon-fadd")
(define_insn_reservation "athlon_ssecmpvector_k8" 3 (define_insn_reservation "athlon_ssecmpvector_k8" 3
(and (eq_attr "cpu" "k8") (and (eq_attr "cpu" "k8")
(eq_attr "type" "ssecmp")) (eq_attr "type" "ssecmp,ssecomi"))
"athlon-double,athlon-fadd") "athlon-double,athlon-fadd")
(define_insn_reservation "athlon_sseadd_load" 7 (define_insn_reservation "athlon_sseadd_load" 7
(and (eq_attr "cpu" "athlon") (and (eq_attr "cpu" "athlon")
......
gcc/config/i386/i386.md
...@@ -147,7 +147,7 @@ ...@@ -147,7 +147,7 @@
str,cld, str,cld,
fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp, fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
sselog,sseiadd,sseishft,sseimul, sselog,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv, sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft" mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
(const_string "other")) (const_string "other"))
...@@ -161,7 +161,7 @@ ...@@ -161,7 +161,7 @@
(cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp") (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
(const_string "i387") (const_string "i387")
(eq_attr "type" "sselog,sseiadd,sseishft,sseimul, (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv") sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssediv")
(const_string "sse") (const_string "sse")
(eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
(const_string "mmx") (const_string "mmx")
...@@ -228,7 +228,7 @@ ...@@ -228,7 +228,7 @@
(eq_attr "type" (eq_attr "type"
"imovx,setcc,icmov, "imovx,setcc,icmov,
sselog,sseiadd,sseishft,sseimul, sselog,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecvt,ssediv, sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssediv,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft") mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
(const_int 1) (const_int 1)
(const_int 0))) (const_int 0)))
...@@ -319,7 +319,7 @@ ...@@ -319,7 +319,7 @@
(if_then_else (match_operand 0 "memory_operand" "") (if_then_else (match_operand 0 "memory_operand" "")
(const_string "store") (const_string "store")
(const_string "none")) (const_string "none"))
(eq_attr "type" "icmp,test,ssecmp,mmxcmp,fcmp") (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
(if_then_else (ior (match_operand 0 "memory_operand" "") (if_then_else (ior (match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")) (match_operand 1 "memory_operand" ""))
(const_string "load") (const_string "load")
...@@ -350,7 +350,7 @@ ...@@ -350,7 +350,7 @@
"!alu1,negnot, "!alu1,negnot,
imov,imovx,icmp,test, imov,imovx,icmp,test,
fmov,fcmp,fsgn, fmov,fcmp,fsgn,
sse,ssemov,ssecmp,ssecvt, sse,ssemov,ssecmp,ssecomi,ssecvt,
mmx,mmxmov,mmxcmp,mmxcvt") mmx,mmxmov,mmxcmp,mmxcvt")
(match_operand 2 "memory_operand" "")) (match_operand 2 "memory_operand" ""))
(const_string "load") (const_string "load")
...@@ -3845,17 +3845,18 @@ ...@@ -3845,17 +3845,18 @@
(set_attr "mode" "SF,SF,SF,SF,DF")]) (set_attr "mode" "SF,SF,SF,SF,DF")])
(define_insn "*truncdfsf2_2" (define_insn "*truncdfsf2_2"
[(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m") [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
(float_truncate:SF (float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY,f#Y")))] (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
"TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{ {
switch (which_alternative) switch (which_alternative)
{ {
case 0: case 0:
return "cvtsd2ss\t{%1, %0|%0, %1}";
case 1: case 1:
return "cvtsd2ss\t{%1, %0|%0, %1}";
case 2:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0"; return "fstp%z0\t%y0";
else else
...@@ -3864,8 +3865,9 @@ ...@@ -3864,8 +3865,9 @@
abort (); abort ();
} }
} }
[(set_attr "type" "ssecvt,fmov") [(set_attr "type" "ssecvt,ssecvt,fmov")
(set_attr "mode" "DF,SF")]) (set_attr "athlon_decode" "vector,double,*")
(set_attr "mode" "DF,DF,SF")])
(define_insn "*truncdfsf2_2_nooverlap" (define_insn "*truncdfsf2_2_nooverlap"
[(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m") [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
...@@ -3905,12 +3907,13 @@ ...@@ -3905,12 +3907,13 @@
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "truncdfsf2_sse_only" (define_insn "truncdfsf2_sse_only"
[(set (match_operand:SF 0 "register_operand" "=Y") [(set (match_operand:SF 0 "register_operand" "=Y,Y")
(float_truncate:SF (float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY")))] (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
"!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS" "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
"cvtsd2ss\t{%1, %0|%0, %1}" "cvtsd2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "athlon_decode" "vector,double")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")])
(define_insn "*truncdfsf2_sse_only_nooverlap" (define_insn "*truncdfsf2_sse_only_nooverlap"
...@@ -4372,18 +4375,20 @@ ...@@ -4372,18 +4375,20 @@
;; When SSE available, it is always faster to use it! ;; When SSE available, it is always faster to use it!
(define_insn "fix_truncsfdi_sse" (define_insn "fix_truncsfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))] (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
"TARGET_64BIT && TARGET_SSE" "TARGET_64BIT && TARGET_SSE"
"cvttss2si{q}\t{%1, %0|%0, %1}" "cvttss2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")]) [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")])
(define_insn "fix_truncdfdi_sse" (define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r") [(set (match_operand:DI 0 "register_operand" "=r,r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
"TARGET_64BIT && TARGET_SSE2" "TARGET_64BIT && TARGET_SSE2"
"cvttsd2si{q}\t{%1, %0|%0, %1}" "cvttsd2si{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")]) [(set_attr "type" "sseicvt,sseicvt")
(set_attr "athlon_decode" "double,vector")])
;; Signed conversion to SImode. ;; Signed conversion to SImode.
...@@ -4480,18 +4485,20 @@ ...@@ -4480,18 +4485,20 @@
;; When SSE available, it is always faster to use it! ;; When SSE available, it is always faster to use it!
(define_insn "fix_truncsfsi_sse" (define_insn "fix_truncsfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))] (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
"TARGET_SSE" "TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}" "cvttss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")]) [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")])
(define_insn "fix_truncdfsi_sse" (define_insn "fix_truncdfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))] (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
"TARGET_SSE2" "TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}" "cvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")]) [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -4664,24 +4671,27 @@ ...@@ -4664,24 +4671,27 @@
"") "")
(define_insn "*floatsisf2_i387" (define_insn "*floatsisf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f") [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
"TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
"@ "@
fild%z1\t%1 fild%z1\t%1
# #
cvtsi2ss\t{%1, %0|%0, %1}
cvtsi2ss\t{%1, %0|%0, %1}" cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,ssecvt") [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "SF") (set_attr "mode" "SF")
(set_attr "athlon_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatsisf2_sse" (define_insn "*floatsisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x") [(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))] (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
"TARGET_SSE" "TARGET_SSE"
"cvtsi2ss\t{%1, %0|%0, %1}" "cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "SF") (set_attr "mode" "SF")
(set_attr "athlon_decode" "vector,double")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
; Avoid possible reformatting penalty on the destination by first ; Avoid possible reformatting penalty on the destination by first
...@@ -4718,24 +4728,27 @@ ...@@ -4718,24 +4728,27 @@
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatdisf2_i387" (define_insn "*floatdisf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f") [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
"TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
"@ "@
fild%z1\t%1 fild%z1\t%1
# #
cvtsi2ss{q}\t{%1, %0|%0, %1}
cvtsi2ss{q}\t{%1, %0|%0, %1}" cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,ssecvt") [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "SF") (set_attr "mode" "SF")
(set_attr "athlon_decode" "*,*,vector,double")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatdisf2_sse" (define_insn "*floatdisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x") [(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))] (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
"TARGET_64BIT && TARGET_SSE" "TARGET_64BIT && TARGET_SSE"
"cvtsi2ss{q}\t{%1, %0|%0, %1}" "cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "SF") (set_attr "mode" "SF")
(set_attr "athlon_decode" "vector,double")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
; Avoid possible reformatting penalty on the destination by first ; Avoid possible reformatting penalty on the destination by first
...@@ -4772,24 +4785,27 @@ ...@@ -4772,24 +4785,27 @@
"") "")
(define_insn "*floatsidf2_i387" (define_insn "*floatsidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f") [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))] (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
"TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
"@ "@
fild%z1\t%1 fild%z1\t%1
# #
cvtsi2sd\t{%1, %0|%0, %1}
cvtsi2sd\t{%1, %0|%0, %1}" cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,ssecvt") [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "DF") (set_attr "mode" "DF")
(set_attr "athlon_decode" "*,*,double,direct")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatsidf2_sse" (define_insn "*floatsidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y") [(set (match_operand:DF 0 "register_operand" "=Y,Y")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))] (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsi2sd\t{%1, %0|%0, %1}" "cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "DF") (set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_expand "floatdidf2" (define_expand "floatdidf2"
...@@ -4810,24 +4826,27 @@ ...@@ -4810,24 +4826,27 @@
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatdidf2_i387" (define_insn "*floatdidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f") [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))] (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
"TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
"@ "@
fild%z1\t%1 fild%z1\t%1
# #
cvtsi2sd{q}\t{%1, %0|%0, %1}
cvtsi2sd{q}\t{%1, %0|%0, %1}" cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "fmov,multi,ssecvt") [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
(set_attr "mode" "DF") (set_attr "mode" "DF")
(set_attr "athlon_decode" "*,*,double,direct")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "*floatdidf2_sse" (define_insn "*floatdidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y") [(set (match_operand:DF 0 "register_operand" "=Y,Y")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))] (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsi2sd{q}\t{%1, %0|%0, %1}" "cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "DF") (set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "fp_int_src" "true")]) (set_attr "fp_int_src" "true")])
(define_insn "floathixf2" (define_insn "floathixf2"
...@@ -6958,7 +6977,7 @@ ...@@ -6958,7 +6977,7 @@
(define_insn "*muldi3_1_rex64" (define_insn "*muldi3_1_rex64"
[(set (match_operand:DI 0 "register_operand" "=r,r,r") [(set (match_operand:DI 0 "register_operand" "=r,r,r")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:DI 2 "x86_64_general_operand" "K,e,mr"))) (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"TARGET_64BIT "TARGET_64BIT
...@@ -6969,6 +6988,15 @@ ...@@ -6969,6 +6988,15 @@
imul{q}\t{%2, %0|%0, %2}" imul{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1") (set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
(cond [(eq_attr "cpu" "athlon")
(const_string "vector")
(eq_attr "alternative" "1")
(const_string "vector")
(and (eq_attr "alternative" "2")
(match_operand 1 "memory_operand" ""))
(const_string "vector")]
(const_string "direct")))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_expand "mulsi3" (define_expand "mulsi3"
...@@ -6981,56 +7009,50 @@ ...@@ -6981,56 +7009,50 @@
(define_insn "*mulsi3_1" (define_insn "*mulsi3_1"
[(set (match_operand:SI 0 "register_operand" "=r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:SI 2 "general_operand" "K,i,mr"))) (match_operand:SI 2 "general_operand" "K,i,mr")))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
; For the {r,0,i} alternative (i.e., register <- register * immediate),
; there are two ways of writing the exact same machine instruction
; in assembly language. One, for example, is:
;
; imul $12, %eax
;
; while the other is:
;
; imul $12, %eax, %eax
;
; The first is simply short-hand for the latter. But, some assemblers,
; like the SCO OSR5 COFF assembler, don't handle the first form.
"@ "@
imul{l}\t{%2, %1, %0|%0, %1, %2} imul{l}\t{%2, %1, %0|%0, %1, %2}
imul{l}\t{%2, %1, %0|%0, %1, %2} imul{l}\t{%2, %1, %0|%0, %1, %2}
imul{l}\t{%2, %0|%0, %2}" imul{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1") (set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
(cond [(eq_attr "cpu" "athlon")
(const_string "vector")
(eq_attr "alternative" "1")
(const_string "vector")
(and (eq_attr "alternative" "2")
(match_operand 1 "memory_operand" ""))
(const_string "vector")]
(const_string "direct")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "*mulsi3_1_zext" (define_insn "*mulsi3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r,r,r") [(set (match_operand:DI 0 "register_operand" "=r,r,r")
(zero_extend:DI (zero_extend:DI
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0") (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:SI 2 "general_operand" "K,i,mr")))) (match_operand:SI 2 "general_operand" "K,i,mr"))))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"TARGET_64BIT "TARGET_64BIT
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
; For the {r,0,i} alternative (i.e., register <- register * immediate),
; there are two ways of writing the exact same machine instruction
; in assembly language. One, for example, is:
;
; imul $12, %eax
;
; while the other is:
;
; imul $12, %eax, %eax
;
; The first is simply short-hand for the latter. But, some assemblers,
; like the SCO OSR5 COFF assembler, don't handle the first form.
"@ "@
imul{l}\t{%2, %1, %k0|%k0, %1, %2} imul{l}\t{%2, %1, %k0|%k0, %1, %2}
imul{l}\t{%2, %1, %k0|%k0, %1, %2} imul{l}\t{%2, %1, %k0|%k0, %1, %2}
imul{l}\t{%2, %k0|%k0, %2}" imul{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1") (set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
(cond [(eq_attr "cpu" "athlon")
(const_string "vector")
(eq_attr "alternative" "1")
(const_string "vector")
(and (eq_attr "alternative" "2")
(match_operand 1 "memory_operand" ""))
(const_string "vector")]
(const_string "direct")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_expand "mulhi3" (define_expand "mulhi3"
...@@ -7043,18 +7065,22 @@ ...@@ -7043,18 +7065,22 @@
(define_insn "*mulhi3_1" (define_insn "*mulhi3_1"
[(set (match_operand:HI 0 "register_operand" "=r,r,r") [(set (match_operand:HI 0 "register_operand" "=r,r,r")
(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0") (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
(match_operand:HI 2 "general_operand" "K,i,mr"))) (match_operand:HI 2 "general_operand" "K,i,mr")))
(clobber (reg:CC 17))] (clobber (reg:CC 17))]
"GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
; %%% There was a note about "Assembler has weird restrictions",
; concerning alternative 1 when op1 == op0. True?
"@ "@
imul{w}\t{%2, %1, %0|%0, %1, %2} imul{w}\t{%2, %1, %0|%0, %1, %2}
imul{w}\t{%2, %1, %0|%0, %1, %2} imul{w}\t{%2, %1, %0|%0, %1, %2}
imul{w}\t{%2, %0|%0, %2}" imul{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1") (set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
(cond [(eq_attr "cpu" "athlon")
(const_string "vector")
(eq_attr "alternative" "1,2")
(const_string "vector")]
(const_string "direct")))
(set_attr "mode" "HI")]) (set_attr "mode" "HI")])
(define_expand "mulqi3" (define_expand "mulqi3"
...@@ -7075,6 +7101,10 @@ ...@@ -7075,6 +7101,10 @@
"mul{b}\t%2" "mul{b}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "direct")))
(set_attr "mode" "QI")]) (set_attr "mode" "QI")])
(define_expand "umulqihi3" (define_expand "umulqihi3"
...@@ -7097,6 +7127,10 @@ ...@@ -7097,6 +7127,10 @@
"mul{b}\t%2" "mul{b}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "direct")))
(set_attr "mode" "QI")]) (set_attr "mode" "QI")])
(define_expand "mulqihi3" (define_expand "mulqihi3"
...@@ -7117,6 +7151,10 @@ ...@@ -7117,6 +7151,10 @@
"imul{b}\t%2" "imul{b}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "direct")))
(set_attr "mode" "QI")]) (set_attr "mode" "QI")])
(define_expand "umulditi3" (define_expand "umulditi3"
...@@ -7140,6 +7178,10 @@ ...@@ -7140,6 +7178,10 @@
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
...@@ -7164,6 +7206,10 @@ ...@@ -7164,6 +7206,10 @@
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_expand "mulditi3" (define_expand "mulditi3"
...@@ -7186,6 +7232,10 @@ ...@@ -7186,6 +7232,10 @@
"imul{q}\t%2" "imul{q}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_expand "mulsidi3" (define_expand "mulsidi3"
...@@ -7208,6 +7258,10 @@ ...@@ -7208,6 +7258,10 @@
"imul{l}\t%2" "imul{l}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_expand "umuldi3_highpart" (define_expand "umuldi3_highpart"
...@@ -7241,6 +7295,10 @@ ...@@ -7241,6 +7295,10 @@
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_expand "umulsi3_highpart" (define_expand "umulsi3_highpart"
...@@ -7273,6 +7331,10 @@ ...@@ -7273,6 +7331,10 @@
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "*umulsi3_highpart_zext" (define_insn "*umulsi3_highpart_zext"
...@@ -7292,6 +7354,10 @@ ...@@ -7292,6 +7354,10 @@
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set_attr "length_immediate" "0") (set_attr "length_immediate" "0")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_expand "smuldi3_highpart" (define_expand "smuldi3_highpart"
...@@ -7324,6 +7390,10 @@ ...@@ -7324,6 +7390,10 @@
"imul{q}\t%2" "imul{q}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "DI")]) (set_attr "mode" "DI")])
(define_expand "smulsi3_highpart" (define_expand "smulsi3_highpart"
...@@ -7355,6 +7425,10 @@ ...@@ -7355,6 +7425,10 @@
"imul{l}\t%2" "imul{l}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "*smulsi3_highpart_zext" (define_insn "*smulsi3_highpart_zext"
...@@ -7373,6 +7447,10 @@ ...@@ -7373,6 +7447,10 @@
"imul{l}\t%2" "imul{l}\t%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "ppro_uops" "few") (set_attr "ppro_uops" "few")
(set (attr "athlon_decode")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double")))
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
;; The patterns that match these are at the end of this file. ;; The patterns that match these are at the end of this file.
...@@ -18125,6 +18203,102 @@ ...@@ -18125,6 +18203,102 @@
(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
"") "")
;; Imul $32bit_imm, mem, reg is vector decoded, while
;; imul $32bit_imm, reg, reg is direct decoded.
(define_peephole2
[(match_scratch:DI 3 "r")
(parallel [(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:CC 17))])]
"TARGET_K8 && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
(clobber (reg:CC 17))])]
"")
(define_peephole2
[(match_scratch:SI 3 "r")
(parallel [(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
(clobber (reg:CC 17))])]
"TARGET_K8 && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
(clobber (reg:CC 17))])]
"")
(define_peephole2
[(match_scratch:SI 3 "r")
(parallel [(set (match_operand:DI 0 "register_operand" "")
(zero_extend:DI
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
(clobber (reg:CC 17))])]
"TARGET_K8 && !optimize_size
&& (GET_CODE (operands[2]) != CONST_INT
|| !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
(clobber (reg:CC 17))])]
"")
;; imul $8/16bit_imm, regmem, reg is vector decoded.
;; Convert it into imul reg, reg
;; It would be better to force assembler to encode instruction using long
;; immediate, but there is apparently no way to do so.
(define_peephole2
[(parallel [(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC 17))])
(match_scratch:DI 3 "r")]
"TARGET_K8 && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
(clobber (reg:CC 17))])]
{
if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);
})
(define_peephole2
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC 17))])
(match_scratch:SI 3 "r")]
"TARGET_K8 && !optimize_size
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
(clobber (reg:CC 17))])]
{
if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);
})
(define_peephole2
[(parallel [(set (match_operand:HI 0 "register_operand" "")
(mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
(match_operand:HI 2 "immediate_operand" "")))
(clobber (reg:CC 17))])
(match_scratch:HI 3 "r")]
"TARGET_K8 && !optimize_size"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
(clobber (reg:CC 17))])]
{
if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);
})
;; Call-value patterns last so that the wildcard operand does not ;; Call-value patterns last so that the wildcard operand does not
;; disrupt insn-recog's switch tables. ;; disrupt insn-recog's switch tables.
...@@ -19733,49 +19907,53 @@ ...@@ -19733,49 +19907,53 @@
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "cvtsi2ss" (define_insn "cvtsi2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF (vec_merge:V4SF
(match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 1 "register_operand" "0,0")
(vec_duplicate:V4SF (vec_duplicate:V4SF
(float:SF (match_operand:SI 2 "nonimmediate_operand" "rm"))) (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
(const_int 14)))] (const_int 14)))]
"TARGET_SSE" "TARGET_SSE"
"cvtsi2ss\t{%2, %0|%0, %2}" "cvtsi2ss\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "vector,double")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "cvtsi2ssq" (define_insn "cvtsi2ssq"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF (vec_merge:V4SF
(match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 1 "register_operand" "0,0")
(vec_duplicate:V4SF (vec_duplicate:V4SF
(float:SF (match_operand:DI 2 "nonimmediate_operand" "rm"))) (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
(const_int 14)))] (const_int 14)))]
"TARGET_SSE && TARGET_64BIT" "TARGET_SSE && TARGET_64BIT"
"cvtsi2ssq\t{%2, %0|%0, %2}" "cvtsi2ssq\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "vector,double")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "cvtss2si" (define_insn "cvtss2si"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(vec_select:SI (vec_select:SI
(fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")) (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
(parallel [(const_int 0)])))] (parallel [(const_int 0)])))]
"TARGET_SSE" "TARGET_SSE"
"cvtss2si\t{%1, %0|%0, %1}" "cvtss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "athlon_decode" "double,vector")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "cvttss2si" (define_insn "cvttss2si"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(vec_select:SI (vec_select:SI
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
UNSPEC_FIX) UNSPEC_FIX)
(parallel [(const_int 0)])))] (parallel [(const_int 0)])))]
"TARGET_SSE" "TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}" "cvttss2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")
(set_attr "athlon_decode" "double,vector")])
;; MMX insns ;; MMX insns
...@@ -21352,42 +21530,45 @@ ...@@ -21352,42 +21530,45 @@
(parallel [(const_int 0)]))))] (parallel [(const_int 0)]))))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsd2si\t{%1, %0|%0, %1}" "cvtsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")])
(define_insn "cvttsd2si" (define_insn "cvttsd2si"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "xm") (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
(parallel [(const_int 0)]))] UNSPEC_FIX))] (parallel [(const_int 0)]))] UNSPEC_FIX))]
"TARGET_SSE2" "TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}" "cvttsd2si\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "SI")]) (set_attr "mode" "SI")
(set_attr "athlon_decode" "double,vector")])
(define_insn "cvtsi2sd" (define_insn "cvtsi2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x") [(set (match_operand:V2DF 0 "register_operand" "=x,x")
(vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0") (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
(vec_duplicate:V2DF (vec_duplicate:V2DF
(float:DF (float:DF
(match_operand:SI 2 "nonimmediate_operand" "rm"))) (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
(const_int 2)))] (const_int 2)))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsi2sd\t{%2, %0|%0, %2}" "cvtsi2sd\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "sseicvt")
(set_attr "mode" "DF")]) (set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")])
;; Conversions between SF and DF ;; Conversions between SF and DF
(define_insn "cvtsd2ss" (define_insn "cvtsd2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x") [(set (match_operand:V4SF 0 "register_operand" "=x,x")
(vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0") (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
(vec_duplicate:V4SF (vec_duplicate:V4SF
(float_truncate:V2SF (float_truncate:V2SF
(match_operand:V2DF 2 "nonimmediate_operand" "xm"))) (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
(const_int 14)))] (const_int 14)))]
"TARGET_SSE2" "TARGET_SSE2"
"cvtsd2ss\t{%2, %0|%0, %2}" "cvtsd2ss\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecvt") [(set_attr "type" "ssecvt")
(set_attr "athlon_decode" "vector,double")
(set_attr "mode" "SF")]) (set_attr "mode" "SF")])
(define_insn "cvtss2sd" (define_insn "cvtss2sd"
......
gcc/config/m68k/m68k.md
...@@ -3122,7 +3122,7 @@ ...@@ -3122,7 +3122,7 @@
[(parallel [(parallel
[(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4) [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
(mult:SI (match_operand:SI 1 "register_operand" "") (mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "nonimmediate_operand" ""))) (match_operand:SI 2 "register_operand" "")))
(set (subreg:SI (match_dup 0) 0) (set (subreg:SI (match_dup 0) 0)
(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
(zero_extend:DI (match_dup 2))) (zero_extend:DI (match_dup 2)))
...@@ -3161,7 +3161,7 @@ ...@@ -3161,7 +3161,7 @@
[(parallel [(parallel
[(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4) [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
(mult:SI (match_operand:SI 1 "register_operand" "") (mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "nonimmediate_operand" ""))) (match_operand:SI 2 "register_operand" "")))
(set (subreg:SI (match_dup 0) 0) (set (subreg:SI (match_dup 0) 0)
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(sign_extend:DI (match_dup 2))) (sign_extend:DI (match_dup 2)))
......
gcc/java/keyword.h
/* C code produced by gperf version 2.7 */ /* C code produced by gperf version 2.7.2 */
/* Command-line: gperf -L C -C -F , 0 -p -t -j1 -i 1 -g -o -N java_keyword -k1,4,$ keyword.gperf */ /* Command-line: gperf -L C -C -F ', 0' -p -t -j1 -i 1 -g -o -N java_keyword -k'1,4,$' keyword.gperf */
/* Keyword definition for the GNU compiler for the Java(TM) language. /* Keyword definition for the GNU compiler for the Java(TM) language.
Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc. Copyright (C) 1997, 1998, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Alexandre Petit-Bianco (apbianco@cygnus.com) Contributed by Alexandre Petit-Bianco (apbianco@cygnus.com)
This file is part of GCC. This file is part of GCC.
...@@ -44,6 +45,10 @@ const struct java_keyword *java_keyword PARAMS ((const char *, unsigned int)); ...@@ -44,6 +45,10 @@ const struct java_keyword *java_keyword PARAMS ((const char *, unsigned int));
#ifdef __GNUC__ #ifdef __GNUC__
__inline __inline
#else
#ifdef __cplusplus
inline
#endif
#endif #endif
static unsigned int static unsigned int
hash (str, len) hash (str, len)
...@@ -105,7 +110,8 @@ java_keyword (str, len) ...@@ -105,7 +110,8 @@ java_keyword (str, len)
{ {
static const struct java_keyword wordlist[] = static const struct java_keyword wordlist[] =
{ {
{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0},
{"", 0},
{"else", ELSE_TK}, {"else", ELSE_TK},
{"true", TRUE_TK}, {"true", TRUE_TK},
{"case", CASE_TK}, {"case", CASE_TK},
...@@ -163,8 +169,9 @@ java_keyword (str, len) ...@@ -163,8 +169,9 @@ java_keyword (str, len)
{"", 0}, {"", 0},
{"finally", FINALLY_TK}, {"finally", FINALLY_TK},
{"throw", THROW_TK}, {"throw", THROW_TK},
{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0},
{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0},
{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0},
{"", 0}, {"", 0}, {"", 0},
{"strictfp", STRICT_TK}, {"strictfp", STRICT_TK},
{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0},
{"private", PRIVATE_TK} {"private", PRIVATE_TK}
......
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