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riscv-gcc-1
Commit f38b27c7 by Jeffrey A Law Committed by Jeff Law
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pa.c, [...]: Support multiple assembler dialects in most assembler templates. 

        * pa.c, pa.h, pa.md: Support multiple assembler dialects in
        most assembler templates.

From-SVN: r29607
parent cc0d9ba8
Showing with 302 additions and 268 deletions
gcc/ChangeLog
......@@ -59,6 +59,9 @@ Wed Sep 22 06:25:15 1999 Jim Kingdon <http://developer.redhat.com>
Wed Sep 22 06:06:57 1999 Jeffrey A Law (law@cygnus.com)
* pa.c, pa.h, pa.md: Support multiple assembler dialects in
most assembler templates.
* pa.c (hppa_legitimize_address): Handle full offsets for PA2.0
FP loads and stores.
(following_call): Always return zero for the PA8000.
......
gcc/config/pa/pa.c
......@@ -1657,7 +1657,7 @@ singlemove_string (operands)
else if ((intval & 0x7ff) == 0)
return "ldil L'%1,%0";
else if (zdepi_cint_p (intval))
return "zdepi %Z1,%0";
return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
else
return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
}
......@@ -1770,8 +1770,8 @@ output_move_double (operands)
register. (We do this in a non-obvious way to
save a register file writeback) */
if (GET_CODE (addr) == POST_INC)
return "stws,ma %1,8(%0)\n\tstw %R1,-4(%0)";
return "stws,ma %1,-8(%0)\n\tstw %R1,12(%0)";
return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
}
else
abort();
......@@ -1790,8 +1790,8 @@ output_move_double (operands)
register. (We do this in a non-obvious way to
save a register file writeback) */
if (GET_CODE (addr) == PRE_INC)
return "stws,mb %1,8(%0)\n\tstw %R1,4(%0)";
return "stws,mb %1,-8(%0)\n\tstw %R1,4(%0)";
return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
}
else
abort();
......@@ -1817,8 +1817,8 @@ output_move_double (operands)
register. (We do this in a non-obvious way to
save a register file writeback) */
if (GET_CODE (addr) == POST_INC)
return "ldws,ma 8(%1),%0\n\tldw -4(%1),%R0";
return "ldws,ma -8(%1),%0\n\tldw 12(%1),%R0";
return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0}";
}
else
{
......@@ -1826,8 +1826,8 @@ output_move_double (operands)
address register *and* update that register. Probably
we don't need to handle this at all. */
if (GET_CODE (addr) == POST_INC)
return "ldw 4(%1),%R0\n\tldws,ma 8(%1),%0";
return "ldw 4(%1),%R0\n\tldws,ma -8(%1),%0";
return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
}
}
else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
......@@ -1844,8 +1844,8 @@ output_move_double (operands)
register. (We do this in a non-obvious way to
save a register file writeback) */
if (GET_CODE (addr) == PRE_INC)
return "ldws,mb 8(%1),%0\n\tldw 4(%1),%R0";
return "ldws,mb -8(%1),%0\n\tldw 4(%1),%R0";
return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
}
else
{
......@@ -1853,8 +1853,8 @@ output_move_double (operands)
address register *and* update that register. Probably
we don't need to handle this at all. */
if (GET_CODE (addr) == PRE_INC)
return "ldw 12(%1),%R0\n\tldws,mb 8(%1),%0";
return "ldw -4(%1),%R0\n\tldws,mb -8(%1),%0";
return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
}
}
else if (GET_CODE (addr) == PLUS
......@@ -1870,7 +1870,8 @@ output_move_double (operands)
xoperands[1] = XEXP (addr, 1);
xoperands[2] = XEXP (XEXP (addr, 0), 0);
xoperands[3] = XEXP (XEXP (addr, 0), 1);
output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
xoperands);
return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
}
else
......@@ -1881,7 +1882,8 @@ output_move_double (operands)
xoperands[1] = XEXP (addr, 1);
xoperands[2] = XEXP (XEXP (addr, 0), 0);
xoperands[3] = XEXP (XEXP (addr, 0), 1);
output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
xoperands);
return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
}
......@@ -2076,11 +2078,11 @@ output_block_move (operands, size_is_constant)
output_asm_insn ("ldi %4,%2", operands);
/* Copying loop. */
output_asm_insn ("ldws,ma 4(%1),%3", operands);
output_asm_insn ("ldws,ma 4(%1),%6", operands);
output_asm_insn ("stws,ma %3,4(%0)", operands);
output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
output_asm_insn ("addib,>= -8,%2,.-12", operands);
output_asm_insn ("stws,ma %6,4(%0)", operands);
output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
/* Handle the residual. There could be up to 7 bytes of
residual to copy! */
......@@ -2088,13 +2090,13 @@ output_block_move (operands, size_is_constant)
{
operands[4] = GEN_INT (n_bytes % 4);
if (n_bytes % 8 >= 4)
output_asm_insn ("ldws,ma 4(%1),%3", operands);
output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
if (n_bytes % 4 != 0)
output_asm_insn ("ldw 0(%1),%6", operands);
if (n_bytes % 8 >= 4)
output_asm_insn ("stws,ma %3,4(%0)", operands);
output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
if (n_bytes % 4 != 0)
output_asm_insn ("stbys,e %6,%4(%0)", operands);
output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
}
return "";
......@@ -2104,21 +2106,21 @@ output_block_move (operands, size_is_constant)
output_asm_insn ("ldi %4,%2", operands);
/* Copying loop. */
output_asm_insn ("ldhs,ma 2(%1),%3", operands);
output_asm_insn ("ldhs,ma 2(%1),%6", operands);
output_asm_insn ("sths,ma %3,2(%0)", operands);
output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
output_asm_insn ("addib,>= -4,%2,.-12", operands);
output_asm_insn ("sths,ma %6,2(%0)", operands);
output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
/* Handle the residual. */
if (n_bytes % 4 != 0)
{
if (n_bytes % 4 >= 2)
output_asm_insn ("ldhs,ma 2(%1),%3", operands);
output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
if (n_bytes % 2 != 0)
output_asm_insn ("ldb 0(%1),%6", operands);
if (n_bytes % 4 >= 2)
output_asm_insn ("sths,ma %3,2(%0)", operands);
output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
if (n_bytes % 2 != 0)
output_asm_insn ("stb %6,0(%0)", operands);
}
......@@ -2130,11 +2132,11 @@ output_block_move (operands, size_is_constant)
output_asm_insn ("ldi %4,%2", operands);
/* Copying loop. */
output_asm_insn ("ldbs,ma 1(%1),%3", operands);
output_asm_insn ("ldbs,ma 1(%1),%6", operands);
output_asm_insn ("stbs,ma %3,1(%0)", operands);
output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
output_asm_insn ("addib,>= -2,%2,.-12", operands);
output_asm_insn ("stbs,ma %6,1(%0)", operands);
output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
/* Handle the residual. */
if (n_bytes % 2 != 0)
......@@ -2218,7 +2220,7 @@ output_and (operands)
abort ();
operands[2] = GEN_INT (len);
return "extru %1,31,%2,%0";
return "{extru|extrw,u} %1,31,%2,%0";
}
else
{
......@@ -2230,7 +2232,7 @@ output_and (operands)
operands[2] = GEN_INT (p);
operands[3] = GEN_INT (len);
return "depi 0,%2,%3,%0";
return "{depi|depwi} 0,%2,%3,%0";
}
}
else
......@@ -2263,7 +2265,7 @@ output_ior (operands)
operands[2] = GEN_INT (p);
operands[3] = GEN_INT (len);
return "depi -1,%2,%3,%0";
return "{depi|depwi} -1,%2,%3,%0";
}
/* Output an ascii string. */
......@@ -3828,21 +3830,32 @@ print_operand (file, x, code)
{
case PRE_DEC:
case PRE_INC:
fputs ("s,mb", file);
if (ASSEMBLER_DIALECT == 0)
fputs ("s,mb", file);
else
fputs (",mb", file);
break;
case POST_DEC:
case POST_INC:
fputs ("s,ma", file);
if (ASSEMBLER_DIALECT == 0)
fputs ("s,ma", file);
else
fputs (",ma", file);
break;
case PLUS:
if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
|| GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
fputs ("x,s", file);
else if (code == 'F')
{
if (ASSEMBLER_DIALECT == 0)
fputs ("x,s", file);
else
fputs (",s", file);
}
else if (code == 'F' && ASSEMBLER_DIALECT == 0)
fputs ("s", file);
break;
default:
if (code == 'F')
if (code == 'F' && ASSEMBLER_DIALECT == 0)
fputs ("s", file);
break;
}
......@@ -4526,9 +4539,9 @@ output_cbranch (operands, nullify, length, negated, insn)
delay slot. */
case 4:
if (useskip)
strcpy (buf, "com%I2clr,");
strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
else
strcpy (buf, "com%I2b,");
strcpy (buf, "{com%I2b,|cmp%I2b,}");
if (negated)
strcat (buf, "%B3");
else
......@@ -4551,7 +4564,7 @@ output_cbranch (operands, nullify, length, negated, insn)
&& ! forward_branch_p (insn)
&& nullify)
{
strcpy (buf, "com%I2b,");
strcpy (buf, "{com%I2b,|cmp%I2b,}");
if (negated)
strcat (buf, "%S3");
else
......@@ -4567,7 +4580,7 @@ output_cbranch (operands, nullify, length, negated, insn)
&& VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
- insn_addresses[INSN_UID (insn)] - 8))
{
strcpy (buf, "com%I2b,");
strcpy (buf, "{com%I2b,|cmp%I2b,}");
if (negated)
strcat (buf, "%B3 %2,%r1,%0%#");
else
......@@ -4575,7 +4588,7 @@ output_cbranch (operands, nullify, length, negated, insn)
}
else
{
strcpy (buf, "com%I2clr,");
strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
if (negated)
strcat (buf, "%S3");
else
......@@ -4596,9 +4609,9 @@ output_cbranch (operands, nullify, length, negated, insn)
/* Create a reversed conditional branch which branches around
the following insns. */
if (negated)
strcpy (buf, "com%I2b,%S3,n %2,%r1,.+20");
strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
else
strcpy (buf, "com%I2b,%B3,n %2,%r1,.+20");
strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
output_asm_insn (buf, operands);
/* Output an insn to save %r1. */
......@@ -4621,9 +4634,9 @@ output_cbranch (operands, nullify, length, negated, insn)
/* Create a reversed conditional branch which branches around
the following insns. */
if (negated)
strcpy (buf, "com%I2b,%S3,n %2,%r1,.+28");
strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
else
strcpy (buf, "com%I2b,%B3,n %2,%r1,.+28");
strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
output_asm_insn (buf, operands);
/* Output an insn to save %r1. */
......@@ -4639,7 +4652,8 @@ output_cbranch (operands, nullify, length, negated, insn)
xoperands[3] = operands[3];
xoperands[4] = gen_label_rtx ();
output_asm_insn ("bl .+8,%%r1\n\taddil L'%l0-%l4,%%r1", xoperands);
output_asm_insn ("{bl|b,l} .+8,%%r1\n\taddil L'%l0-%l4,%%r1",
xoperands);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
CODE_LABEL_NUMBER (xoperands[4]));
output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
......@@ -4707,7 +4721,7 @@ output_bb (operands, nullify, length, negated, insn, which)
delay slot. */
case 4:
if (useskip)
strcpy (buf, "extrs,");
strcpy (buf, "{extrs,|extrw,s,}");
else
strcpy (buf, "bb,");
if ((which == 0 && negated)
......@@ -4770,7 +4784,7 @@ output_bb (operands, nullify, length, negated, insn, which)
}
else
{
strcpy (buf, "extrs,");
strcpy (buf, "{extrs,|extrw,s,}");
if ((which == 0 && negated)
|| (which == 1 && ! negated))
strcat (buf, "<");
......@@ -4845,24 +4859,24 @@ output_bvb (operands, nullify, length, negated, insn, which)
delay slot. */
case 4:
if (useskip)
strcpy (buf, "vextrs,");
strcpy (buf, "{vextrs,|extrw,s,}");
else
strcpy (buf, "bvb,");
strcpy (buf, "{bvb,|bb,}");
if ((which == 0 && negated)
|| (which == 1 && ! negated))
strcat (buf, ">=");
else
strcat (buf, "<");
if (useskip)
strcat (buf, " %0,1,%%r0");
strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
else if (nullify && negated)
strcat (buf, ",n %0,%3");
strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
else if (nullify && ! negated)
strcat (buf, ",n %0,%2");
strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
else if (! nullify && negated)
strcat (buf, "%0,%3");
strcat (buf, "{%0,%3|%0,%%sar,%3}");
else if (! nullify && ! negated)
strcat (buf, " %0,%2");
strcat (buf, "{ %0,%2| %0,%%sar,%2}");
break;
/* All long conditionals. Note an short backward branch with an
......@@ -4875,16 +4889,16 @@ output_bvb (operands, nullify, length, negated, insn, which)
&& ! forward_branch_p (insn)
&& nullify)
{
strcpy (buf, "bvb,");
strcpy (buf, "{bvb,|bb,}");
if ((which == 0 && negated)
|| (which == 1 && ! negated))
strcat (buf, "<");
else
strcat (buf, ">=");
if (negated)
strcat (buf, ",n %0,.+12\n\tb %3");
strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
else
strcat (buf, ",n %0,.+12\n\tb %2");
strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
}
/* Handle short backwards branch with an unfilled delay slot.
Using a bb;nop rather than extrs;bl saves 1 cycle for both
......@@ -4895,33 +4909,33 @@ output_bvb (operands, nullify, length, negated, insn, which)
&& VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
- insn_addresses[INSN_UID (insn)] - 8))
{
strcpy (buf, "bvb,");
strcpy (buf, "{bvb,|bb,}");
if ((which == 0 && negated)
|| (which == 1 && ! negated))
strcat (buf, ">=");
else
strcat (buf, "<");
if (negated)
strcat (buf, " %0,%3%#");
strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
else
strcat (buf, " %0,%2%#");
strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
}
else
{
strcpy (buf, "vextrs,");
strcpy (buf, "{vextrs,|extrw,s,}");
if ((which == 0 && negated)
|| (which == 1 && ! negated))
strcat (buf, "<");
else
strcat (buf, ">=");
if (nullify && negated)
strcat (buf, " %0,1,%%r0\n\tb,n %3");
strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
else if (nullify && ! negated)
strcat (buf, " %0,1,%%r0\n\tb,n %2");
strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
else if (negated)
strcat (buf, " %0,1,%%r0\n\tb %3");
strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
else
strcat (buf, " %0,1,%%r0\n\tb %2");
strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
}
break;
......@@ -4951,10 +4965,10 @@ output_dbra (operands, insn, which_alternative)
return "ldo %1(%0),%0";
else if (which_alternative == 1)
{
output_asm_insn ("fstws %0,-16(%%r30)",operands);
output_asm_insn ("{fstws|fstw} %0,-16(%%r30)",operands);
output_asm_insn ("ldw -16(%%r30),%4",operands);
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
return "fldws -16(%%r30),%0";
return "{fldws|fldw} -16(%%r30),%0";
}
else
{
......@@ -5016,12 +5030,12 @@ output_dbra (operands, insn, which_alternative)
/* Move loop counter from FP register to MEM then into a GR,
increment the GR, store the GR into MEM, and finally reload
the FP register from MEM from within the branch's delay slot. */
output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
if (get_attr_length (insn) == 24)
return "comb,%S2 %%r0,%4,%3\n\tfldws -16(%%r30),%0";
return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
else
return "comclr,%B2 %%r0,%4,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
}
/* Deal with gross reload from memory case. */
else
......@@ -5058,7 +5072,7 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
else if (which_alternative == 1)
{
output_asm_insn ("stw %1,-16(%%r30)",operands);
return "fldws -16(%%r30),%0";
return "{fldws|fldw} -16(%%r30),%0";
}
else if (which_alternative == 2)
return "stw %1,%0";
......@@ -5125,9 +5139,9 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
the FP register from MEM from within the branch's delay slot. */
output_asm_insn ("stw %1,-16(%%r30)",operands);
if (get_attr_length (insn) == 12)
return "comb,%S2 %%r0,%1,%3\n\tfldws -16(%%r30),%0";
return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
else
return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
}
/* Deal with gross reload from memory case. */
else if (which_alternative == 2)
......@@ -5135,17 +5149,17 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
/* Reload loop counter from memory, the store back to memory
happens in the branch's delay slot. */
if (get_attr_length (insn) == 8)
return "comb,%S2 %%r0,%1,%3\n\tstw %1,%0";
return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
else
return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
}
/* Handle SAR as a destination. */
else
{
if (get_attr_length (insn) == 8)
return "comb,%S2 %%r0,%1,%3\n\tmtsar %r1";
return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
else
return "comclr,%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
}
}
......@@ -5174,7 +5188,7 @@ output_millicode_call (insn, call_dest)
&& get_attr_length (insn) == 4))
{
xoperands[0] = call_dest;
output_asm_insn ("bl %0,%%r31%#", xoperands);
output_asm_insn ("{bl|b,l} %0,%%r31%#", xoperands);
return "";
}
......@@ -5206,7 +5220,7 @@ output_millicode_call (insn, call_dest)
{
xoperands[0] = call_dest;
output_asm_insn ("ldil L%%%0,%%r31", xoperands);
output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands);
output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%%r31)", xoperands);
output_asm_insn ("nop", xoperands);
}
/* Pure portable runtime doesn't allow be/ble; we also don't have
......@@ -5235,7 +5249,7 @@ output_millicode_call (insn, call_dest)
xoperands[0] = call_dest;
xoperands[1] = gen_label_rtx ();
/* Get our address + 8 into %r1. */
output_asm_insn ("bl .+8,%%r1", xoperands);
output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
/* Add %r1 to the offset of our target from the next insn. */
output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
......@@ -5288,13 +5302,14 @@ output_millicode_call (insn, call_dest)
xoperands[0] = call_dest;
xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
if (! VAL_14_BITS_P (distance))
output_asm_insn ("bl %0,%%r31\n\tnop\n\tb,n %1", xoperands);
output_asm_insn ("{bl|b,l} %0,%%r31\n\tnop\n\tb,n %1", xoperands);
else
{
xoperands[3] = gen_label_rtx ();
output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands);
xoperands[2] = gen_label_rtx ();
output_asm_insn ("\n\t{bl|b,l} %0,%%r31\n\tldo %1-%3(%%r31),%%r31",
xoperands);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
CODE_LABEL_NUMBER (xoperands[3]));
CODE_LABEL_NUMBER (xoperands[2]));
}
/* Delete the jump. */
......@@ -5333,7 +5348,7 @@ output_call (insn, call_dest)
&& get_attr_length (insn) == 4))
{
xoperands[0] = call_dest;
output_asm_insn ("bl %0,%%r2%#", xoperands);
output_asm_insn ("{bl|b,l} %0,%%r2%#", xoperands);
return "";
}
......@@ -5387,14 +5402,16 @@ output_call (insn, call_dest)
{
xoperands[0] = XEXP (use, 0);
xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands);
output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
xoperands);
output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
}
else
{
xoperands[0] = XEXP (use, 0);
xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands);
output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
xoperands);
output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
}
......@@ -5468,7 +5485,7 @@ output_call (insn, call_dest)
output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
/* Get our address + 8 into %r1. */
output_asm_insn ("bl .+8,%%r1", xoperands);
output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
/* Add %r1 to the offset of dyncall from the next insn. */
output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
......@@ -5496,7 +5513,8 @@ output_call (insn, call_dest)
/* Get the high part of the address of $dyncall into %r2, then
add in the low part in the branch instruction. */
output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
output_asm_insn ("{ble|be,l} R%%$$dyncall(%%sr4,%%r2)",
xoperands);
/* Copy the return pointer into both %r31 and %r2. */
output_asm_insn ("copy %%r31,%%r2", xoperands);
......@@ -5537,11 +5555,12 @@ output_call (insn, call_dest)
xoperands[0] = call_dest;
xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
if (! VAL_14_BITS_P (distance))
output_asm_insn ("bl %0,%%r2\n\tnop\n\tb,n %1", xoperands);
output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
else
{
xoperands[3] = gen_label_rtx ();
output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands);
output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
xoperands);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
CODE_LABEL_NUMBER (xoperands[3]));
}
......
gcc/config/pa/pa.h
......@@ -200,6 +200,10 @@ extern int target_flags;
{ "arch=", &pa_arch_string, "Specify architecture for code generation. Values are 1.0, 1.1, and 2.0. 2.0 requires gas snapshot 19990413 or later." }\
}
/* Specify the dialect of assembler to use. New mnemonics is dialect one
and the old mnemonics are dialect zero. */
#define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
#define OVERRIDE_OPTIONS override_options ()
/* stabs-in-som is nearly identical to stabs-in-elf. To avoid useless
......@@ -1158,7 +1162,10 @@ extern int may_call_alloca;
{ \
fputs ("\tldw 36(%r22),%r21\n", FILE); \
fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
fputs ("\tdepi 0,31,2,%r21\n", FILE); \
if (ASSEMBLER_DIALECT == 0) \
fputs ("\tdepi 0,31,2,%r21\n", FILE); \
else \
fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
fputs ("\tldw 4(%r21),%r19\n", FILE); \
fputs ("\tldw 0(%r21),%r21\n", FILE); \
fputs ("\tldsid (%r21),%r1\n", FILE); \
......
gcc/config/pa/pa.md
......@@ -616,7 +616,7 @@
[(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith11_operand" "rI")]))]
""
"com%I2clr,%B3 %2,%1,%0\;ldi 1,%0"
"{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -629,7 +629,7 @@
[(match_operand:SI 4 "register_operand" "r")
(match_operand:SI 5 "arith11_operand" "rI")])))]
""
"com%I2clr,%S3 %2,%1,%%r0\;com%I5clr,%B6 %5,%4,%0\;ldi 1,%0"
"{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
[(set_attr "type" "binary")
(set_attr "length" "12")])
......@@ -641,7 +641,7 @@
[(match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith11_operand" "rI")])))]
""
"com%I2clr,%B3 %2,%1,%0\;ldi -1,%0"
"{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -657,7 +657,7 @@
(match_operand:SI 3 "arith11_operand" "rI"))
(match_operand:SI 1 "register_operand" "r")))]
""
"sub%I3 %3,%2,%%r0\;addc %%r0,%1,%0"
"sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -669,7 +669,7 @@
(match_operand:SI 3 "register_operand" "r"))
(match_operand:SI 1 "register_operand" "r")))]
""
"sub %2,%3,%%r0\;addc %%r0,%1,%0"
"sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -682,7 +682,7 @@
(match_operand:SI 3 "int11_operand" "I"))
(match_operand:SI 1 "register_operand" "r")))]
""
"addi %k3,%2,%%r0\;addc %%r0,%1,%0"
"addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -694,8 +694,8 @@
(match_operand:SI 1 "register_operand" "0,?r")))]
""
"@
com%I3clr,%B4 %3,%2,%%r0\;addi 1,%0,%0
com%I3clr,%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
{com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
{com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
[(set_attr "type" "binary,binary")
(set_attr "length" "8,12")])
......@@ -705,7 +705,7 @@
(gtu:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "arith11_operand" "rI"))))]
""
"sub%I3 %3,%2,%%r0\;subb %1,0,%0"
"sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -716,7 +716,7 @@
(match_operand:SI 3 "arith11_operand" "rI")))
(match_operand:SI 4 "register_operand" "r")))]
""
"sub%I3 %3,%2,%%r0\;subb %1,%4,%0"
"sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -728,7 +728,7 @@
(ltu:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "register_operand" "r"))))]
""
"sub %2,%3,%%r0\;subb %1,0,%0"
"sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -739,7 +739,7 @@
(match_operand:SI 3 "register_operand" "r")))
(match_operand:SI 4 "register_operand" "r")))]
""
"sub %2,%3,%%r0\;subb %1,%4,%0"
"sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -752,7 +752,7 @@
(leu:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "int11_operand" "I"))))]
""
"addi %k3,%2,%%r0\;subb %1,0,%0"
"addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -763,7 +763,7 @@
(match_operand:SI 3 "int11_operand" "I")))
(match_operand:SI 4 "register_operand" "r")))]
""
"addi %k3,%2,%%r0\;subb %1,%4,%0"
"addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -775,8 +775,8 @@
(match_operand:SI 3 "arith11_operand" "rI,rI")])))]
""
"@
com%I3clr,%B4 %3,%2,%%r0\;addi -1,%0,%0
com%I3clr,%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
{com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
{com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
[(set_attr "type" "binary,binary")
(set_attr "length" "8,12")])
......@@ -789,9 +789,9 @@
(match_operand:SI 2 "arith11_operand" "r,I,M")))]
""
"@
comclr,> %2,%0,%%r0\;copy %2,%0
comiclr,> %2,%0,%%r0\;ldi %2,%0
comclr,> %1,%r2,%0\;copy %1,%0"
{comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
{comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
{comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
[(set_attr "type" "multi,multi,multi")
(set_attr "length" "8,8,8")])
......@@ -801,8 +801,8 @@
(match_operand:SI 2 "arith11_operand" "r,I")))]
""
"@
comclr,>> %2,%0,%%r0\;copy %2,%0
comiclr,>> %2,%0,%%r0\;ldi %2,%0"
{comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
{comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
[(set_attr "type" "multi,multi")
(set_attr "length" "8,8")])
......@@ -812,9 +812,9 @@
(match_operand:SI 2 "arith11_operand" "r,I,M")))]
""
"@
comclr,< %2,%0,%%r0\;copy %2,%0
comiclr,< %2,%0,%%r0\;ldi %2,%0
comclr,< %1,%r2,%0\;copy %1,%0"
{comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
{comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
{comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
[(set_attr "type" "multi,multi,multi")
(set_attr "length" "8,8,8")])
......@@ -824,8 +824,8 @@
(match_operand:SI 2 "arith11_operand" "r,I")))]
""
"@
comclr,<< %2,%0,%%r0\;copy %2,%0
comiclr,<< %2,%0,%%r0\;ldi %2,%0"
{comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
{comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
[(set_attr "type" "multi,multi")
(set_attr "length" "8,8")])
......@@ -874,11 +874,11 @@
(const_int 0)))]
""
"@
com%I4clr,%S5 %4,%3,%%r0\;ldi 0,%0
com%I4clr,%B5 %4,%3,%0\;copy %1,%0
com%I4clr,%B5 %4,%3,%0\;ldi %1,%0
com%I4clr,%B5 %4,%3,%0\;ldil L'%1,%0
com%I4clr,%B5 %4,%3,%0\;zdepi %Z1,%0"
{com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi 0,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;copy %1,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldi %1,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldil L'%1,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
[(set_attr "type" "multi,multi,multi,multi,nullshift")
(set_attr "length" "8,8,8,8,8")])
......@@ -892,14 +892,14 @@
(match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
""
"@
com%I4clr,%S5 %4,%3,%%r0\;copy %2,%0
com%I4clr,%S5 %4,%3,%%r0\;ldi %2,%0
com%I4clr,%S5 %4,%3,%%r0\;ldil L'%2,%0
com%I4clr,%S5 %4,%3,%%r0\;zdepi %Z2,%0
com%I4clr,%B5 %4,%3,%%r0\;copy %1,%0
com%I4clr,%B5 %4,%3,%%r0\;ldi %1,%0
com%I4clr,%B5 %4,%3,%%r0\;ldil L'%1,%0
com%I4clr,%B5 %4,%3,%%r0\;zdepi %Z1,%0"
{com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
{com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
{com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
{com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
{com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
[(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
(set_attr "length" "8,8,8,8,8,8,8,8")])
......@@ -1407,7 +1407,7 @@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
zdepi %Z1,%0
{zdepi|depwi,z} %Z1,%0
ldw%M1 %1,%0
stw%M0 %r1,%0
mtsar %r1
......@@ -1430,7 +1430,7 @@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
zdepi %Z1,%0
{zdepi|depwi,z} %Z1,%0
ldw%M1 %1,%0
stw%M0 %r1,%0
mtsar %r1"
......@@ -1450,9 +1450,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"ldwx %1(%2),%0\";
return \"{ldwx|ldw} %1(%2),%0\";
else
return \"ldwx %2(%1),%0\";
return \"{ldwx|ldw} %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1469,9 +1469,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"ldwx %2(%1),%0\";
return \"{ldwx|ldw} %2(%1),%0\";
else
return \"ldwx %1(%2),%0\";
return \"{ldwx|ldw} %1(%2),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1501,8 +1501,8 @@
"*
{
if (INTVAL (operands[2]) < 0)
return \"ldwm %2(%1),%0\";
return \"ldws,mb %2(%1),%0\";
return \"{ldwm|ldw,mb} %2(%1),%0\";
return \"{ldws|ldw},mb %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1517,8 +1517,8 @@
"*
{
if (INTVAL (operands[1]) < 0)
return \"stwm %r2,%1(%0)\";
return \"stws,mb %r2,%1(%0)\";
return \"{stwm|stw,mb} %r2,%1(%0)\";
return \"{stws|stw},mb %r2,%1(%0)\";
}"
[(set_attr "type" "store")
(set_attr "length" "4")])
......@@ -1533,8 +1533,8 @@
"*
{
if (INTVAL (operands[2]) > 0)
return \"ldwm %2(%1),%0\";
return \"ldws,ma %2(%1),%0\";
return \"{ldwm|ldw,ma} %2(%1),%0\";
return \"{ldws|ldw},ma %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1562,8 +1562,8 @@
"*
{
if (INTVAL (operands[2]) > 0)
return \"stwm %r1,%2(%0)\";
return \"stws,ma %r1,%2(%0)\";
return \"{stwm|stw,ma} %r1,%2(%0)\";
return \"{stws|stw},ma %r1,%2(%0)\";
}"
[(set_attr "type" "store")
(set_attr "length" "4")])
......@@ -1584,8 +1584,8 @@
xoperands[0] = operands[0];
xoperands[1] = operands[1];
xoperands[2] = label_rtx;
output_asm_insn (\"bl .+8,%0\", xoperands);
output_asm_insn (\"depi 0,31,2,%0\", xoperands);
output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
CODE_LABEL_NUMBER (label_rtx));
......@@ -1676,7 +1676,7 @@
"reload_completed"
"@
addil L'%G2,%1
ldil L'%G2,%0\;addl %0,%1,%0"
ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
[(set_attr "type" "binary,binary")
(set_attr "length" "4,8")])
......@@ -1791,7 +1791,7 @@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
zdepi %Z1,%0
{zdepi|depwi,z} %Z1,%0
ldh%M1 %1,%0
sth%M0 %r1,%0
mtsar %r1
......@@ -1812,9 +1812,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"ldhx %1(%2),%0\";
return \"{ldhx|ldh} %1(%2),%0\";
else
return \"ldhx %2(%1),%0\";
return \"{ldhx|ldh} %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1831,9 +1831,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"ldhx %2(%1),%0\";
return \"{ldhx|ldh} %2(%1),%0\";
else
return \"ldhx %1(%2),%0\";
return \"{ldhx|ldh} %1(%2),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1853,9 +1853,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"ldhx %1(%2),%0\";
return \"{ldhx|ldh} %1(%2),%0\";
else
return \"ldhx %2(%1),%0\";
return \"{ldhx|ldh} %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1874,9 +1874,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"ldhx %2(%1),%0\";
return \"{ldhx|ldh} %2(%1),%0\";
else
return \"ldhx %1(%2),%0\";
return \"{ldhx|ldh} %1(%2),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1888,7 +1888,7 @@
(set (match_dup 1)
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ldhs,mb %2(%1),%0"
"{ldhs|ldh},mb %2(%1),%0"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1902,7 +1902,7 @@
(set (match_dup 1)
(plus:SI (match_dup 1) (match_dup 2)))]
""
"ldhs,mb %2(%1),%0"
"{ldhs|ldh},mb %2(%1),%0"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1913,7 +1913,7 @@
(set (match_dup 0)
(plus:SI (match_dup 0) (match_dup 1)))]
""
"sths,mb %r2,%1(%0)"
"{sths|sth},mb %r2,%1(%0)"
[(set_attr "type" "store")
(set_attr "length" "4")])
......@@ -1953,7 +1953,7 @@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
zdepi %Z1,%0
{zdepi|depwi,z} %Z1,%0
ldb%M1 %1,%0
stb%M0 %r1,%0
mtsar %r1
......@@ -1974,9 +1974,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"ldbx %1(%2),%0\";
return \"{ldbx|ldb} %1(%2),%0\";
else
return \"ldbx %2(%1),%0\";
return \"{ldbx|ldb} %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -1993,9 +1993,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"ldbx %2(%1),%0\";
return \"{ldbx|ldb} %2(%1),%0\";
else
return \"ldbx %1(%2),%0\";
return \"{ldbx|ldb} %1(%2),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2015,9 +2015,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"ldbx %1(%2),%0\";
return \"{ldbx|ldb} %1(%2),%0\";
else
return \"ldbx %2(%1),%0\";
return \"{ldbx|ldb} %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2036,9 +2036,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"ldbx %2(%1),%0\";
return \"{ldbx|ldb} %2(%1),%0\";
else
return \"ldbx %1(%2),%0\";
return \"{ldbx|ldb} %1(%2),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2057,9 +2057,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"ldbx %1(%2),%0\";
return \"{ldbx|ldb} %1(%2),%0\";
else
return \"ldbx %2(%1),%0\";
return \"{ldbx|ldb} %2(%1),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2078,9 +2078,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"ldbx %2(%1),%0\";
return \"{ldbx|ldb} %2(%1),%0\";
else
return \"ldbx %1(%2),%0\";
return \"{ldbx|ldb} %1(%2),%0\";
}"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2091,7 +2091,7 @@
(match_operand:SI 2 "int5_operand" "L"))))
(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
""
"ldbs,mb %2(%1),%0"
"{ldbs|ldb},mb %2(%1),%0"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2103,7 +2103,7 @@
(match_operand:SI 2 "int5_operand" "L")))))
(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
""
"ldbs,mb %2(%1),%0"
"{ldbs|ldb},mb %2(%1),%0"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2114,7 +2114,7 @@
(match_operand:SI 2 "int5_operand" "L")))))
(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
""
"ldbs,mb %2(%1),%0"
"{ldbs|ldb},mb %2(%1),%0"
[(set_attr "type" "load")
(set_attr "length" "4")])
......@@ -2125,7 +2125,7 @@
(set (match_dup 0)
(plus:SI (match_dup 0) (match_dup 1)))]
""
"stbs,mb %r2,%1(%0)"
"{stbs|stb},mb %r2,%1(%0)"
[(set_attr "type" "store")
(set_attr "length" "4")])
......@@ -2332,9 +2332,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"flddx %1(%2),%0\";
return \"{flddx|fldd} %1(%2),%0\";
else
return \"flddx %2(%1),%0\";
return \"{flddx|fldd} %2(%1),%0\";
}"
[(set_attr "type" "fpload")
(set_attr "length" "4")])
......@@ -2351,9 +2351,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"flddx %2(%1),%0\";
return \"{flddx|fldd} %2(%1),%0\";
else
return \"flddx %1(%2),%0\";
return \"{flddx|fldd} %1(%2),%0\";
}"
[(set_attr "type" "fpload")
(set_attr "length" "4")])
......@@ -2370,9 +2370,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"fstdx %0,%1(%2)\";
return \"{fstdx|fstd} %0,%1(%2)\";
else
return \"fstdx %0,%2(%1)\";
return \"{fstdx|fstd} %0,%2(%1)\";
}"
[(set_attr "type" "fpstore")
(set_attr "length" "4")])
......@@ -2389,9 +2389,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"fstdx %0,%2(%1)\";
return \"{fstdx|fstd} %0,%2(%1)\";
else
return \"fstdx %0,%1(%2)\";
return \"{fstdx|fstd} %0,%1(%2)\";
}"
[(set_attr "type" "fpstore")
(set_attr "length" "4")])
......@@ -2635,9 +2635,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"fldwx %1(%2),%0\";
return \"{fldwx|fldw} %1(%2),%0\";
else
return \"fldwx %2(%1),%0\";
return \"{fldwx|fldw} %2(%1),%0\";
}"
[(set_attr "type" "fpload")
(set_attr "length" "4")])
......@@ -2654,9 +2654,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"fldwx %2(%1),%0\";
return \"{fldwx|fldw} %2(%1),%0\";
else
return \"fldwx %1(%2),%0\";
return \"{fldwx|fldw} %1(%2),%0\";
}"
[(set_attr "type" "fpload")
(set_attr "length" "4")])
......@@ -2673,9 +2673,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[2] == hard_frame_pointer_rtx
|| operands[2] == stack_pointer_rtx)
return \"fstwx %0,%1(%2)\";
return \"{fstwx|fstw} %0,%1(%2)\";
else
return \"fstwx %0,%2(%1)\";
return \"{fstwx|fstw} %0,%2(%1)\";
}"
[(set_attr "type" "fpstore")
(set_attr "length" "4")])
......@@ -2692,9 +2692,9 @@
pseudos that don't get hard registers. Deal with it. */
if (operands[1] == hard_frame_pointer_rtx
|| operands[1] == stack_pointer_rtx)
return \"fstwx %0,%2(%1)\";
return \"{fstwx|fstw} %0,%2(%1)\";
else
return \"fstwx %0,%1(%2)\";
return \"{fstwx|fstw} %0,%1(%2)\";
}"
[(set_attr "type" "fpstore")
(set_attr "length" "4")])
......@@ -2719,7 +2719,7 @@
(match_operand:HI 1 "move_operand" "r,RQ")))]
"GET_CODE (operands[1]) != CONST_INT"
"@
extru %1,31,16,%0
{extru|extrw,u} %1,31,16,%0
ldh%M1 %1,%0"
[(set_attr "type" "shift,load")
(set_attr "length" "4,4")])
......@@ -2737,7 +2737,7 @@
(match_operand:QI 1 "move_operand" "r,RQ")))]
"GET_CODE (operands[1]) != CONST_INT"
"@
extru %1,31,8,%0
{extru|extrw,u} %1,31,8,%0
ldb%M1 %1,%0"
[(set_attr "type" "shift,load")
(set_attr "length" "4,4")])
......@@ -2755,7 +2755,7 @@
(match_operand:QI 1 "move_operand" "r,RQ")))]
"GET_CODE (operands[1]) != CONST_INT"
"@
extru %1,31,8,%0
{extru|extrw,u} %1,31,8,%0
ldb%M1 %1,%0"
[(set_attr "type" "shift,load")
(set_attr "length" "4,4")])
......@@ -2766,7 +2766,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
""
"extrs %1,31,16,%0"
"{extrs|extrw,s} %1,31,16,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -2774,7 +2774,7 @@
[(set (match_operand:HI 0 "register_operand" "=r")
(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
""
"extrs %1,31,8,%0"
"{extrs|extrw,s} %1,31,8,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -2782,7 +2782,7 @@
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
""
"extrs %1,31,8,%0"
"{extrs|extrw,s} %1,31,8,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -2793,7 +2793,7 @@
(float_extend:DF
(match_operand:SF 1 "register_operand" "f")))]
"! TARGET_SOFT_FLOAT"
"fcnvff,sgl,dbl %1,%0"
"{fcnvff|fcnv},sgl,dbl %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2802,7 +2802,7 @@
(float_truncate:SF
(match_operand:DF 1 "register_operand" "f")))]
"! TARGET_SOFT_FLOAT"
"fcnvff,dbl,sgl %1,%0"
"{fcnvff|fcnv},dbl,sgl %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2821,7 +2821,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float:SF (match_operand:SI 1 "const_int_operand" "m")))]
"! TARGET_SOFT_FLOAT"
"fldw%F1 %1,%0\;fcnvxf,sgl,sgl %0,%0"
"fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "8")])
......@@ -2829,7 +2829,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float:SF (match_operand:SI 1 "register_operand" "f")))]
"! TARGET_SOFT_FLOAT"
"fcnvxf,sgl,sgl %1,%0"
"{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2840,7 +2840,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float:DF (match_operand:SI 1 "const_int_operand" "m")))]
"! TARGET_SOFT_FLOAT"
"fldw%F1 %1,%0\;fcnvxf,sgl,dbl %0,%0"
"fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "8")])
......@@ -2848,7 +2848,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float:DF (match_operand:SI 1 "register_operand" "f")))]
"! TARGET_SOFT_FLOAT"
"fcnvxf,sgl,dbl %1,%0"
"{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2892,7 +2892,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float:SF (match_operand:DI 1 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
"fcnvxf,dbl,sgl %1,%0"
"{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2900,7 +2900,7 @@
[(set (match_operand:DF 0 "register_operand" "=f")
(float:DF (match_operand:DI 1 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
"fcnvxf,dbl,dbl %1,%0"
"{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2911,7 +2911,7 @@
[(set (match_operand:SI 0 "register_operand" "=f")
(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
"! TARGET_SOFT_FLOAT"
"fcnvfxt,sgl,sgl %1,%0"
"{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2919,7 +2919,7 @@
[(set (match_operand:SI 0 "register_operand" "=f")
(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
"! TARGET_SOFT_FLOAT"
"fcnvfxt,dbl,sgl %1,%0"
"{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2927,7 +2927,7 @@
[(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
"fcnvfxt,sgl,dbl %1,%0"
"{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -2935,7 +2935,7 @@
[(set (match_operand:DI 0 "register_operand" "=f")
(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
"fcnvfxt,dbl,dbl %1,%0"
"{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
[(set_attr "type" "fpalu")
(set_attr "length" "4")])
......@@ -3022,12 +3022,12 @@
if (GET_CODE (operands[2]) == CONST_INT)
{
if (INTVAL (operands[2]) >= 0)
return \"addi %2,%R1,%R0\;addc %1,0,%0\";
return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
else
return \"addi %2,%R1,%R0\;subb %1,0,%0\";
return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
}
else
return \"add %R2,%R1,%R0\;addc %2,%1,%0\";
return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
}"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -3112,7 +3112,7 @@
(match_operand:SI 2 "arith_operand" "r,J")))]
""
"@
addl %1,%2,%0
{addl|add,l} %1,%2,%0
ldo %2(%1),%0"
[(set_attr "type" "binary,binary")
(set_attr "pa_combine_type" "addmove")
......@@ -3130,9 +3130,9 @@
"*
{
if (GET_CODE (operands[3]) == CONST_INT)
return \"ldo %3(%2),%0\;addl %1,%0,%0\";
return \"ldo %3(%2),%0\;{addl|add,l} %1,%0,%0\";
else
return \"addl %3,%2,%0\;addl %1,%0,%0\";
return \"{addl|add,l} %3,%2,%0\;{addl|add,l} %1,%0,%0\";
}"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -3149,7 +3149,7 @@
(minus:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "register_operand" "r")))]
""
"sub %R1,%R2,%R0\;subb %1,%2,%0"
"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
[(set_attr "type" "binary")
(set_attr "length" "8")])
......@@ -3627,7 +3627,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
""
"sub %%r0,%R1,%R0\;subb %%r0,%1,%0"
"sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
[(set_attr "type" "unary")
(set_attr "length" "8")])
......@@ -4195,7 +4195,7 @@
(match_operand:SI 3 "shadd_operand" ""))
(match_operand:SI 1 "register_operand" "r")))]
""
"sh%O3addl %2,%1,%0"
"{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
[(set_attr "type" "binary")
(set_attr "length" "4")])
......@@ -4216,8 +4216,8 @@
(match_operand:SI 3 "const_int_operand" "r,J")))]
"reload_in_progress"
"@
sh%O4addl %2,%1,%0\;addl %3,%0,%0
sh%O4addl %2,%1,%0\;ldo %3(%0),%0"
{sh%O4addl %2,%1,%0|shladd,l %2,%O4,%1,%0}\;{addl|add,l} %3,%0,%0
{sh%O4addl %2,%1,%0|shladd,l %2,%O4,%1,%0}\;ldo %3(%0),%0"
[(set_attr "type" "multi")
(set_attr "length" "8")])
......@@ -4287,7 +4287,7 @@
(ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "n")))]
""
"zdep %1,%P2,%L2,%0"
"{zdep|depw,z} %1,%P2,%L2,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4304,8 +4304,8 @@
(match_operand:SI 2 "register_operand" "q,q"))))]
""
"@
zvdep %1,32,%0
zvdepi %1,32,%0"
{zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
{zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
[(set_attr "type" "shift,shift")
(set_attr "length" "4,4")])
......@@ -4320,7 +4320,7 @@
int x = INTVAL (operands[1]);
operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
operands[1] = GEN_INT ((x & 0xf) - 0x10);
return \"zvdepi %1,%2,%0\";
return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4337,7 +4337,7 @@
{
int x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 (x + 1));
return \"vdepi -1,%2,%0\";
return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4354,7 +4354,7 @@
{
int x = INTVAL (operands[1]);
operands[2] = GEN_INT (exact_log2 ((~x) + 1));
return \"vdepi 0,%2,%0\";
return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4380,7 +4380,7 @@
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "n")))]
""
"extrs %1,%P2,%L2,%0"
"{extrs|extrw,s} %1,%P2,%L2,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4390,7 +4390,7 @@
(minus:SI (const_int 31)
(match_operand:SI 2 "register_operand" "q"))))]
""
"vextrs %1,32,%0"
"{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4400,8 +4400,8 @@
(match_operand:SI 2 "arith32_operand" "q,n")))]
""
"@
vshd %%r0,%1,%0
extru %1,%P2,%L2,%0"
{vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
{extru|extrw,u} %1,%P2,%L2,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4415,10 +4415,10 @@
if (GET_CODE (operands[2]) == CONST_INT)
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
return \"shd %1,%1,%2,%0\";
return \"{shd|shrpw} %1,%1,%2,%0\";
}
else
return \"vshd %1,%1,%0\";
return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4448,7 +4448,7 @@
"*
{
operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
return \"shd %1,%1,%2,%0\";
return \"{shd|shrpw} %1,%1,%2,%0\";
}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4461,7 +4461,7 @@
(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 4 "const_int_operand" "n"))]))]
"INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
"shd %1,%2,%4,%0"
"{shd|shrpw} %1,%2,%4,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4473,7 +4473,7 @@
(ashift:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n"))]))]
"INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
"shd %1,%2,%4,%0"
"{shd|shrpw} %1,%2,%4,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4488,7 +4488,7 @@
int cnt = INTVAL (operands[2]) & 31;
operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
operands[2] = GEN_INT (31 - cnt);
return \"zdep %1,%2,%3,%0\";
return \"{zdep|depw,z} %1,%2,%3,%0\";
}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -4551,7 +4551,7 @@
[(unspec_volatile [(const_int 0)] 0)
(use (match_operand:SI 0 "const_int_operand" ""))]
""
"bl _mcount,%%r2\;ldo %0(%%r2),%%r25"
"{bl|b,l} _mcount,%%r2\;ldo %0(%%r2),%%r25"
[(set_attr "type" "multi")
(set_attr "length" "8")])
......@@ -4609,7 +4609,8 @@
xoperands[0] = operands[0];
xoperands[1] = gen_label_rtx ();
output_asm_insn (\"bl .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\", xoperands);
output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\",
xoperands);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
CODE_LABEL_NUMBER (xoperands[1]));
output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\\n\\tbv %%r0(%%r1)\",
......@@ -4800,7 +4801,7 @@
No need to check target flags as the length uniquely identifies
the remaining cases. */
if (get_attr_length (insn) == 8)
return \".CALL\\tARGW0=GR\;bl $$dyncall,%%r31\;copy %%r31,%%r2\";
return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
/* Long millicode call, but we are not generating PIC or portable runtime
code. */
......@@ -4814,7 +4815,7 @@
/* If we're generating PIC code. */
xoperands[0] = operands[0];
xoperands[1] = gen_label_rtx ();
output_asm_insn (\"bl .+8,%%r1\", xoperands);
output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
CODE_LABEL_NUMBER (xoperands[1]));
......@@ -4960,7 +4961,7 @@
No need to check target flags as the length uniquely identifies
the remaining cases. */
if (get_attr_length (insn) == 8)
return \".CALL\\tARGW0=GR\;bl $$dyncall,%%r31\;copy %%r31,%%r2\";
return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
/* Long millicode call, but we are not generating PIC or portable runtime
code. */
......@@ -4974,7 +4975,7 @@
/* If we're generating PIC code. */
xoperands[0] = operands[1];
xoperands[1] = gen_label_rtx ();
output_asm_insn (\"bl .+8,%%r1\", xoperands);
output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
CODE_LABEL_NUMBER (xoperands[1]));
......@@ -5129,7 +5130,7 @@
(match_operand:SI 2 "uint5_operand" "")
(match_operand:SI 3 "uint5_operand" "")))]
""
"extru %1,%3+%2-1,%2,%0"
"{extru|extrw,u} %1,%3+%2-1,%2,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -5139,7 +5140,7 @@
(const_int 1)
(match_operand:SI 3 "register_operand" "q")))]
""
"vextru %1,1,%0"
"{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -5149,7 +5150,7 @@
(match_operand:SI 2 "uint5_operand" "")
(match_operand:SI 3 "uint5_operand" "")))]
""
"extrs %1,%3+%2-1,%2,%0"
"{extrs|extrw,s} %1,%3+%2-1,%2,%0"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -5159,7 +5160,7 @@
(const_int 1)
(match_operand:SI 3 "register_operand" "q")))]
""
"vextrs %1,1,%0"
"{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -5170,8 +5171,8 @@
(match_operand:SI 3 "arith5_operand" "r,L"))]
""
"@
dep %3,%2+%1-1,%1,%0
depi %3,%2+%1-1,%1,%0"
{dep|depw} %3,%2+%1-1,%1,%0
{depi|depwi} %3,%2+%1-1,%1,%0"
[(set_attr "type" "shift,shift")
(set_attr "length" "4,4")])
......@@ -5186,7 +5187,7 @@
"*
{
operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
return \"depi %3,%2+%1-1,%1,%0\";
return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
}"
[(set_attr "type" "shift")
(set_attr "length" "4")])
......@@ -5656,7 +5657,7 @@
NULL);
}
else
output_asm_insn (\"bl,n __outline_prologue_fp,%%r31\", NULL);
output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
}
else
{
......@@ -5669,7 +5670,7 @@
output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
}
else
output_asm_insn (\"bl,n __outline_prologue,%%r31\", NULL);
output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
}
return \"\";
}"
......@@ -5711,7 +5712,7 @@
NULL);
}
else
output_asm_insn (\"bl,n __outline_epilogue_fp,%%r31\", NULL);
output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
}
else
{
......@@ -5726,7 +5727,7 @@
output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
}
else
output_asm_insn (\"bl,n __outline_epilogue,%%r31\", NULL);
output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
}
return \"\";
}"
......@@ -5777,24 +5778,28 @@
/* Next, examine the low two bits in %r26, if they aren't 0x2, then
we use %r26 unchanged. */
if (get_attr_length (insn) == 32)
output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+24\", NULL);
output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+24\", NULL);
else if (get_attr_length (insn) == 40)
output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+32\", NULL);
output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+32\", NULL);
else if (get_attr_length (insn) == 44)
output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+36\", NULL);
output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+36\", NULL);
else
output_asm_insn (\"extru %%r26,31,2,%%r31\;comib,<>,n 2,%%r31,.+20\", NULL);
output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+20\", NULL);
/* Next, compare %r26 with 4096, if %r26 is less than or equal to
4096, then we use %r26 unchanged. */
if (get_attr_length (insn) == 32)
output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+16\", NULL);
output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+16\",
NULL);
else if (get_attr_length (insn) == 40)
output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+24\", NULL);
output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+24\",
NULL);
else if (get_attr_length (insn) == 44)
output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+28\", NULL);
output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+28\",
NULL);
else
output_asm_insn (\"ldi 4096,%%r31\;comb,<<,n %%r26,%%r31,.+12\", NULL);
output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+12\",
NULL);
/* Else call $$sh_func_adrs to extract the function's real add24. */
return output_millicode_call (insn,
......
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