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riscv-gcc-1
Commit f3536097 by Shujing Zhao Committed by Paolo Carlini
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predicates.md: Use REG_P... 

2009-06-03  Shujing Zhao  <pearly.zhao@oracle.com>

	* config/sh/predicates.md: Use REG_P, MEM_P, CONST_INT_P, LABEL_P,
	JUMP_P, CALL_P, NONJUMP_INSN_P, NOTE_P, BARRIER_P and
	JUMP_TABLE_DATA_P where applicable.
	* config/sh/sh.c: Ditto.
	* config/sh/sh.h: Ditto.
	* config/sh/sh.md: Ditto.
	* config/sh/symbian.c: Ditto.

From-SVN: r148119
parent d6ced3b7
Showing with 250 additions and 252 deletions
gcc/config/sh/predicates.md
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
cond = XEXP (op, 0); cond = XEXP (op, 0);
mem = XEXP (op, 1); mem = XEXP (op, 1);
res = XEXP (op, 2); res = XEXP (op, 2);
if (GET_CODE (mem) != MEM if (!MEM_P (mem)
|| (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE)) || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
return 0; return 0;
tar = XEXP (res, 0); tar = XEXP (res, 0);
...@@ -52,8 +52,8 @@ ...@@ -52,8 +52,8 @@
and = XEXP (cond, 0); and = XEXP (cond, 0);
return (GET_CODE (and) == AND return (GET_CODE (and) == AND
&& rtx_equal_p (XEXP (and, 0), tar) && rtx_equal_p (XEXP (and, 0), tar)
&& GET_CODE (XEXP (and, 1)) == CONST_INT && CONST_INT_P (XEXP (and, 1))
&& GET_CODE (XEXP (cond, 1)) == CONST_INT && CONST_INT_P (XEXP (cond, 1))
&& INTVAL (XEXP (and, 1)) == 3 && INTVAL (XEXP (and, 1)) == 3
&& INTVAL (XEXP (cond, 1)) == 3); && INTVAL (XEXP (cond, 1)) == 3);
}) })
...@@ -108,11 +108,11 @@ ...@@ -108,11 +108,11 @@
attempting to transform a sequence of two 64-bit sets of the attempting to transform a sequence of two 64-bit sets of the
same register from literal constants into a set and an add, same register from literal constants into a set and an add,
when the difference is too wide for an add. */ when the difference is too wide for an add. */
if (GET_CODE (op) == CONST_INT if (CONST_INT_P (op)
|| satisfies_constraint_Css (op)) || satisfies_constraint_Css (op))
return 1; return 1;
else if (GET_CODE (op) == TRUNCATE else if (GET_CODE (op) == TRUNCATE
&& GET_CODE (XEXP (op, 0)) == REG && REG_P (XEXP (op, 0))
&& ! system_reg_operand (XEXP (op, 0), VOIDmode) && ! system_reg_operand (XEXP (op, 0), VOIDmode)
&& (mode == VOIDmode || mode == GET_MODE (op)) && (mode == VOIDmode || mode == GET_MODE (op))
&& (GET_MODE_SIZE (GET_MODE (op)) && (GET_MODE_SIZE (GET_MODE (op))
...@@ -152,9 +152,9 @@ ...@@ -152,9 +152,9 @@
{ {
int regno; int regno;
if (GET_CODE (op) == REG) if (REG_P (op))
regno = REGNO (op); regno = REGNO (op);
else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG) else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op)); regno = REGNO (SUBREG_REG (op));
else else
return 1; return 1;
...@@ -175,7 +175,7 @@ ...@@ -175,7 +175,7 @@
#if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */ #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */
if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
&& GET_MODE (XEXP (op, 0)) == HImode && GET_MODE (XEXP (op, 0)) == HImode
&& GET_CODE (XEXP (op, 0)) == REG && REG_P (XEXP (op, 0))
&& REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG) && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
return register_operand (XEXP (op, 0), VOIDmode); return register_operand (XEXP (op, 0), VOIDmode);
#endif #endif
...@@ -223,13 +223,13 @@ ...@@ -223,13 +223,13 @@
{ {
if (GET_CODE (op) == PLUS) if (GET_CODE (op) == PLUS)
{ {
if (GET_CODE (XEXP (op, 0)) != REG) if (!REG_P (XEXP (op, 0)))
return 0; return 0;
if (GET_CODE (XEXP (op, 1)) != CONST_INT if (!CONST_INT_P (XEXP (op, 1))
|| (INTVAL (XEXP (op, 1)) & 31)) || (INTVAL (XEXP (op, 1)) & 31))
return 0; return 0;
} }
else if (GET_CODE (op) != REG) else if (!REG_P (op))
return 0; return 0;
return address_operand (op, mode); return address_operand (op, mode);
}) })
...@@ -253,7 +253,7 @@ ...@@ -253,7 +253,7 @@
(define_predicate "cmpsi_operand" (define_predicate "cmpsi_operand"
(match_code "subreg,reg,const_int") (match_code "subreg,reg,const_int")
{ {
if (GET_CODE (op) == REG && REGNO (op) == T_REG if (REG_P (op) && REGNO (op) == T_REG
&& GET_MODE (op) == SImode && GET_MODE (op) == SImode
&& TARGET_SH1) && TARGET_SH1)
return 1; return 1;
...@@ -319,9 +319,9 @@ ...@@ -319,9 +319,9 @@
{ {
int regno; int regno;
if (GET_CODE (op) == REG) if (REG_P (op))
regno = REGNO (op); regno = REGNO (op);
else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG) else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op)); regno = REGNO (SUBREG_REG (op));
else else
return 1; return 1;
...@@ -337,7 +337,7 @@ ...@@ -337,7 +337,7 @@
(define_predicate "fpscr_operand" (define_predicate "fpscr_operand"
(match_code "reg") (match_code "reg")
{ {
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) == FPSCR_REG && (REGNO (op) == FPSCR_REG
|| (REGNO (op) >= FIRST_PSEUDO_REGISTER || (REGNO (op) >= FIRST_PSEUDO_REGISTER
&& !(reload_in_progress || reload_completed))) && !(reload_in_progress || reload_completed)))
...@@ -352,7 +352,7 @@ ...@@ -352,7 +352,7 @@
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
return fp_arith_reg_operand (op, mode); return fp_arith_reg_operand (op, mode);
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
&& GET_MODE (op) == mode); && GET_MODE (op) == mode);
}) })
...@@ -374,7 +374,7 @@ ...@@ -374,7 +374,7 @@
(define_predicate "general_movsrc_operand" (define_predicate "general_movsrc_operand"
(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector") (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
{ {
if (GET_CODE (op) == MEM) if (MEM_P (op))
{ {
rtx inside = XEXP (op, 0); rtx inside = XEXP (op, 0);
if (GET_CODE (inside) == CONST) if (GET_CODE (inside) == CONST)
...@@ -385,7 +385,7 @@ ...@@ -385,7 +385,7 @@
if (GET_CODE (inside) == PLUS if (GET_CODE (inside) == PLUS
&& GET_CODE (XEXP (inside, 0)) == LABEL_REF && GET_CODE (XEXP (inside, 0)) == LABEL_REF
&& GET_CODE (XEXP (inside, 1)) == CONST_INT) && CONST_INT_P (XEXP (inside, 1)))
return 1; return 1;
/* Only post inc allowed. */ /* Only post inc allowed. */
...@@ -411,7 +411,7 @@ ...@@ -411,7 +411,7 @@
(match_code "subreg,reg,mem") (match_code "subreg,reg,mem")
{ {
/* Only pre dec allowed. */ /* Only pre dec allowed. */
if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC) if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
return 0; return 0;
if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
...@@ -428,7 +428,7 @@ ...@@ -428,7 +428,7 @@
{ {
rtx inside; rtx inside;
if (GET_CODE (op) != MEM || GET_MODE (op) != mode) if (!MEM_P (op) || GET_MODE (op) != mode)
return 0; return 0;
inside = XEXP (op, 0); inside = XEXP (op, 0);
...@@ -436,7 +436,7 @@ ...@@ -436,7 +436,7 @@
if (GET_CODE (inside) == POST_INC) if (GET_CODE (inside) == POST_INC)
inside = XEXP (inside, 0); inside = XEXP (inside, 0);
if (GET_CODE (inside) == REG) if (REG_P (inside))
return 1; return 1;
return 0; return 0;
...@@ -457,7 +457,7 @@ ...@@ -457,7 +457,7 @@
op = XEXP (op, 0); op = XEXP (op, 0);
/* Can't use true_regnum here because copy_cost wants to know about /* Can't use true_regnum here because copy_cost wants to know about
SECONDARY_INPUT_RELOAD_CLASS. */ SECONDARY_INPUT_RELOAD_CLASS. */
return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op)); return REG_P (op) && FP_REGISTER_P (REGNO (op));
}) })
;; TODO: Add a comment here. ;; TODO: Add a comment here.
...@@ -532,7 +532,7 @@ ...@@ -532,7 +532,7 @@
{ {
HOST_WIDE_INT i; HOST_WIDE_INT i;
if (GET_CODE (op) != CONST_INT) if (!CONST_INT_P (op))
return 0; return 0;
i = INTVAL (op); i = INTVAL (op);
return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0; return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
...@@ -575,7 +575,7 @@ ...@@ -575,7 +575,7 @@
return 0; return 0;
i = XVECLEN (op, 0) - 1; i = XVECLEN (op, 0) - 1;
for (; i >= 0; i--) for (; i >= 0; i--)
if (GET_CODE (XVECEXP (op, 0, i)) != CONST_INT) if (!CONST_INT_P (XVECEXP (op, 0, i)))
return 0; return 0;
return 1; return 1;
}) })
...@@ -597,12 +597,12 @@ ...@@ -597,12 +597,12 @@
/* Determine numbers of last and of least significant elements. */ /* Determine numbers of last and of least significant elements. */
last = XVECLEN (op, 0) - 1; last = XVECLEN (op, 0) - 1;
least = TARGET_LITTLE_ENDIAN ? 0 : last; least = TARGET_LITTLE_ENDIAN ? 0 : last;
if (GET_CODE (XVECEXP (op, 0, least)) != CONST_INT) if (!CONST_INT_P (XVECEXP (op, 0, least)))
return 0; return 0;
sign_ix = least; sign_ix = least;
if (GET_MODE_UNIT_SIZE (mode) == 1) if (GET_MODE_UNIT_SIZE (mode) == 1)
sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1; sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
if (GET_CODE (XVECEXP (op, 0, sign_ix)) != CONST_INT) if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
return 0; return 0;
unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op)); unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1) sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
...@@ -660,7 +660,7 @@ ...@@ -660,7 +660,7 @@
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend") (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend")
{ {
return (CONSTANT_P (op) return (CONSTANT_P (op)
? (GET_CODE (op) == CONST_INT ? (CONST_INT_P (op)
? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode) ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
: nonmemory_operand (op, mode)) : nonmemory_operand (op, mode))
: shift_count_reg_operand (op, mode)); : shift_count_reg_operand (op, mode));
...@@ -728,7 +728,7 @@ ...@@ -728,7 +728,7 @@
if (GET_CODE (op) == SUBREG) if (GET_CODE (op) == SUBREG)
op = XEXP (op, 0); op = XEXP (op, 0);
if (GET_CODE (op) != REG) if (!REG_P (op))
return 0; return 0;
/* We must protect ourselves from matching pseudos that are virtual /* We must protect ourselves from matching pseudos that are virtual
...@@ -784,7 +784,7 @@ ...@@ -784,7 +784,7 @@
(define_predicate "xor_operand" (define_predicate "xor_operand"
(match_code "subreg,reg,const_int") (match_code "subreg,reg,const_int")
{ {
if (GET_CODE (op) == CONST_INT) if (CONST_INT_P (op))
return (TARGET_SHMEDIA return (TARGET_SHMEDIA
? (satisfies_constraint_I06 (op) ? (satisfies_constraint_I06 (op)
|| (!can_create_pseudo_p () && INTVAL (op) == 0xff)) || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
...@@ -799,13 +799,13 @@ ...@@ -799,13 +799,13 @@
(define_predicate "bitwise_memory_operand" (define_predicate "bitwise_memory_operand"
(match_code "mem") (match_code "mem")
{ {
if (GET_CODE (op) == MEM) if (MEM_P (op))
{ {
if (REG_P (XEXP (op, 0))) if (REG_P (XEXP (op, 0)))
return 1; return 1;
if (GET_CODE (XEXP (op, 0)) == PLUS if (GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == REG && REG_P (XEXP (XEXP (op, 0), 0))
&& satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))) && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))
return 1; return 1;
} }
......
gcc/config/sh/sh.c
...@@ -829,7 +829,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -829,7 +829,7 @@ print_operand (FILE *stream, rtx x, int code)
break; break;
case 't': case 't':
gcc_assert (GET_CODE (x) == MEM); gcc_assert (MEM_P (x));
x = XEXP (x, 0); x = XEXP (x, 0);
switch (GET_CODE (x)) switch (GET_CODE (x))
{ {
...@@ -862,15 +862,15 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -862,15 +862,15 @@ print_operand (FILE *stream, rtx x, int code)
case 'M': case 'M':
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
if (GET_CODE (x) == MEM if (MEM_P (x)
&& GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG && (REG_P (XEXP (XEXP (x, 0), 1))
|| GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG)) || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
fputc ('x', stream); fputc ('x', stream);
} }
else else
{ {
if (GET_CODE (x) == MEM) if (MEM_P (x))
{ {
switch (GET_MODE (x)) switch (GET_MODE (x))
{ {
...@@ -886,7 +886,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -886,7 +886,7 @@ print_operand (FILE *stream, rtx x, int code)
break; break;
case 'm': case 'm':
gcc_assert (GET_CODE (x) == MEM); gcc_assert (MEM_P (x));
x = XEXP (x, 0); x = XEXP (x, 0);
/* Fall through. */ /* Fall through. */
case 'U': case 'U':
...@@ -926,7 +926,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -926,7 +926,7 @@ print_operand (FILE *stream, rtx x, int code)
break; break;
case 'd': case 'd':
gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode); gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1); fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
break; break;
...@@ -939,7 +939,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -939,7 +939,7 @@ print_operand (FILE *stream, rtx x, int code)
} }
goto default_output; goto default_output;
case 'u': case 'u':
if (GET_CODE (x) == CONST_INT) if (CONST_INT_P (x))
{ {
fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1)); fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
break; break;
...@@ -965,7 +965,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -965,7 +965,7 @@ print_operand (FILE *stream, rtx x, int code)
== GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
&& subreg_lowpart_p (inner)) && subreg_lowpart_p (inner))
inner = SUBREG_REG (inner); inner = SUBREG_REG (inner);
if (GET_CODE (inner) == CONST_INT) if (CONST_INT_P (inner))
{ {
x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x))); x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
goto default_output; goto default_output;
...@@ -974,7 +974,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -974,7 +974,7 @@ print_operand (FILE *stream, rtx x, int code)
if (GET_CODE (inner) == SUBREG if (GET_CODE (inner) == SUBREG
&& (GET_MODE_SIZE (GET_MODE (inner)) && (GET_MODE_SIZE (GET_MODE (inner))
< GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
&& GET_CODE (SUBREG_REG (inner)) == REG) && REG_P (SUBREG_REG (inner)))
{ {
offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)), offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
GET_MODE (SUBREG_REG (inner)), GET_MODE (SUBREG_REG (inner)),
...@@ -982,7 +982,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -982,7 +982,7 @@ print_operand (FILE *stream, rtx x, int code)
GET_MODE (inner)); GET_MODE (inner));
inner = SUBREG_REG (inner); inner = SUBREG_REG (inner);
} }
if (GET_CODE (inner) != REG || GET_MODE_SIZE (inner_mode) > 8) if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
abort (); abort ();
/* Floating point register pairs are always big endian; /* Floating point register pairs are always big endian;
general purpose registers are 64 bit wide. */ general purpose registers are 64 bit wide. */
...@@ -1007,7 +1007,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -1007,7 +1007,7 @@ print_operand (FILE *stream, rtx x, int code)
goto default_output; goto default_output;
case SUBREG: case SUBREG:
gcc_assert (SUBREG_BYTE (x) == 0 gcc_assert (SUBREG_BYTE (x) == 0
&& GET_CODE (SUBREG_REG (x)) == REG); && REG_P (SUBREG_REG (x)));
x = SUBREG_REG (x); x = SUBREG_REG (x);
/* Fall through. */ /* Fall through. */
...@@ -1021,7 +1021,7 @@ print_operand (FILE *stream, rtx x, int code) ...@@ -1021,7 +1021,7 @@ print_operand (FILE *stream, rtx x, int code)
else if (FP_REGISTER_P (REGNO (x)) else if (FP_REGISTER_P (REGNO (x))
&& mode == V4SFmode) && mode == V4SFmode)
fprintf ((stream), "fv%s", reg_names[regno] + 2); fprintf ((stream), "fv%s", reg_names[regno] + 2);
else if (GET_CODE (x) == REG else if (REG_P (x)
&& mode == V2SFmode) && mode == V2SFmode)
fprintf ((stream), "fp%s", reg_names[regno] + 2); fprintf ((stream), "fp%s", reg_names[regno] + 2);
else if (FP_REGISTER_P (REGNO (x)) else if (FP_REGISTER_P (REGNO (x))
...@@ -1078,7 +1078,7 @@ int ...@@ -1078,7 +1078,7 @@ int
expand_block_move (rtx *operands) expand_block_move (rtx *operands)
{ {
int align = INTVAL (operands[3]); int align = INTVAL (operands[3]);
int constp = (GET_CODE (operands[2]) == CONST_INT); int constp = (CONST_INT_P (operands[2]));
int bytes = (constp ? INTVAL (operands[2]) : 0); int bytes = (constp ? INTVAL (operands[2]) : 0);
if (! constp) if (! constp)
...@@ -1224,7 +1224,7 @@ prepare_move_operands (rtx operands[], enum machine_mode mode) ...@@ -1224,7 +1224,7 @@ prepare_move_operands (rtx operands[], enum machine_mode mode)
rtx temp; rtx temp;
if (SYMBOLIC_CONST_P (operands[1])) if (SYMBOLIC_CONST_P (operands[1]))
{ {
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (Pmode, operands[1]); operands[1] = force_reg (Pmode, operands[1]);
else if (TARGET_SHMEDIA else if (TARGET_SHMEDIA
&& GET_CODE (operands[1]) == LABEL_REF && GET_CODE (operands[1]) == LABEL_REF
...@@ -1261,7 +1261,7 @@ prepare_move_operands (rtx operands[], enum machine_mode mode) ...@@ -1261,7 +1261,7 @@ prepare_move_operands (rtx operands[], enum machine_mode mode)
&& ! sh_register_operand (operands[1], mode)) && ! sh_register_operand (operands[1], mode))
operands[1] = copy_to_mode_reg (mode, operands[1]); operands[1] = copy_to_mode_reg (mode, operands[1]);
if (GET_CODE (operands[0]) == MEM && ! memory_operand (operands[0], mode)) if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
{ {
/* This is like change_address_1 (operands[0], mode, 0, 1) , /* This is like change_address_1 (operands[0], mode, 0, 1) ,
except that we can't use that function because it is static. */ except that we can't use that function because it is static. */
...@@ -1276,9 +1276,9 @@ prepare_move_operands (rtx operands[], enum machine_mode mode) ...@@ -1276,9 +1276,9 @@ prepare_move_operands (rtx operands[], enum machine_mode mode)
being used for the source. */ being used for the source. */
else if (TARGET_SH1 else if (TARGET_SH1
&& refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0) && refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0)
&& GET_CODE (operands[0]) == MEM && MEM_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) == PLUS && GET_CODE (XEXP (operands[0], 0)) == PLUS
&& GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG) && REG_P (XEXP (XEXP (operands[0], 0), 1)))
operands[1] = copy_to_mode_reg (mode, operands[1]); operands[1] = copy_to_mode_reg (mode, operands[1]);
} }
...@@ -1384,8 +1384,8 @@ prepare_cbranch_operands (rtx *operands, enum machine_mode mode, ...@@ -1384,8 +1384,8 @@ prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
comparison = GET_CODE (operands[0]); comparison = GET_CODE (operands[0]);
else else
scratch = operands[4]; scratch = operands[4];
if (GET_CODE (operands[1]) == CONST_INT if (CONST_INT_P (operands[1])
&& GET_CODE (operands[2]) != CONST_INT) && !CONST_INT_P (operands[2]))
{ {
rtx tmp = operands[1]; rtx tmp = operands[1];
...@@ -1393,7 +1393,7 @@ prepare_cbranch_operands (rtx *operands, enum machine_mode mode, ...@@ -1393,7 +1393,7 @@ prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
operands[2] = tmp; operands[2] = tmp;
comparison = swap_condition (comparison); comparison = swap_condition (comparison);
} }
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
{ {
HOST_WIDE_INT val = INTVAL (operands[2]); HOST_WIDE_INT val = INTVAL (operands[2]);
if ((val == -1 || val == -0x81) if ((val == -1 || val == -0x81)
...@@ -1444,7 +1444,7 @@ prepare_cbranch_operands (rtx *operands, enum machine_mode mode, ...@@ -1444,7 +1444,7 @@ prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
allocated to a different hard register, thus we load the constant into allocated to a different hard register, thus we load the constant into
a register unless it is zero. */ a register unless it is zero. */
if (!REG_P (operands[2]) if (!REG_P (operands[2])
&& (GET_CODE (operands[2]) != CONST_INT && (!CONST_INT_P (operands[2])
|| (mode == SImode && operands[2] != CONST0_RTX (SImode) || (mode == SImode && operands[2] != CONST0_RTX (SImode)
&& ((comparison != EQ && comparison != NE) && ((comparison != EQ && comparison != NE)
|| (REG_P (op1) && REGNO (op1) != R0_REG) || (REG_P (op1) && REGNO (op1) != R0_REG)
...@@ -1569,7 +1569,7 @@ expand_cbranchdi4 (rtx *operands, enum rtx_code comparison) ...@@ -1569,7 +1569,7 @@ expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
break; break;
case GTU: case GT: case GTU: case GT:
msw_taken = comparison; msw_taken = comparison;
if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1) if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
break; break;
if (comparison != GTU || op2h != CONST0_RTX (SImode)) if (comparison != GTU || op2h != CONST0_RTX (SImode))
msw_skip = swap_condition (msw_taken); msw_skip = swap_condition (msw_taken);
...@@ -1593,7 +1593,7 @@ expand_cbranchdi4 (rtx *operands, enum rtx_code comparison) ...@@ -1593,7 +1593,7 @@ expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
lsw_taken = LTU; lsw_taken = LTU;
break; break;
case LEU: case LE: case LEU: case LE:
if (GET_CODE (op2l) == CONST_INT && INTVAL (op2l) == -1) if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
msw_taken = comparison; msw_taken = comparison;
else else
{ {
...@@ -1960,7 +1960,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], ...@@ -1960,7 +1960,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
rtx dst = operands[0]; rtx dst = operands[0];
rtx src = operands[1]; rtx src = operands[1];
if (GET_CODE (dst) == MEM if (MEM_P (dst)
&& GET_CODE (XEXP (dst, 0)) == PRE_DEC) && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
return "mov.l %T1,%0\n\tmov.l %1,%0"; return "mov.l %T1,%0\n\tmov.l %1,%0";
...@@ -1978,7 +1978,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], ...@@ -1978,7 +1978,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else else
return "mov %1,%0\n\tmov %T1,%T0"; return "mov %1,%0\n\tmov %T1,%T0";
} }
else if (GET_CODE (src) == CONST_INT) else if (CONST_INT_P (src))
{ {
if (INTVAL (src) < 0) if (INTVAL (src) < 0)
output_asm_insn ("mov #-1,%S0", operands); output_asm_insn ("mov #-1,%S0", operands);
...@@ -1987,7 +1987,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], ...@@ -1987,7 +1987,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
return "mov %1,%R0"; return "mov %1,%R0";
} }
else if (GET_CODE (src) == MEM) else if (MEM_P (src))
{ {
int ptrreg = -1; int ptrreg = -1;
int dreg = REGNO (dst); int dreg = REGNO (dst);
...@@ -2012,7 +2012,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[], ...@@ -2012,7 +2012,7 @@ output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
supported, so we can't use the 'o' constraint. supported, so we can't use the 'o' constraint.
Thus we must check for and handle r0+REG addresses here. Thus we must check for and handle r0+REG addresses here.
We punt for now, since this is likely very rare. */ We punt for now, since this is likely very rare. */
gcc_assert (GET_CODE (XEXP (inside, 1)) != REG); gcc_assert (!REG_P (XEXP (inside, 1)));
break; break;
case LABEL_REF: case LABEL_REF:
...@@ -2076,7 +2076,7 @@ output_far_jump (rtx insn, rtx op) ...@@ -2076,7 +2076,7 @@ output_far_jump (rtx insn, rtx op)
jump = "mov.l %O0,%1; jmp @%1"; jump = "mov.l %O0,%1; jmp @%1";
} }
/* If we have a scratch register available, use it. */ /* If we have a scratch register available, use it. */
if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
&& INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch) && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
{ {
this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0)); this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
...@@ -2235,7 +2235,7 @@ output_branchy_insn (enum rtx_code code, const char *templ, ...@@ -2235,7 +2235,7 @@ output_branchy_insn (enum rtx_code code, const char *templ,
{ {
rtx next_insn = NEXT_INSN (insn); rtx next_insn = NEXT_INSN (insn);
if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn)) if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
{ {
rtx src = SET_SRC (PATTERN (next_insn)); rtx src = SET_SRC (PATTERN (next_insn));
if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code) if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
...@@ -2348,7 +2348,7 @@ sh_cannot_copy_insn_p (rtx insn) ...@@ -2348,7 +2348,7 @@ sh_cannot_copy_insn_p (rtx insn)
if (!reload_completed || !flag_pic) if (!reload_completed || !flag_pic)
return false; return false;
if (GET_CODE (insn) != INSN) if (!NONJUMP_INSN_P (insn))
return false; return false;
if (asm_noperands (insn) >= 0) if (asm_noperands (insn) >= 0)
return false; return false;
...@@ -2443,7 +2443,7 @@ shiftcosts (rtx x) ...@@ -2443,7 +2443,7 @@ shiftcosts (rtx x)
if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
{ {
if (GET_MODE (x) == DImode if (GET_MODE (x) == DImode
&& GET_CODE (XEXP (x, 1)) == CONST_INT && CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) == 1) && INTVAL (XEXP (x, 1)) == 1)
return 2; return 2;
...@@ -2451,7 +2451,7 @@ shiftcosts (rtx x) ...@@ -2451,7 +2451,7 @@ shiftcosts (rtx x)
return MAX_COST; return MAX_COST;
} }
/* If shift by a non constant, then this will be expensive. */ /* If shift by a non constant, then this will be expensive. */
if (GET_CODE (XEXP (x, 1)) != CONST_INT) if (!CONST_INT_P (XEXP (x, 1)))
return SH_DYNAMIC_SHIFT_COST; return SH_DYNAMIC_SHIFT_COST;
/* Otherwise, return the true cost in instructions. Cope with out of range /* Otherwise, return the true cost in instructions. Cope with out of range
...@@ -2478,7 +2478,7 @@ andcosts (rtx x) ...@@ -2478,7 +2478,7 @@ andcosts (rtx x)
int i; int i;
/* Anding with a register is a single cycle and instruction. */ /* Anding with a register is a single cycle and instruction. */
if (GET_CODE (XEXP (x, 1)) != CONST_INT) if (!CONST_INT_P (XEXP (x, 1)))
return 1; return 1;
i = INTVAL (XEXP (x, 1)); i = INTVAL (XEXP (x, 1));
...@@ -2514,12 +2514,12 @@ static inline int ...@@ -2514,12 +2514,12 @@ static inline int
addsubcosts (rtx x) addsubcosts (rtx x)
{ {
/* Adding a register is a single cycle insn. */ /* Adding a register is a single cycle insn. */
if (GET_CODE (XEXP (x, 1)) == REG if (REG_P (XEXP (x, 1))
|| GET_CODE (XEXP (x, 1)) == SUBREG) || GET_CODE (XEXP (x, 1)) == SUBREG)
return 1; return 1;
/* Likewise for small constants. */ /* Likewise for small constants. */
if (GET_CODE (XEXP (x, 1)) == CONST_INT if (CONST_INT_P (XEXP (x, 1))
&& CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1)))) && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
return 1; return 1;
...@@ -2820,7 +2820,7 @@ gen_shifty_op (int code, rtx *operands) ...@@ -2820,7 +2820,7 @@ gen_shifty_op (int code, rtx *operands)
{ {
/* There is a two instruction sequence for 31 bit left shifts, /* There is a two instruction sequence for 31 bit left shifts,
but it requires r0. */ but it requires r0. */
if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0) if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
{ {
emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx)); emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
emit_insn (gen_rotlsi3_31 (operands[0], operands[0])); emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
...@@ -2888,7 +2888,7 @@ expand_ashiftrt (rtx *operands) ...@@ -2888,7 +2888,7 @@ expand_ashiftrt (rtx *operands)
if (TARGET_SH3) if (TARGET_SH3)
{ {
if (GET_CODE (operands[2]) != CONST_INT) if (!CONST_INT_P (operands[2]))
{ {
rtx count = copy_to_mode_reg (SImode, operands[2]); rtx count = copy_to_mode_reg (SImode, operands[2]);
emit_insn (gen_negsi2 (count, count)); emit_insn (gen_negsi2 (count, count));
...@@ -2904,7 +2904,7 @@ expand_ashiftrt (rtx *operands) ...@@ -2904,7 +2904,7 @@ expand_ashiftrt (rtx *operands)
return 1; return 1;
} }
} }
if (GET_CODE (operands[2]) != CONST_INT) if (!CONST_INT_P (operands[2]))
return 0; return 0;
value = INTVAL (operands[2]) & 31; value = INTVAL (operands[2]) & 31;
...@@ -2995,7 +2995,7 @@ shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp) ...@@ -2995,7 +2995,7 @@ shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
if (left < 0 || left > 31) if (left < 0 || left > 31)
return 0; return 0;
if (GET_CODE (mask_rtx) == CONST_INT) if (CONST_INT_P (mask_rtx))
mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left; mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
else else
mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left; mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
...@@ -3732,7 +3732,7 @@ dump_table (rtx start, rtx barrier) ...@@ -3732,7 +3732,7 @@ dump_table (rtx start, rtx barrier)
scan = emit_insn_after (gen_align_4 (), scan); scan = emit_insn_after (gen_align_4 (), scan);
need_align = 0; need_align = 0;
for (; start != barrier; start = NEXT_INSN (start)) for (; start != barrier; start = NEXT_INSN (start))
if (GET_CODE (start) == INSN if (NONJUMP_INSN_P (start)
&& recog_memoized (start) == CODE_FOR_casesi_worker_2) && recog_memoized (start) == CODE_FOR_casesi_worker_2)
{ {
rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0)); rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
...@@ -3876,7 +3876,7 @@ dump_table (rtx start, rtx barrier) ...@@ -3876,7 +3876,7 @@ dump_table (rtx start, rtx barrier)
static int static int
hi_const (rtx src) hi_const (rtx src)
{ {
return (GET_CODE (src) == CONST_INT return (CONST_INT_P (src)
&& INTVAL (src) >= -32768 && INTVAL (src) >= -32768
&& INTVAL (src) <= 32767); && INTVAL (src) <= 32767);
} }
...@@ -3892,7 +3892,7 @@ hi_const (rtx src) ...@@ -3892,7 +3892,7 @@ hi_const (rtx src)
static int static int
broken_move (rtx insn) broken_move (rtx insn)
{ {
if (GET_CODE (insn) == INSN) if (NONJUMP_INSN_P (insn))
{ {
rtx pat = PATTERN (insn); rtx pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL) if (GET_CODE (pat) == PARALLEL)
...@@ -3920,7 +3920,7 @@ broken_move (rtx insn) ...@@ -3920,7 +3920,7 @@ broken_move (rtx insn)
&& (! TARGET_SH4 || TARGET_FMOVD && (! TARGET_SH4 || TARGET_FMOVD
|| (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0)) || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
== SCRATCH)) == SCRATCH))
&& GET_CODE (SET_DEST (pat)) == REG && REG_P (SET_DEST (pat))
&& FP_REGISTER_P (REGNO (SET_DEST (pat)))) && FP_REGISTER_P (REGNO (SET_DEST (pat))))
&& ! (TARGET_SH2A && ! (TARGET_SH2A
&& GET_MODE (SET_DEST (pat)) == SImode && GET_MODE (SET_DEST (pat)) == SImode
...@@ -3936,7 +3936,7 @@ broken_move (rtx insn) ...@@ -3936,7 +3936,7 @@ broken_move (rtx insn)
static int static int
mova_p (rtx insn) mova_p (rtx insn)
{ {
return (GET_CODE (insn) == INSN return (NONJUMP_INSN_P (insn)
&& GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
&& XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
...@@ -3964,9 +3964,9 @@ fixup_mova (rtx mova) ...@@ -3964,9 +3964,9 @@ fixup_mova (rtx mova)
{ {
worker = NEXT_INSN (worker); worker = NEXT_INSN (worker);
gcc_assert (worker gcc_assert (worker
&& GET_CODE (worker) != CODE_LABEL && !LABEL_P (worker)
&& GET_CODE (worker) != JUMP_INSN); && !JUMP_P (worker));
} while (GET_CODE (worker) == NOTE } while (NOTE_P (worker)
|| recog_memoized (worker) != CODE_FOR_casesi_worker_1); || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
wpat = PATTERN (worker); wpat = PATTERN (worker);
wpat0 = XVECEXP (wpat, 0, 0); wpat0 = XVECEXP (wpat, 0, 0);
...@@ -4084,12 +4084,12 @@ find_barrier (int num_mova, rtx mova, rtx from) ...@@ -4084,12 +4084,12 @@ find_barrier (int num_mova, rtx mova, rtx from)
call, determine the alignment. N.B. When find_barrier recurses for call, determine the alignment. N.B. When find_barrier recurses for
an out-of-reach mova, we might see labels at the start of previously an out-of-reach mova, we might see labels at the start of previously
inserted constant tables. */ inserted constant tables. */
if (GET_CODE (from) == CODE_LABEL if (LABEL_P (from)
&& CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg) && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
{ {
if (optimize) if (optimize)
new_align = 1 << label_to_alignment (from); new_align = 1 << label_to_alignment (from);
else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER) else if (BARRIER_P (prev_nonnote_insn (from)))
new_align = 1 << barrier_align (from); new_align = 1 << barrier_align (from);
else else
new_align = 1; new_align = 1;
...@@ -4099,7 +4099,7 @@ find_barrier (int num_mova, rtx mova, rtx from) ...@@ -4099,7 +4099,7 @@ find_barrier (int num_mova, rtx mova, rtx from)
for explicit alignments. If the table is long, we might be forced for explicit alignments. If the table is long, we might be forced
to emit the new table in front of it; the length of the alignment to emit the new table in front of it; the length of the alignment
might be the last straw. */ might be the last straw. */
else if (GET_CODE (from) == INSN else if (NONJUMP_INSN_P (from)
&& GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
&& XINT (PATTERN (from), 1) == UNSPECV_ALIGN) && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0)); new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
...@@ -4107,12 +4107,12 @@ find_barrier (int num_mova, rtx mova, rtx from) ...@@ -4107,12 +4107,12 @@ find_barrier (int num_mova, rtx mova, rtx from)
at the end. That is better than putting it in front because at the end. That is better than putting it in front because
this way, we don't need extra alignment for adding a 4-byte-aligned this way, we don't need extra alignment for adding a 4-byte-aligned
mov(a) label to a 2/4 or 8/4 byte aligned table. */ mov(a) label to a 2/4 or 8/4 byte aligned table. */
else if (GET_CODE (from) == INSN else if (NONJUMP_INSN_P (from)
&& GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
&& XINT (PATTERN (from), 1) == UNSPECV_CONST_END) && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
return from; return from;
if (GET_CODE (from) == BARRIER) if (BARRIER_P (from))
{ {
rtx next; rtx next;
...@@ -4198,9 +4198,7 @@ find_barrier (int num_mova, rtx mova, rtx from) ...@@ -4198,9 +4198,7 @@ find_barrier (int num_mova, rtx mova, rtx from)
if (found_si > count_si) if (found_si > count_si)
count_si = found_si; count_si = found_si;
} }
else if (GET_CODE (from) == JUMP_INSN else if (JUMP_TABLE_DATA_P (from))
&& (GET_CODE (PATTERN (from)) == ADDR_VEC
|| GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
{ {
if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode) if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
|| (num_mova || (num_mova
...@@ -4227,7 +4225,7 @@ find_barrier (int num_mova, rtx mova, rtx from) ...@@ -4227,7 +4225,7 @@ find_barrier (int num_mova, rtx mova, rtx from)
} }
} }
/* For the SH1, we generate alignments even after jumps-around-jumps. */ /* For the SH1, we generate alignments even after jumps-around-jumps. */
else if (GET_CODE (from) == JUMP_INSN else if (JUMP_P (from)
&& ! TARGET_SH2 && ! TARGET_SH2
&& ! TARGET_SMALLCODE) && ! TARGET_SMALLCODE)
new_align = 4; new_align = 4;
...@@ -4298,8 +4296,8 @@ find_barrier (int num_mova, rtx mova, rtx from) ...@@ -4298,8 +4296,8 @@ find_barrier (int num_mova, rtx mova, rtx from)
around the constant pool table will be hit. Putting it before around the constant pool table will be hit. Putting it before
a jump makes it more likely that the bra delay slot will be a jump makes it more likely that the bra delay slot will be
filled. */ filled. */
while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE while (NOTE_P (from) || JUMP_P (from)
|| GET_CODE (from) == CODE_LABEL) || LABEL_P (from))
from = PREV_INSN (from); from = PREV_INSN (from);
from = emit_jump_insn_after (gen_jump (label), from); from = emit_jump_insn_after (gen_jump (label), from);
...@@ -4322,7 +4320,7 @@ sfunc_uses_reg (rtx insn) ...@@ -4322,7 +4320,7 @@ sfunc_uses_reg (rtx insn)
int i; int i;
rtx pattern, part, reg_part, reg; rtx pattern, part, reg_part, reg;
if (GET_CODE (insn) != INSN) if (!NONJUMP_INSN_P (insn))
return 0; return 0;
pattern = PATTERN (insn); pattern = PATTERN (insn);
if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC) if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
...@@ -4343,7 +4341,7 @@ sfunc_uses_reg (rtx insn) ...@@ -4343,7 +4341,7 @@ sfunc_uses_reg (rtx insn)
if (part == reg_part || GET_CODE (part) == CLOBBER) if (part == reg_part || GET_CODE (part) == CLOBBER)
continue; continue;
if (reg_mentioned_p (reg, ((GET_CODE (part) == SET if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
&& GET_CODE (SET_DEST (part)) == REG) && REG_P (SET_DEST (part)))
? SET_SRC (part) : part))) ? SET_SRC (part) : part)))
return 0; return 0;
} }
...@@ -4366,18 +4364,18 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set) ...@@ -4366,18 +4364,18 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set)
{ {
pattern = single_set (insn); pattern = single_set (insn);
if (pattern if (pattern
&& GET_CODE (SET_DEST (pattern)) == REG && REG_P (SET_DEST (pattern))
&& REGNO (reg) == REGNO (SET_DEST (pattern))) && REGNO (reg) == REGNO (SET_DEST (pattern)))
*set = pattern; *set = pattern;
return 0; return 0;
} }
if (GET_CODE (insn) != CALL_INSN) if (!CALL_P (insn))
{ {
/* We don't use rtx_equal_p because we don't care if the mode is /* We don't use rtx_equal_p because we don't care if the mode is
different. */ different. */
pattern = single_set (insn); pattern = single_set (insn);
if (pattern if (pattern
&& GET_CODE (SET_DEST (pattern)) == REG && REG_P (SET_DEST (pattern))
&& REGNO (reg) == REGNO (SET_DEST (pattern))) && REGNO (reg) == REGNO (SET_DEST (pattern)))
{ {
rtx par, part; rtx par, part;
...@@ -4416,7 +4414,7 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set) ...@@ -4416,7 +4414,7 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set)
{ {
/* We don't use rtx_equal_p, because we don't care if the /* We don't use rtx_equal_p, because we don't care if the
mode is different. */ mode is different. */
if (GET_CODE (SET_DEST (pattern)) != REG if (!REG_P (SET_DEST (pattern))
|| REGNO (reg) != REGNO (SET_DEST (pattern))) || REGNO (reg) != REGNO (SET_DEST (pattern)))
return 1; return 1;
...@@ -4427,7 +4425,7 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set) ...@@ -4427,7 +4425,7 @@ noncall_uses_reg (rtx reg, rtx insn, rtx *set)
} }
if (GET_CODE (pattern) != CALL if (GET_CODE (pattern) != CALL
|| GET_CODE (XEXP (pattern, 0)) != MEM || !MEM_P (XEXP (pattern, 0))
|| ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0))) || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
return 1; return 1;
...@@ -4460,7 +4458,7 @@ regs_used (rtx x, int is_dest) ...@@ -4460,7 +4458,7 @@ regs_used (rtx x, int is_dest)
{ {
rtx y = SUBREG_REG (x); rtx y = SUBREG_REG (x);
if (GET_CODE (y) != REG) if (!REG_P (y))
break; break;
if (REGNO (y) < 16) if (REGNO (y) < 16)
return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1) return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
...@@ -4523,7 +4521,7 @@ gen_block_redirect (rtx jump, int addr, int need_block) ...@@ -4523,7 +4521,7 @@ gen_block_redirect (rtx jump, int addr, int need_block)
rtx dest; rtx dest;
/* First, check if we already have an instruction that satisfies our need. */ /* First, check if we already have an instruction that satisfies our need. */
if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev)) if (prev && NONJUMP_INSN_P (prev) && ! INSN_DELETED_P (prev))
{ {
if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch) if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
return prev; return prev;
...@@ -4620,7 +4618,7 @@ gen_block_redirect (rtx jump, int addr, int need_block) ...@@ -4620,7 +4618,7 @@ gen_block_redirect (rtx jump, int addr, int need_block)
else if (optimize && need_block >= 0) else if (optimize && need_block >= 0)
{ {
rtx next = next_active_insn (next_active_insn (dest)); rtx next = next_active_insn (next_active_insn (dest));
if (next && GET_CODE (next) == JUMP_INSN if (next && JUMP_P (next)
&& GET_CODE (PATTERN (next)) == SET && GET_CODE (PATTERN (next)) == SET
&& recog_memoized (next) == CODE_FOR_jump_compact) && recog_memoized (next) == CODE_FOR_jump_compact)
{ {
...@@ -4737,7 +4735,7 @@ fixup_addr_diff_vecs (rtx first) ...@@ -4737,7 +4735,7 @@ fixup_addr_diff_vecs (rtx first)
{ {
rtx vec_lab, pat, prev, prevpat, x, braf_label; rtx vec_lab, pat, prev, prevpat, x, braf_label;
if (GET_CODE (insn) != JUMP_INSN if (!JUMP_P (insn)
|| GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
continue; continue;
pat = PATTERN (insn); pat = PATTERN (insn);
...@@ -4746,7 +4744,7 @@ fixup_addr_diff_vecs (rtx first) ...@@ -4746,7 +4744,7 @@ fixup_addr_diff_vecs (rtx first)
/* Search the matching casesi_jump_2. */ /* Search the matching casesi_jump_2. */
for (prev = vec_lab; ; prev = PREV_INSN (prev)) for (prev = vec_lab; ; prev = PREV_INSN (prev))
{ {
if (GET_CODE (prev) != JUMP_INSN) if (!JUMP_P (prev))
continue; continue;
prevpat = PATTERN (prev); prevpat = PATTERN (prev);
if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2) if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
...@@ -4835,7 +4833,7 @@ barrier_align (rtx barrier_or_label) ...@@ -4835,7 +4833,7 @@ barrier_align (rtx barrier_or_label)
prev = prev_real_insn (prev); prev = prev_real_insn (prev);
for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2; for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
credit >= 0 && prev && GET_CODE (prev) == INSN; credit >= 0 && prev && NONJUMP_INSN_P (prev);
prev = prev_real_insn (prev)) prev = prev_real_insn (prev))
{ {
jump_to_next = 0; jump_to_next = 0;
...@@ -4859,7 +4857,7 @@ barrier_align (rtx barrier_or_label) ...@@ -4859,7 +4857,7 @@ barrier_align (rtx barrier_or_label)
credit -= get_attr_length (prev); credit -= get_attr_length (prev);
} }
if (prev if (prev
&& GET_CODE (prev) == JUMP_INSN && JUMP_P (prev)
&& JUMP_LABEL (prev)) && JUMP_LABEL (prev))
{ {
rtx x; rtx x;
...@@ -4903,7 +4901,7 @@ sh_loop_align (rtx label) ...@@ -4903,7 +4901,7 @@ sh_loop_align (rtx label)
do do
next = next_nonnote_insn (next); next = next_nonnote_insn (next);
while (next && GET_CODE (next) == CODE_LABEL); while (next && LABEL_P (next));
if (! next if (! next
|| ! INSN_P (next) || ! INSN_P (next)
...@@ -4969,7 +4967,7 @@ sh_reorg (void) ...@@ -4969,7 +4967,7 @@ sh_reorg (void)
rtx pattern, reg, link, set, scan, dies, label; rtx pattern, reg, link, set, scan, dies, label;
int rescan = 0, foundinsn = 0; int rescan = 0, foundinsn = 0;
if (GET_CODE (insn) == CALL_INSN) if (CALL_P (insn))
{ {
pattern = PATTERN (insn); pattern = PATTERN (insn);
...@@ -4979,7 +4977,7 @@ sh_reorg (void) ...@@ -4979,7 +4977,7 @@ sh_reorg (void)
pattern = SET_SRC (pattern); pattern = SET_SRC (pattern);
if (GET_CODE (pattern) != CALL if (GET_CODE (pattern) != CALL
|| GET_CODE (XEXP (pattern, 0)) != MEM) || !MEM_P (XEXP (pattern, 0)))
continue; continue;
reg = XEXP (XEXP (pattern, 0), 0); reg = XEXP (XEXP (pattern, 0), 0);
...@@ -4991,13 +4989,13 @@ sh_reorg (void) ...@@ -4991,13 +4989,13 @@ sh_reorg (void)
continue; continue;
} }
if (GET_CODE (reg) != REG) if (!REG_P (reg))
continue; continue;
/* Try scanning backward to find where the register is set. */ /* Try scanning backward to find where the register is set. */
link = NULL; link = NULL;
for (scan = PREV_INSN (insn); for (scan = PREV_INSN (insn);
scan && GET_CODE (scan) != CODE_LABEL; scan && !LABEL_P (scan);
scan = PREV_INSN (scan)) scan = PREV_INSN (scan))
{ {
if (! INSN_P (scan)) if (! INSN_P (scan))
...@@ -5049,7 +5047,7 @@ sh_reorg (void) ...@@ -5049,7 +5047,7 @@ sh_reorg (void)
the call, and can result in situations where a single call the call, and can result in situations where a single call
insn may have two targets depending on where we came from. */ insn may have two targets depending on where we came from. */
if (GET_CODE (scan) == CODE_LABEL && ! foundinsn) if (LABEL_P (scan) && ! foundinsn)
break; break;
if (! INSN_P (scan)) if (! INSN_P (scan))
...@@ -5059,7 +5057,7 @@ sh_reorg (void) ...@@ -5059,7 +5057,7 @@ sh_reorg (void)
safely, we would have to check that all the safely, we would have to check that all the
instructions at the jump destination did not use REG. */ instructions at the jump destination did not use REG. */
if (GET_CODE (scan) == JUMP_INSN) if (JUMP_P (scan))
break; break;
if (! reg_mentioned_p (reg, scan)) if (! reg_mentioned_p (reg, scan))
...@@ -5072,7 +5070,7 @@ sh_reorg (void) ...@@ -5072,7 +5070,7 @@ sh_reorg (void)
foundinsn = 1; foundinsn = 1;
if (scan != insn if (scan != insn
&& (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan))) && (CALL_P (scan) || sfunc_uses_reg (scan)))
{ {
/* There is a function call to this register other /* There is a function call to this register other
than the one we are checking. If we optimize than the one we are checking. If we optimize
...@@ -5128,7 +5126,7 @@ sh_reorg (void) ...@@ -5128,7 +5126,7 @@ sh_reorg (void)
scan = NEXT_INSN (scan); scan = NEXT_INSN (scan);
if (scan != insn if (scan != insn
&& ((GET_CODE (scan) == CALL_INSN && ((CALL_P (scan)
&& reg_mentioned_p (reg, scan)) && reg_mentioned_p (reg, scan))
|| ((reg2 = sfunc_uses_reg (scan)) || ((reg2 = sfunc_uses_reg (scan))
&& REGNO (reg2) == REGNO (reg)))) && REGNO (reg2) == REGNO (reg))))
...@@ -5168,7 +5166,7 @@ sh_reorg (void) ...@@ -5168,7 +5166,7 @@ sh_reorg (void)
num_mova = 0; num_mova = 0;
} }
} }
else if (GET_CODE (insn) == JUMP_INSN else if (JUMP_P (insn)
&& GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
&& num_mova && num_mova
/* ??? loop invariant motion can also move a mova out of a /* ??? loop invariant motion can also move a mova out of a
...@@ -5203,7 +5201,7 @@ sh_reorg (void) ...@@ -5203,7 +5201,7 @@ sh_reorg (void)
} }
} }
if (broken_move (insn) if (broken_move (insn)
|| (GET_CODE (insn) == INSN || (NONJUMP_INSN_P (insn)
&& recog_memoized (insn) == CODE_FOR_casesi_worker_2)) && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
{ {
rtx scan; rtx scan;
...@@ -5223,9 +5221,9 @@ sh_reorg (void) ...@@ -5223,9 +5221,9 @@ sh_reorg (void)
/* Now find all the moves between the points and modify them. */ /* Now find all the moves between the points and modify them. */
for (scan = insn; scan != barrier; scan = NEXT_INSN (scan)) for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
{ {
if (GET_CODE (scan) == CODE_LABEL) if (LABEL_P (scan))
last_float = 0; last_float = 0;
if (GET_CODE (scan) == INSN if (NONJUMP_INSN_P (scan)
&& recog_memoized (scan) == CODE_FOR_casesi_worker_2) && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
need_aligned_label = 1; need_aligned_label = 1;
if (broken_move (scan)) if (broken_move (scan))
...@@ -5258,7 +5256,7 @@ sh_reorg (void) ...@@ -5258,7 +5256,7 @@ sh_reorg (void)
} }
dst = gen_rtx_REG (HImode, REGNO (dst) + offset); dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
} }
if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst))) if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
{ {
/* This must be an insn that clobbers r0. */ /* This must be an insn that clobbers r0. */
rtx *clobberp = &XVECEXP (PATTERN (scan), 0, rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
...@@ -5387,7 +5385,7 @@ get_dest_uid (rtx label, int max_uid) ...@@ -5387,7 +5385,7 @@ get_dest_uid (rtx label, int max_uid)
dest = NEXT_INSN (dest); dest = NEXT_INSN (dest);
dest_uid = INSN_UID (dest); dest_uid = INSN_UID (dest);
} }
if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN) if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
return 0; return 0;
return dest_uid; return dest_uid;
} }
...@@ -5421,7 +5419,7 @@ split_branches (rtx first) ...@@ -5421,7 +5419,7 @@ split_branches (rtx first)
so transform it into a note. */ so transform it into a note. */
SET_INSN_DELETED (insn); SET_INSN_DELETED (insn);
} }
else if (GET_CODE (insn) == JUMP_INSN else if (JUMP_P (insn)
/* Don't mess with ADDR_DIFF_VEC */ /* Don't mess with ADDR_DIFF_VEC */
&& (GET_CODE (PATTERN (insn)) == SET && (GET_CODE (PATTERN (insn)) == SET
|| GET_CODE (PATTERN (insn)) == RETURN)) || GET_CODE (PATTERN (insn)) == RETURN))
...@@ -5509,9 +5507,9 @@ split_branches (rtx first) ...@@ -5509,9 +5507,9 @@ split_branches (rtx first)
0)); 0));
if (beyond if (beyond
&& (GET_CODE (beyond) == JUMP_INSN && (JUMP_P (beyond)
|| ((beyond = next_active_insn (beyond)) || ((beyond = next_active_insn (beyond))
&& GET_CODE (beyond) == JUMP_INSN)) && JUMP_P (beyond)))
&& GET_CODE (PATTERN (beyond)) == SET && GET_CODE (PATTERN (beyond)) == SET
&& recog_memoized (beyond) == CODE_FOR_jump_compact && recog_memoized (beyond) == CODE_FOR_jump_compact
&& ((INSN_ADDRESSES && ((INSN_ADDRESSES
...@@ -5524,9 +5522,9 @@ split_branches (rtx first) ...@@ -5524,9 +5522,9 @@ split_branches (rtx first)
next = next_active_insn (insn); next = next_active_insn (insn);
if ((GET_CODE (next) == JUMP_INSN if ((JUMP_P (next)
|| ((next = next_active_insn (next)) || ((next = next_active_insn (next))
&& GET_CODE (next) == JUMP_INSN)) && JUMP_P (next)))
&& GET_CODE (PATTERN (next)) == SET && GET_CODE (PATTERN (next)) == SET
&& recog_memoized (next) == CODE_FOR_jump_compact && recog_memoized (next) == CODE_FOR_jump_compact
&& ((INSN_ADDRESSES && ((INSN_ADDRESSES
...@@ -6090,7 +6088,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) ...@@ -6090,7 +6088,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
{ {
rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG); rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
pr_live = (pr_initial pr_live = (pr_initial
? (GET_CODE (pr_initial) != REG ? (!REG_P (pr_initial)
|| REGNO (pr_initial) != (PR_REG)) || REGNO (pr_initial) != (PR_REG))
: df_regs_ever_live_p (PR_REG)); : df_regs_ever_live_p (PR_REG));
/* For Shcompact, if not optimizing, we end up with a memory reference /* For Shcompact, if not optimizing, we end up with a memory reference
...@@ -8657,7 +8655,7 @@ reg_unused_after (rtx reg, rtx insn) ...@@ -8657,7 +8655,7 @@ reg_unused_after (rtx reg, rtx insn)
case. Disregard the case where this is a store to memory, since case. Disregard the case where this is a store to memory, since
we are checking a register used in the store address. */ we are checking a register used in the store address. */
set = single_set (insn); set = single_set (insn);
if (set && GET_CODE (SET_DEST (set)) != MEM if (set && !MEM_P (SET_DEST (set))
&& reg_overlap_mentioned_p (reg, SET_DEST (set))) && reg_overlap_mentioned_p (reg, SET_DEST (set)))
return 1; return 1;
...@@ -8696,9 +8694,9 @@ reg_unused_after (rtx reg, rtx insn) ...@@ -8696,9 +8694,9 @@ reg_unused_after (rtx reg, rtx insn)
rtx this_insn = XVECEXP (PATTERN (insn), 0, i); rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
rtx set = single_set (this_insn); rtx set = single_set (this_insn);
if (GET_CODE (this_insn) == CALL_INSN) if (CALL_P (this_insn))
code = CALL_INSN; code = CALL_INSN;
else if (GET_CODE (this_insn) == JUMP_INSN) else if (JUMP_P (this_insn))
{ {
if (INSN_ANNULLED_BRANCH_P (this_insn)) if (INSN_ANNULLED_BRANCH_P (this_insn))
return 0; return 0;
...@@ -8709,7 +8707,7 @@ reg_unused_after (rtx reg, rtx insn) ...@@ -8709,7 +8707,7 @@ reg_unused_after (rtx reg, rtx insn)
return 0; return 0;
if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
{ {
if (GET_CODE (SET_DEST (set)) != MEM) if (!MEM_P (SET_DEST (set)))
retval = 1; retval = 1;
else else
return 0; return 0;
...@@ -8728,7 +8726,7 @@ reg_unused_after (rtx reg, rtx insn) ...@@ -8728,7 +8726,7 @@ reg_unused_after (rtx reg, rtx insn)
if (set && reg_overlap_mentioned_p (reg, SET_SRC (set))) if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
return 0; return 0;
if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
return GET_CODE (SET_DEST (set)) != MEM; return !MEM_P (SET_DEST (set));
if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
return 0; return 0;
...@@ -8883,11 +8881,11 @@ sh_insn_length_adjustment (rtx insn) ...@@ -8883,11 +8881,11 @@ sh_insn_length_adjustment (rtx insn)
{ {
/* Instructions with unfilled delay slots take up an extra two bytes for /* Instructions with unfilled delay slots take up an extra two bytes for
the nop in the delay slot. */ the nop in the delay slot. */
if (((GET_CODE (insn) == INSN if (((NONJUMP_INSN_P (insn)
&& GET_CODE (PATTERN (insn)) != USE && GET_CODE (PATTERN (insn)) != USE
&& GET_CODE (PATTERN (insn)) != CLOBBER) && GET_CODE (PATTERN (insn)) != CLOBBER)
|| GET_CODE (insn) == CALL_INSN || CALL_P (insn)
|| (GET_CODE (insn) == JUMP_INSN || (JUMP_P (insn)
&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
&& GET_CODE (PATTERN (insn)) != ADDR_VEC)) && GET_CODE (PATTERN (insn)) != ADDR_VEC))
&& GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
...@@ -8897,7 +8895,7 @@ sh_insn_length_adjustment (rtx insn) ...@@ -8897,7 +8895,7 @@ sh_insn_length_adjustment (rtx insn)
/* SH2e has a bug that prevents the use of annulled branches, so if /* SH2e has a bug that prevents the use of annulled branches, so if
the delay slot is not filled, we'll have to put a NOP in it. */ the delay slot is not filled, we'll have to put a NOP in it. */
if (sh_cpu_attr == CPU_SH2E if (sh_cpu_attr == CPU_SH2E
&& GET_CODE (insn) == JUMP_INSN && JUMP_P (insn)
&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
&& GET_CODE (PATTERN (insn)) != ADDR_VEC && GET_CODE (PATTERN (insn)) != ADDR_VEC
&& get_attr_type (insn) == TYPE_CBRANCH && get_attr_type (insn) == TYPE_CBRANCH
...@@ -8906,7 +8904,7 @@ sh_insn_length_adjustment (rtx insn) ...@@ -8906,7 +8904,7 @@ sh_insn_length_adjustment (rtx insn)
/* sh-dsp parallel processing insn take four bytes instead of two. */ /* sh-dsp parallel processing insn take four bytes instead of two. */
if (GET_CODE (insn) == INSN) if (NONJUMP_INSN_P (insn))
{ {
int sum = 0; int sum = 0;
rtx body = PATTERN (insn); rtx body = PATTERN (insn);
...@@ -8978,7 +8976,7 @@ sh_insn_length_adjustment (rtx insn) ...@@ -8978,7 +8976,7 @@ sh_insn_length_adjustment (rtx insn)
bool bool
sh_legitimate_index_p (enum machine_mode mode, rtx op) sh_legitimate_index_p (enum machine_mode mode, rtx op)
{ {
if (GET_CODE (op) == CONST_INT) if (CONST_INT_P (op))
{ {
if (TARGET_SHMEDIA) if (TARGET_SHMEDIA)
{ {
...@@ -9171,7 +9169,7 @@ sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode) ...@@ -9171,7 +9169,7 @@ sh_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
if (GET_CODE (x) == PLUS if (GET_CODE (x) == PLUS
&& (GET_MODE_SIZE (mode) == 4 && (GET_MODE_SIZE (mode) == 4
|| GET_MODE_SIZE (mode) == 8) || GET_MODE_SIZE (mode) == 8)
&& GET_CODE (XEXP (x, 1)) == CONST_INT && CONST_INT_P (XEXP (x, 1))
&& BASE_REGISTER_RTX_P (XEXP (x, 0)) && BASE_REGISTER_RTX_P (XEXP (x, 0))
&& ! TARGET_SHMEDIA && ! TARGET_SHMEDIA
&& ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
...@@ -9233,7 +9231,7 @@ mark_constant_pool_use (rtx x) ...@@ -9233,7 +9231,7 @@ mark_constant_pool_use (rtx x)
lab = x; lab = x;
for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn)) for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
{ {
if (GET_CODE (insn) != CODE_LABEL if (!LABEL_P (insn)
|| LABEL_REFS (insn) != NEXT_INSN (insn)) || LABEL_REFS (insn) != NEXT_INSN (insn))
break; break;
lab = insn; lab = insn;
...@@ -9245,7 +9243,7 @@ mark_constant_pool_use (rtx x) ...@@ -9245,7 +9243,7 @@ mark_constant_pool_use (rtx x)
/* Mark constants in a window. */ /* Mark constants in a window. */
for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn)) for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
{ {
if (GET_CODE (insn) != INSN) if (!NONJUMP_INSN_P (insn))
continue; continue;
pattern = PATTERN (insn); pattern = PATTERN (insn);
...@@ -9419,7 +9417,7 @@ sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost) ...@@ -9419,7 +9417,7 @@ sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
} }
/* The only input for a call that is timing-critical is the /* The only input for a call that is timing-critical is the
function's address. */ function's address. */
if (GET_CODE (insn) == CALL_INSN) if (CALL_P (insn))
{ {
rtx call = PATTERN (insn); rtx call = PATTERN (insn);
...@@ -9427,7 +9425,7 @@ sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost) ...@@ -9427,7 +9425,7 @@ sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
call = XVECEXP (call, 0 ,0); call = XVECEXP (call, 0 ,0);
if (GET_CODE (call) == SET) if (GET_CODE (call) == SET)
call = SET_SRC (call); call = SET_SRC (call);
if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM if (GET_CODE (call) == CALL && MEM_P (XEXP (call, 0))
/* sibcalli_thunk uses a symbol_ref in an unspec. */ /* sibcalli_thunk uses a symbol_ref in an unspec. */
&& (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
|| ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))) || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
...@@ -9605,7 +9603,7 @@ find_set_regmode_weight (rtx x, enum machine_mode mode) ...@@ -9605,7 +9603,7 @@ find_set_regmode_weight (rtx x, enum machine_mode mode)
return 1; return 1;
if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode)) if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
{ {
if (GET_CODE (SET_DEST (x)) == REG) if (REG_P (SET_DEST (x)))
{ {
if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x))) if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
return 1; return 1;
...@@ -9642,7 +9640,7 @@ find_insn_regmode_weight (rtx insn, enum machine_mode mode) ...@@ -9642,7 +9640,7 @@ find_insn_regmode_weight (rtx insn, enum machine_mode mode)
if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED) if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
{ {
rtx note = XEXP (x, 0); rtx note = XEXP (x, 0);
if (GET_CODE (note) == REG && GET_MODE (note) == mode) if (REG_P (note) && GET_MODE (note) == mode)
reg_weight--; reg_weight--;
} }
} }
...@@ -10684,7 +10682,7 @@ sh_mark_label (rtx address, int nuses) ...@@ -10684,7 +10682,7 @@ sh_mark_label (rtx address, int nuses)
address = XVECEXP (address, 0, 0); address = XVECEXP (address, 0, 0);
} }
if (GET_CODE (address) == LABEL_REF if (GET_CODE (address) == LABEL_REF
&& GET_CODE (XEXP (address, 0)) == CODE_LABEL) && LABEL_P (XEXP (address, 0)))
LABEL_NUSES (XEXP (address, 0)) += nuses; LABEL_NUSES (XEXP (address, 0)) += nuses;
} }
...@@ -11074,10 +11072,10 @@ sh_expand_t_scc (rtx operands[]) ...@@ -11074,10 +11072,10 @@ sh_expand_t_scc (rtx operands[])
rtx result = target; rtx result = target;
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE (op0) != REG || REGNO (op0) != T_REG if (!REG_P (op0) || REGNO (op0) != T_REG
|| GET_CODE (op1) != CONST_INT) || !CONST_INT_P (op1))
return 0; return 0;
if (GET_CODE (result) != REG) if (!REG_P (result))
result = gen_reg_rtx (SImode); result = gen_reg_rtx (SImode);
val = INTVAL (op1); val = INTVAL (op1);
if ((code == EQ && val == 1) || (code == NE && val == 0)) if ((code == EQ && val == 1) || (code == NE && val == 0))
...@@ -11131,7 +11129,7 @@ check_use_sfunc_addr (rtx insn, rtx reg) ...@@ -11131,7 +11129,7 @@ check_use_sfunc_addr (rtx insn, rtx reg)
/* Search for the sfunc. It should really come right after INSN. */ /* Search for the sfunc. It should really come right after INSN. */
while ((insn = NEXT_INSN (insn))) while ((insn = NEXT_INSN (insn)))
{ {
if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN) if (LABEL_P (insn) || JUMP_P (insn))
break; break;
if (! INSN_P (insn)) if (! INSN_P (insn))
continue; continue;
...@@ -11319,7 +11317,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify) ...@@ -11319,7 +11317,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements, rtx new_rtx = replace_n_hard_rtx (SUBREG_REG (x), replacements,
n_replacements, modify); n_replacements, modify);
if (GET_CODE (new_rtx) == CONST_INT) if (CONST_INT_P (new_rtx))
{ {
x = simplify_subreg (GET_MODE (x), new_rtx, x = simplify_subreg (GET_MODE (x), new_rtx,
GET_MODE (SUBREG_REG (x)), GET_MODE (SUBREG_REG (x)),
...@@ -11332,7 +11330,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify) ...@@ -11332,7 +11330,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
return x; return x;
} }
else if (GET_CODE (x) == REG) else if (REG_P (x))
{ {
unsigned regno = REGNO (x); unsigned regno = REGNO (x);
unsigned nregs = (regno < FIRST_PSEUDO_REGISTER unsigned nregs = (regno < FIRST_PSEUDO_REGISTER
...@@ -11345,7 +11343,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify) ...@@ -11345,7 +11343,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
rtx to = replacements[i*2+1]; rtx to = replacements[i*2+1];
unsigned from_regno, from_nregs, to_regno, new_regno; unsigned from_regno, from_nregs, to_regno, new_regno;
if (GET_CODE (from) != REG) if (!REG_P (from))
continue; continue;
from_regno = REGNO (from); from_regno = REGNO (from);
from_nregs = (from_regno < FIRST_PSEUDO_REGISTER from_nregs = (from_regno < FIRST_PSEUDO_REGISTER
...@@ -11354,7 +11352,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify) ...@@ -11354,7 +11352,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
{ {
if (regno < from_regno if (regno < from_regno
|| regno + nregs > from_regno + nregs || regno + nregs > from_regno + nregs
|| GET_CODE (to) != REG || !REG_P (to)
|| result) || result)
return NULL_RTX; return NULL_RTX;
to_regno = REGNO (to); to_regno = REGNO (to);
...@@ -11379,7 +11377,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify) ...@@ -11379,7 +11377,7 @@ replace_n_hard_rtx (rtx x, rtx *replacements, int n_replacements, int modify)
rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements, rtx new_rtx = replace_n_hard_rtx (XEXP (x, 0), replacements,
n_replacements, modify); n_replacements, modify);
if (GET_CODE (new_rtx) == CONST_INT) if (CONST_INT_P (new_rtx))
{ {
x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
new_rtx, GET_MODE (XEXP (x, 0))); new_rtx, GET_MODE (XEXP (x, 0)));
...@@ -11455,7 +11453,7 @@ shmedia_cleanup_truncate (rtx *p, void *n_changes) ...@@ -11455,7 +11453,7 @@ shmedia_cleanup_truncate (rtx *p, void *n_changes)
if (GET_CODE (x) != TRUNCATE) if (GET_CODE (x) != TRUNCATE)
return 0; return 0;
reg = XEXP (x, 0); reg = XEXP (x, 0);
if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && GET_CODE (reg) == REG) if (GET_MODE_SIZE (GET_MODE (reg)) > 8 && REG_P (reg))
{ {
enum machine_mode reg_mode = GET_MODE (reg); enum machine_mode reg_mode = GET_MODE (reg);
XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode, XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode,
...@@ -11475,7 +11473,7 @@ shmedia_cleanup_truncate (rtx *p, void *n_changes) ...@@ -11475,7 +11473,7 @@ shmedia_cleanup_truncate (rtx *p, void *n_changes)
static int static int
sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) sh_contains_memref_p_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
{ {
return (GET_CODE (*loc) == MEM); return (MEM_P (*loc));
} }
/* Return nonzero iff INSN contains a MEM. */ /* Return nonzero iff INSN contains a MEM. */
...@@ -11574,7 +11572,7 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass, ...@@ -11574,7 +11572,7 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
abort (); abort ();
} }
if (rclass == FPUL_REGS if (rclass == FPUL_REGS
&& ((GET_CODE (x) == REG && ((REG_P (x)
&& (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
|| REGNO (x) == T_REG)) || REGNO (x) == T_REG))
|| GET_CODE (x) == PLUS)) || GET_CODE (x) == PLUS))
...@@ -11589,8 +11587,8 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass, ...@@ -11589,8 +11587,8 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
return NO_REGS; return NO_REGS;
} }
if (rclass == FPSCR_REGS if (rclass == FPSCR_REGS
&& ((GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER) && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
|| (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PLUS))) || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
return GENERAL_REGS; return GENERAL_REGS;
if (REGCLASS_HAS_FP_REG (rclass) if (REGCLASS_HAS_FP_REG (rclass)
&& TARGET_SHMEDIA && TARGET_SHMEDIA
...@@ -11611,12 +11609,12 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass, ...@@ -11611,12 +11609,12 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
} /* end of input-only processing. */ } /* end of input-only processing. */
if (((REGCLASS_HAS_FP_REG (rclass) if (((REGCLASS_HAS_FP_REG (rclass)
&& (GET_CODE (x) == REG && (REG_P (x)
&& (GENERAL_OR_AP_REGISTER_P (REGNO (x)) && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
|| (FP_REGISTER_P (REGNO (x)) && mode == SImode || (FP_REGISTER_P (REGNO (x)) && mode == SImode
&& TARGET_FMOVD)))) && TARGET_FMOVD))))
|| (REGCLASS_HAS_GENERAL_REG (rclass) || (REGCLASS_HAS_GENERAL_REG (rclass)
&& GET_CODE (x) == REG && REG_P (x)
&& FP_REGISTER_P (REGNO (x)))) && FP_REGISTER_P (REGNO (x))))
&& ! TARGET_SHMEDIA && ! TARGET_SHMEDIA
&& (mode == SFmode || mode == SImode)) && (mode == SFmode || mode == SImode))
...@@ -11624,8 +11622,8 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass, ...@@ -11624,8 +11622,8 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
if ((rclass == FPUL_REGS if ((rclass == FPUL_REGS
|| (REGCLASS_HAS_FP_REG (rclass) || (REGCLASS_HAS_FP_REG (rclass)
&& ! TARGET_SHMEDIA && mode == SImode)) && ! TARGET_SHMEDIA && mode == SImode))
&& (GET_CODE (x) == MEM && (MEM_P (x)
|| (GET_CODE (x) == REG || (REG_P (x)
&& (REGNO (x) >= FIRST_PSEUDO_REGISTER && (REGNO (x) >= FIRST_PSEUDO_REGISTER
|| REGNO (x) == T_REG || REGNO (x) == T_REG
|| system_reg_operand (x, VOIDmode))))) || system_reg_operand (x, VOIDmode)))))
...@@ -11637,13 +11635,13 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass, ...@@ -11637,13 +11635,13 @@ sh_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
if ((rclass == TARGET_REGS if ((rclass == TARGET_REGS
|| (TARGET_SHMEDIA && rclass == SIBCALL_REGS)) || (TARGET_SHMEDIA && rclass == SIBCALL_REGS))
&& !satisfies_constraint_Csy (x) && !satisfies_constraint_Csy (x)
&& (GET_CODE (x) != REG || ! GENERAL_REGISTER_P (REGNO (x)))) && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
return GENERAL_REGS; return GENERAL_REGS;
if ((rclass == MAC_REGS || rclass == PR_REGS) if ((rclass == MAC_REGS || rclass == PR_REGS)
&& GET_CODE (x) == REG && ! GENERAL_REGISTER_P (REGNO (x)) && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
&& rclass != REGNO_REG_CLASS (REGNO (x))) && rclass != REGNO_REG_CLASS (REGNO (x)))
return GENERAL_REGS; return GENERAL_REGS;
if (rclass != GENERAL_REGS && GET_CODE (x) == REG if (rclass != GENERAL_REGS && REG_P (x)
&& TARGET_REGISTER_P (REGNO (x))) && TARGET_REGISTER_P (REGNO (x)))
return GENERAL_REGS; return GENERAL_REGS;
return NO_REGS; return NO_REGS;
......
gcc/config/sh/sh.h
...@@ -888,7 +888,7 @@ do { \ ...@@ -888,7 +888,7 @@ do { \
#define LABEL_ALIGN(A_LABEL) \ #define LABEL_ALIGN(A_LABEL) \
( \ ( \
(PREV_INSN (A_LABEL) \ (PREV_INSN (A_LABEL) \
&& GET_CODE (PREV_INSN (A_LABEL)) == INSN \ && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
&& GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
&& XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
/* explicit alignment insn in constant tables. */ \ /* explicit alignment insn in constant tables. */ \
...@@ -900,9 +900,9 @@ do { \ ...@@ -900,9 +900,9 @@ do { \
/* The base two logarithm of the known minimum alignment of an insn length. */ /* The base two logarithm of the known minimum alignment of an insn length. */
#define INSN_LENGTH_ALIGNMENT(A_INSN) \ #define INSN_LENGTH_ALIGNMENT(A_INSN) \
(GET_CODE (A_INSN) == INSN \ (NONJUMP_INSN_P (A_INSN) \
? 1 << TARGET_SHMEDIA \ ? 1 << TARGET_SHMEDIA \
: GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \ : JUMP_P (A_INSN) || CALL_P (A_INSN) \
? 1 << TARGET_SHMEDIA \ ? 1 << TARGET_SHMEDIA \
: CACHE_LOG) : CACHE_LOG)
...@@ -1547,12 +1547,12 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1547,12 +1547,12 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#if 0 #if 0
#define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \ #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
((((REGCLASS_HAS_FP_REG (CLASS) \ ((((REGCLASS_HAS_FP_REG (CLASS) \
&& (GET_CODE (X) == REG \ && (REG_P (X) \
&& (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
|| (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \ || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
&& TARGET_FMOVD)))) \ && TARGET_FMOVD)))) \
|| (REGCLASS_HAS_GENERAL_REG (CLASS) \ || (REGCLASS_HAS_GENERAL_REG (CLASS) \
&& GET_CODE (X) == REG \ && REG_P (X) \
&& FP_REGISTER_P (REGNO (X)))) \ && FP_REGISTER_P (REGNO (X)))) \
&& ! TARGET_SHMEDIA \ && ! TARGET_SHMEDIA \
&& ((MODE) == SFmode || (MODE) == SImode)) \ && ((MODE) == SFmode || (MODE) == SImode)) \
...@@ -1560,8 +1560,8 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1560,8 +1560,8 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
: (((CLASS) == FPUL_REGS \ : (((CLASS) == FPUL_REGS \
|| (REGCLASS_HAS_FP_REG (CLASS) \ || (REGCLASS_HAS_FP_REG (CLASS) \
&& ! TARGET_SHMEDIA && MODE == SImode)) \ && ! TARGET_SHMEDIA && MODE == SImode)) \
&& (GET_CODE (X) == MEM \ && (MEM_P (X) \
|| (GET_CODE (X) == REG \ || (REG_P (X) \
&& (REGNO (X) >= FIRST_PSEUDO_REGISTER \ && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| REGNO (X) == T_REG \ || REGNO (X) == T_REG \
|| system_reg_operand (X, VOIDmode))))) \ || system_reg_operand (X, VOIDmode))))) \
...@@ -1569,13 +1569,13 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1569,13 +1569,13 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
: (((CLASS) == TARGET_REGS \ : (((CLASS) == TARGET_REGS \
|| (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \ || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
&& !satisfies_constraint_Csy (X) \ && !satisfies_constraint_Csy (X) \
&& (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \ && (!REG_P (X) || ! GENERAL_REGISTER_P (REGNO (X)))) \
? GENERAL_REGS \ ? GENERAL_REGS \
: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \ : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
&& GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \ && REG_P (X) && ! GENERAL_REGISTER_P (REGNO (X)) \
&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \ && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
? GENERAL_REGS \ ? GENERAL_REGS \
: ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \ : ((CLASS) != GENERAL_REGS && REG_P (X) \
&& TARGET_REGISTER_P (REGNO (X))) \ && TARGET_REGISTER_P (REGNO (X))) \
? GENERAL_REGS : (ELSE)) ? GENERAL_REGS : (ELSE))
...@@ -1590,7 +1590,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1590,7 +1590,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
&& (MODE) == SFmode && fldi_ok ())) \ && (MODE) == SFmode && fldi_ok ())) \
? R0_REGS \ ? R0_REGS \
: ((CLASS) == FPUL_REGS \ : ((CLASS) == FPUL_REGS \
&& ((GET_CODE (X) == REG \ && ((REG_P (X) \
&& (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \ && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
|| REGNO (X) == T_REG)) \ || REGNO (X) == T_REG)) \
|| GET_CODE (X) == PLUS)) \ || GET_CODE (X) == PLUS)) \
...@@ -1600,8 +1600,8 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; ...@@ -1600,8 +1600,8 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
? GENERAL_REGS \ ? GENERAL_REGS \
: R0_REGS) \ : R0_REGS) \
: ((CLASS) == FPSCR_REGS \ : ((CLASS) == FPSCR_REGS \
&& ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ && ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\ || (MEM_P (X) && GET_CODE (XEXP ((X), 0)) == PLUS))) \
? GENERAL_REGS \ ? GENERAL_REGS \
: (REGCLASS_HAS_FP_REG (CLASS) \ : (REGCLASS_HAS_FP_REG (CLASS) \
&& TARGET_SHMEDIA \ && TARGET_SHMEDIA \
...@@ -2218,11 +2218,11 @@ struct sh_args { ...@@ -2218,11 +2218,11 @@ struct sh_args {
|| (GET_CODE ((OP)) == CONST \ || (GET_CODE ((OP)) == CONST \
&& GET_CODE (XEXP ((OP), 0)) == PLUS \ && GET_CODE (XEXP ((OP), 0)) == PLUS \
&& GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
&& GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)) && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
#define IS_NON_EXPLICIT_CONSTANT_P(OP) \ #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
(CONSTANT_P (OP) \ (CONSTANT_P (OP) \
&& GET_CODE (OP) != CONST_INT \ && !CONST_INT_P (OP) \
&& GET_CODE (OP) != CONST_DOUBLE \ && GET_CODE (OP) != CONST_DOUBLE \
&& (!flag_pic \ && (!flag_pic \
|| (LEGITIMATE_PIC_OPERAND_P (OP) \ || (LEGITIMATE_PIC_OPERAND_P (OP) \
...@@ -2252,7 +2252,7 @@ struct sh_args { ...@@ -2252,7 +2252,7 @@ struct sh_args {
&& (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
|| (GET_CODE (XEXP ((OP), 0)) == PLUS \ || (GET_CODE (XEXP ((OP), 0)) == PLUS \
&& UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
&& GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
#define PIC_ADDR_P(OP) \ #define PIC_ADDR_P(OP) \
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
...@@ -2273,7 +2273,7 @@ struct sh_args { ...@@ -2273,7 +2273,7 @@ struct sh_args {
&& (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
|| GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
|| DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \ || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
&& GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)) && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
#define PIC_REFERENCE_P(OP) \ #define PIC_REFERENCE_P(OP) \
(GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
...@@ -2286,22 +2286,22 @@ struct sh_args { ...@@ -2286,22 +2286,22 @@ struct sh_args {
: NON_PIC_REFERENCE_P (OP)) : NON_PIC_REFERENCE_P (OP))
#define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X, STRICT)) \ ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
|| (GET_CODE (X) == SUBREG \ || (GET_CODE (X) == SUBREG \
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
&& GET_CODE (SUBREG_REG (X)) == REG \ && REG_P (SUBREG_REG (X)) \
&& REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT))) && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
/* Since this must be r0, which is a single register class, we must check /* Since this must be r0, which is a single register class, we must check
SUBREGs more carefully, to be sure that we don't accept one that extends SUBREGs more carefully, to be sure that we don't accept one that extends
outside the class. */ outside the class. */
#define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \ #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X, STRICT)) \ ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
|| (GET_CODE (X) == SUBREG \ || (GET_CODE (X) == SUBREG \
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \ && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \ GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
&& GET_CODE (SUBREG_REG (X)) == REG \ && REG_P (SUBREG_REG (X)) \
&& SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT))) && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
#ifdef REG_OK_STRICT #ifdef REG_OK_STRICT
...@@ -2332,7 +2332,7 @@ struct sh_args { ...@@ -2332,7 +2332,7 @@ struct sh_args {
{ \ { \
if (GET_CODE (X) == PLUS \ if (GET_CODE (X) == PLUS \
&& (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \ && CONST_INT_P (XEXP (X, 1)) \
&& BASE_REGISTER_RTX_P (XEXP (X, 0)) \ && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
&& ! TARGET_SHMEDIA \ && ! TARGET_SHMEDIA \
&& ! (TARGET_SH4 && (MODE) == DFmode) \ && ! (TARGET_SH4 && (MODE) == DFmode) \
...@@ -2387,9 +2387,9 @@ struct sh_args { ...@@ -2387,9 +2387,9 @@ struct sh_args {
else if (GET_CODE (X) == PLUS \ else if (GET_CODE (X) == PLUS \
&& (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \ && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
&& GET_CODE (XEXP (X, 0)) == PLUS \ && GET_CODE (XEXP (X, 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
&& BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \ && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \ && CONST_INT_P (XEXP (X, 1)) \
&& ! TARGET_SHMEDIA \ && ! TARGET_SHMEDIA \
&& ! (TARGET_SH2E && MODE == SFmode)) \ && ! (TARGET_SH2E && MODE == SFmode)) \
{ \ { \
...@@ -2521,14 +2521,14 @@ struct sh_args { ...@@ -2521,14 +2521,14 @@ struct sh_args {
in particular. */ in particular. */
#define INSN_SETS_ARE_DELAYED(X) \ #define INSN_SETS_ARE_DELAYED(X) \
((GET_CODE (X) == INSN \ ((NONJUMP_INSN_P (X) \
&& GET_CODE (PATTERN (X)) != SEQUENCE \ && GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \ && GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \ && GET_CODE (PATTERN (X)) != CLOBBER \
&& get_attr_is_sfunc (X))) && get_attr_is_sfunc (X)))
#define INSN_REFERENCES_ARE_DELAYED(X) \ #define INSN_REFERENCES_ARE_DELAYED(X) \
((GET_CODE (X) == INSN \ ((NONJUMP_INSN_P (X) \
&& GET_CODE (PATTERN (X)) != SEQUENCE \ && GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \ && GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \ && GET_CODE (PATTERN (X)) != CLOBBER \
......
gcc/config/sh/sh.md
...@@ -1044,7 +1044,7 @@ ...@@ -1044,7 +1044,7 @@
(match_dup 0) (match_dup 0)
(match_dup 2)))] (match_dup 2)))]
"TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0]) "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])
&& (GET_CODE (operands[1]) != REG || GENERAL_REGISTER_P (REGNO (operands[1])))" && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))"
[(set (match_dup 2) [(set (match_dup 2)
(if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))] (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))]
" "
...@@ -1548,7 +1548,7 @@ ...@@ -1548,7 +1548,7 @@
"" ""
" "
{ {
if (TARGET_SH1 && GET_CODE (operands[1]) == CONST_INT) if (TARGET_SH1 && CONST_INT_P (operands[1]))
{ {
emit_insn (gen_negsi2 (operands[0], operands[2])); emit_insn (gen_negsi2 (operands[0], operands[2]));
emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
...@@ -3054,7 +3054,7 @@ label: ...@@ -3054,7 +3054,7 @@ label:
" "
{ {
if (TARGET_SH1 if (TARGET_SH1
&& GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255) && CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 255)
{ {
emit_insn (gen_zero_extendqisi2 (operands[0], emit_insn (gen_zero_extendqisi2 (operands[0],
gen_lowpart (QImode, operands[1]))); gen_lowpart (QImode, operands[1])));
...@@ -3247,7 +3247,7 @@ label: ...@@ -3247,7 +3247,7 @@ label:
offset = SUBREG_BYTE (operands[0]); offset = SUBREG_BYTE (operands[0]);
operands[0] = SUBREG_REG (operands[0]); operands[0] = SUBREG_REG (operands[0]);
} }
gcc_assert (GET_CODE (operands[0]) == REG); gcc_assert (REG_P (operands[0]));
if (! TARGET_LITTLE_ENDIAN) if (! TARGET_LITTLE_ENDIAN)
offset += 8 - GET_MODE_SIZE (inmode); offset += 8 - GET_MODE_SIZE (inmode);
operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset); operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
...@@ -3360,7 +3360,7 @@ label: ...@@ -3360,7 +3360,7 @@ label:
int count, choice; int count, choice;
if (GET_CODE (operands[2]) != CONST_INT) if (!CONST_INT_P (operands[2]))
FAIL; FAIL;
count = INTVAL (operands[2]); count = INTVAL (operands[2]);
choice = rot_tab[count]; choice = rot_tab[count];
...@@ -3415,7 +3415,7 @@ label: ...@@ -3415,7 +3415,7 @@ label:
"TARGET_SH1" "TARGET_SH1"
" "
{ {
if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8) if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 8)
FAIL; FAIL;
}") }")
...@@ -3448,7 +3448,7 @@ label: ...@@ -3448,7 +3448,7 @@ label:
#" #"
"TARGET_SH3 "TARGET_SH3
&& reload_completed && reload_completed
&& GET_CODE (operands[2]) == CONST_INT && CONST_INT_P (operands[2])
&& ! satisfies_constraint_P27 (operands[2])" && ! satisfies_constraint_P27 (operands[2])"
[(set (match_dup 3) (match_dup 2)) [(set (match_dup 3) (match_dup 2))
(parallel (parallel
...@@ -3522,7 +3522,7 @@ label: ...@@ -3522,7 +3522,7 @@ label:
emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2])); emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2]));
DONE; DONE;
} }
if (GET_CODE (operands[2]) == CONST_INT if (CONST_INT_P (operands[2])
&& sh_dynamicalize_shift_p (operands[2])) && sh_dynamicalize_shift_p (operands[2]))
operands[2] = force_reg (SImode, operands[2]); operands[2] = force_reg (SImode, operands[2]);
if (TARGET_SH3) if (TARGET_SH3)
...@@ -3557,7 +3557,7 @@ label: ...@@ -3557,7 +3557,7 @@ label:
"TARGET_SH1" "TARGET_SH1"
" "
{ {
if (GET_CODE (operands[2]) != CONST_INT) if (!CONST_INT_P (operands[2]))
FAIL; FAIL;
/* It may be possible to call gen_ashlhi3 directly with more generic /* It may be possible to call gen_ashlhi3 directly with more generic
operands. Make sure operands[1] is a HImode register here. */ operands. Make sure operands[1] is a HImode register here. */
...@@ -3824,7 +3824,7 @@ label: ...@@ -3824,7 +3824,7 @@ label:
emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2])); emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2]));
DONE; DONE;
} }
if (GET_CODE (operands[2]) == CONST_INT if (CONST_INT_P (operands[2])
&& sh_dynamicalize_shift_p (operands[2])) && sh_dynamicalize_shift_p (operands[2]))
operands[2] = force_reg (SImode, operands[2]); operands[2] = force_reg (SImode, operands[2]);
if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2]))) if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
...@@ -3910,13 +3910,13 @@ label: ...@@ -3910,13 +3910,13 @@ label:
emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2])); emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2]));
DONE; DONE;
} }
if (GET_CODE (operands[2]) == CONST_INT if (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) == 1) && INTVAL (operands[2]) == 1)
{ {
emit_insn (gen_ashldi3_k (operands[0], operands[1])); emit_insn (gen_ashldi3_k (operands[0], operands[1]));
DONE; DONE;
} }
else if (GET_CODE (operands[2]) == CONST_INT else if (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) < 32) && INTVAL (operands[2]) < 32)
{ {
emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2])); emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
...@@ -3944,7 +3944,7 @@ label: ...@@ -3944,7 +3944,7 @@ label:
(match_operand:DI 2 "shift_count_operand" "r,n")))] (match_operand:DI 2 "shift_count_operand" "r,n")))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (arith_reg_dest (operands[0], DImode) && (arith_reg_dest (operands[0], DImode)
|| (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 32))" || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))"
"@ "@
shlrd %1, %2, %0 shlrd %1, %2, %0
shlri %1, %2, %0" shlri %1, %2, %0"
...@@ -3972,7 +3972,7 @@ label: ...@@ -3972,7 +3972,7 @@ label:
emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2])); emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2]));
DONE; DONE;
} }
if (GET_CODE (operands[2]) != CONST_INT if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) != 1) || INTVAL (operands[2]) != 1)
FAIL; FAIL;
}") }")
...@@ -3995,7 +3995,7 @@ label: ...@@ -3995,7 +3995,7 @@ label:
(match_operand:DI 2 "shift_count_operand" "r,n")))] (match_operand:DI 2 "shift_count_operand" "r,n")))]
"TARGET_SHMEDIA "TARGET_SHMEDIA
&& (arith_reg_dest (operands[0], DImode) && (arith_reg_dest (operands[0], DImode)
|| (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32))" || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))"
"@ "@
shard %1, %2, %0 shard %1, %2, %0
shari %1, %2, %0" shari %1, %2, %0"
...@@ -4041,7 +4041,7 @@ label: ...@@ -4041,7 +4041,7 @@ label:
emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2])); emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2]));
DONE; DONE;
} }
if (GET_CODE (operands[2]) != CONST_INT if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) != 1) || INTVAL (operands[2]) != 1)
FAIL; FAIL;
}") }")
...@@ -5091,7 +5091,7 @@ label: ...@@ -5091,7 +5091,7 @@ label:
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "immediate_operand" ""))] (match_operand:SI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed "TARGET_SHMEDIA && reload_completed
&& ((GET_CODE (operands[1]) == CONST_INT && ((CONST_INT_P (operands[1])
&& ! satisfies_constraint_I16 (operands[1])) && ! satisfies_constraint_I16 (operands[1]))
|| GET_CODE (operands[1]) == CONST_DOUBLE)" || GET_CODE (operands[1]) == CONST_DOUBLE)"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))]) [(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
...@@ -5279,9 +5279,9 @@ label: ...@@ -5279,9 +5279,9 @@ label:
"TARGET_SH1 "TARGET_SH1
&& (arith_reg_operand (operands[0], HImode) && (arith_reg_operand (operands[0], HImode)
|| arith_reg_operand (operands[1], HImode)) || arith_reg_operand (operands[1], HImode))
&& (GET_CODE (operands[0]) != MEM && (!MEM_P (operands[0])
|| GET_CODE (XEXP (operands[0], 0)) != PLUS || GET_CODE (XEXP (operands[0], 0)) != PLUS
|| GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != REG || !REG_P (XEXP (XEXP (operands[0], 0), 1))
|| ! refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0))" || ! refers_to_regno_p (R0_REG, R0_REG + 1, operands[1], (rtx *)0))"
"@ "@
mov.w %1,%0 mov.w %1,%0
...@@ -5366,9 +5366,9 @@ label: ...@@ -5366,9 +5366,9 @@ label:
{ {
int regno; int regno;
if ((GET_CODE (operands[0]) == MEM if ((MEM_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
|| (GET_CODE (operands[1]) == MEM || (MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == POST_INC)) && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
FAIL; FAIL;
...@@ -5532,7 +5532,7 @@ label: ...@@ -5532,7 +5532,7 @@ label:
[(set (match_operand:DI 0 "ext_dest_operand" "") [(set (match_operand:DI 0 "ext_dest_operand" "")
(match_operand:DI 1 "immediate_operand" ""))] (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed "TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_INT && CONST_INT_P (operands[1])
&& ! satisfies_constraint_I16 (operands[1])" && ! satisfies_constraint_I16 (operands[1])"
[(set (match_dup 0) (match_dup 2)) [(set (match_dup 0) (match_dup 2))
(match_dup 1)] (match_dup 1)]
...@@ -5764,8 +5764,8 @@ label: ...@@ -5764,8 +5764,8 @@ label:
"TARGET_SH1 "TARGET_SH1
&& (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
/* ??? We provide some insn so that direct_{load,store}[DFmode] get set */ /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3) || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3)) || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
&& (arith_reg_operand (operands[0], DFmode) && (arith_reg_operand (operands[0], DFmode)
|| arith_reg_operand (operands[1], DFmode))" || arith_reg_operand (operands[1], DFmode))"
"* return output_movedouble (insn, operands, DFmode);" "* return output_movedouble (insn, operands, DFmode);"
...@@ -5890,12 +5890,12 @@ label: ...@@ -5890,12 +5890,12 @@ label:
} }
if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0) if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
mem = SUBREG_REG (mem); mem = SUBREG_REG (mem);
if (GET_CODE (mem) == MEM) if (MEM_P (mem))
{ {
rtx addr = XEXP (mem, 0); rtx addr = XEXP (mem, 0);
if (GET_CODE (addr) == PLUS if (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == REG && REG_P (XEXP (addr, 0))
&& GET_CODE (XEXP (addr, 1)) == REG) && REG_P (XEXP (addr, 1)))
{ {
int offset; int offset;
rtx reg0 = gen_rtx_REG (Pmode, 0); rtx reg0 = gen_rtx_REG (Pmode, 0);
...@@ -6115,9 +6115,9 @@ label: ...@@ -6115,9 +6115,9 @@ label:
{ {
int regno; int regno;
if ((GET_CODE (operands[0]) == MEM if ((MEM_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
|| (GET_CODE (operands[1]) == MEM || (MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == POST_INC)) && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
FAIL; FAIL;
...@@ -6171,7 +6171,7 @@ label: ...@@ -6171,7 +6171,7 @@ label:
{ {
rtx addr, reg, const_int; rtx addr, reg, const_int;
if (GET_CODE (operands[1]) != MEM) if (!MEM_P (operands[1]))
FAIL; FAIL;
addr = XEXP (operands[1], 0); addr = XEXP (operands[1], 0);
if (GET_CODE (addr) != PLUS) if (GET_CODE (addr) != PLUS)
...@@ -6179,7 +6179,7 @@ label: ...@@ -6179,7 +6179,7 @@ label:
reg = XEXP (addr, 0); reg = XEXP (addr, 0);
const_int = XEXP (addr, 1); const_int = XEXP (addr, 1);
if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2]) if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
&& GET_CODE (const_int) == CONST_INT)) && CONST_INT_P (const_int)))
FAIL; FAIL;
emit_move_insn (operands[2], const_int); emit_move_insn (operands[2], const_int);
emit_move_insn (operands[0], emit_move_insn (operands[0],
...@@ -6199,7 +6199,7 @@ label: ...@@ -6199,7 +6199,7 @@ label:
{ {
rtx addr, reg, const_int; rtx addr, reg, const_int;
if (GET_CODE (operands[1]) != MEM) if (!MEM_P (operands[1]))
FAIL; FAIL;
addr = XEXP (operands[1], 0); addr = XEXP (operands[1], 0);
if (GET_CODE (addr) != PLUS) if (GET_CODE (addr) != PLUS)
...@@ -6207,7 +6207,7 @@ label: ...@@ -6207,7 +6207,7 @@ label:
reg = XEXP (addr, 0); reg = XEXP (addr, 0);
const_int = XEXP (addr, 1); const_int = XEXP (addr, 1);
if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2]) if (! (BASE_REGISTER_RTX_P (reg) && INDEX_REGISTER_RTX_P (operands[2])
&& GET_CODE (const_int) == CONST_INT)) && CONST_INT_P (const_int)))
FAIL; FAIL;
emit_move_insn (operands[2], const_int); emit_move_insn (operands[2], const_int);
emit_move_insn (change_address (operands[1], VOIDmode, emit_move_insn (change_address (operands[1], VOIDmode,
...@@ -6333,13 +6333,13 @@ label: ...@@ -6333,13 +6333,13 @@ label:
{ {
rtx x, y; rtx x, y;
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
x = adjust_address (operands[0], V2SFmode, x = adjust_address (operands[0], V2SFmode,
i * GET_MODE_SIZE (V2SFmode)); i * GET_MODE_SIZE (V2SFmode));
else else
x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8); x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8);
if (GET_CODE (operands[1]) == MEM) if (MEM_P (operands[1]))
y = adjust_address (operands[1], V2SFmode, y = adjust_address (operands[1], V2SFmode,
i * GET_MODE_SIZE (V2SFmode)); i * GET_MODE_SIZE (V2SFmode));
else else
...@@ -6377,7 +6377,7 @@ label: ...@@ -6377,7 +6377,7 @@ label:
{ {
rtx x,y; rtx x,y;
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
x = adjust_address (operands[0], V2SFmode, x = adjust_address (operands[0], V2SFmode,
i * GET_MODE_SIZE (V2SFmode)); i * GET_MODE_SIZE (V2SFmode));
else else
...@@ -6386,7 +6386,7 @@ label: ...@@ -6386,7 +6386,7 @@ label:
alter_subreg (&x); alter_subreg (&x);
} }
if (GET_CODE (operands[1]) == MEM) if (MEM_P (operands[1]))
y = adjust_address (operands[1], V2SFmode, y = adjust_address (operands[1], V2SFmode,
i * GET_MODE_SIZE (V2SFmode)); i * GET_MODE_SIZE (V2SFmode));
else else
...@@ -6475,8 +6475,8 @@ label: ...@@ -6475,8 +6475,8 @@ label:
"TARGET_SH1 "TARGET_SH1
&& (! TARGET_SH2E && (! TARGET_SH2E
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */ /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3) || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3)) || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
&& (arith_reg_operand (operands[0], SFmode) && (arith_reg_operand (operands[0], SFmode)
|| arith_reg_operand (operands[1], SFmode))" || arith_reg_operand (operands[1], SFmode))"
"@ "@
...@@ -7400,7 +7400,7 @@ label: ...@@ -7400,7 +7400,7 @@ label:
XEXP (operands[0], 0) = reg; XEXP (operands[0], 0) = reg;
} }
if (!flag_pic && TARGET_SH2A if (!flag_pic && TARGET_SH2A
&& GET_CODE (operands[0]) == MEM && MEM_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
{ {
if (sh2a_is_function_vector_call (XEXP (operands[0], 0))) if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
...@@ -7411,7 +7411,7 @@ label: ...@@ -7411,7 +7411,7 @@ label:
} }
} }
if (flag_pic && TARGET_SH2 if (flag_pic && TARGET_SH2
&& GET_CODE (operands[0]) == MEM && MEM_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
{ {
emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1])); emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
...@@ -7594,7 +7594,7 @@ label: ...@@ -7594,7 +7594,7 @@ label:
XEXP (operands[1], 0) = reg; XEXP (operands[1], 0) = reg;
} }
if (!flag_pic && TARGET_SH2A if (!flag_pic && TARGET_SH2A
&& GET_CODE (operands[1]) == MEM && MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
{ {
if (sh2a_is_function_vector_call (XEXP (operands[1], 0))) if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
...@@ -7605,7 +7605,7 @@ label: ...@@ -7605,7 +7605,7 @@ label:
} }
} }
if (flag_pic && TARGET_SH2 if (flag_pic && TARGET_SH2
&& GET_CODE (operands[1]) == MEM && MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
{ {
emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0), emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
...@@ -7800,7 +7800,7 @@ label: ...@@ -7800,7 +7800,7 @@ label:
XEXP (operands[0], 0) = reg; XEXP (operands[0], 0) = reg;
} }
if (flag_pic && TARGET_SH2 if (flag_pic && TARGET_SH2
&& GET_CODE (operands[0]) == MEM && MEM_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
/* The PLT needs the PIC register, but the epilogue would have /* The PLT needs the PIC register, but the epilogue would have
to restore it, so we can only use PC-relative PIC calls for to restore it, so we can only use PC-relative PIC calls for
...@@ -7992,7 +7992,7 @@ label: ...@@ -7992,7 +7992,7 @@ label:
XEXP (operands[1], 0) = reg; XEXP (operands[1], 0) = reg;
} }
if (flag_pic && TARGET_SH2 if (flag_pic && TARGET_SH2
&& GET_CODE (operands[1]) == MEM && MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
/* The PLT needs the PIC register, but the epilogue would have /* The PLT needs the PIC register, but the epilogue would have
to restore it, so we can only use PC-relative PIC calls for to restore it, so we can only use PC-relative PIC calls for
...@@ -8123,7 +8123,7 @@ label: ...@@ -8123,7 +8123,7 @@ label:
/* If epilogue clobbers r0, preserve it in macl. */ /* If epilogue clobbers r0, preserve it in macl. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
if ((set = single_set (insn)) if ((set = single_set (insn))
&& GET_CODE (SET_DEST (set)) == REG && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == R0_REG) && REGNO (SET_DEST (set)) == R0_REG)
{ {
rtx r0 = gen_rtx_REG (SImode, R0_REG); rtx r0 = gen_rtx_REG (SImode, R0_REG);
...@@ -9604,7 +9604,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -9604,7 +9604,7 @@ mov.l\\t1f,r0\\n\\
"TARGET_SH2E "TARGET_SH2E
&& (! reload_completed && (! reload_completed
|| true_regnum (operands[0]) != FPSCR_REG || true_regnum (operands[0]) != FPSCR_REG
|| GET_CODE (operands[1]) != MEM || !MEM_P (operands[1])
|| GET_CODE (XEXP (operands[1], 0)) != PLUS)" || GET_CODE (XEXP (operands[1], 0)) != PLUS)"
"@ "@
! precision stays the same ! precision stays the same
...@@ -10862,7 +10862,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10862,7 +10862,7 @@ mov.l\\t1f,r0\\n\\
size = bitsize / 8; size = bitsize / 8;
orig_address = XEXP (operands[0], 0); orig_address = XEXP (operands[0], 0);
shift_reg = gen_reg_rtx (SImode); shift_reg = gen_reg_rtx (SImode);
if (GET_CODE (x) == CONST_INT) if (CONST_INT_P (x))
{ {
v = INTVAL (x); v = INTVAL (x);
qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode))); qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
...@@ -10879,7 +10879,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10879,7 +10879,7 @@ mov.l\\t1f,r0\\n\\
while (size -= 1) while (size -= 1)
{ {
if (GET_CODE (x) == CONST_INT) if (CONST_INT_P (x))
qi_val qi_val
= force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode))); = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
else else
...@@ -10939,7 +10939,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10939,7 +10939,7 @@ mov.l\\t1f,r0\\n\\
if (TARGET_SH4A_ARCH if (TARGET_SH4A_ARCH
&& INTVAL (operands[2]) == 32 && INTVAL (operands[2]) == 32
&& INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
&& GET_CODE (operands[1]) == MEM && MEM_ALIGN (operands[1]) < 32) && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
{ {
rtx src = adjust_address (operands[1], BLKmode, 0); rtx src = adjust_address (operands[1], BLKmode, 0);
set_mem_size (src, GEN_INT (4)); set_mem_size (src, GEN_INT (4));
...@@ -10971,7 +10971,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -10971,7 +10971,7 @@ mov.l\\t1f,r0\\n\\
if (TARGET_SH4A_ARCH if (TARGET_SH4A_ARCH
&& INTVAL (operands[2]) == 32 && INTVAL (operands[2]) == 32
&& INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) && INTVAL (operands[3]) == -24 * (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN)
&& GET_CODE (operands[1]) == MEM && MEM_ALIGN (operands[1]) < 32) && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
{ {
rtx src = adjust_address (operands[1], BLKmode, 0); rtx src = adjust_address (operands[1], BLKmode, 0);
set_mem_size (src, GEN_INT (4)); set_mem_size (src, GEN_INT (4));
...@@ -11304,7 +11304,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -11304,7 +11304,7 @@ mov.l\\t1f,r0\\n\\
(set (mem:SF (match_dup 0)) (set (mem:SF (match_dup 0))
(match_operand:SF 2 "general_movsrc_operand" ""))] (match_operand:SF 2 "general_movsrc_operand" ""))]
"TARGET_SH1 && REGNO (operands[0]) == 0 "TARGET_SH1 && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16) && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
|| (GET_CODE (operands[2]) == SUBREG || (GET_CODE (operands[2]) == SUBREG
&& REGNO (SUBREG_REG (operands[2])) < 16)) && REGNO (SUBREG_REG (operands[2])) < 16))
&& reg_unused_after (operands[0], insn)" && reg_unused_after (operands[0], insn)"
...@@ -11317,7 +11317,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -11317,7 +11317,7 @@ mov.l\\t1f,r0\\n\\
(mem:SF (match_dup 0)))] (mem:SF (match_dup 0)))]
"TARGET_SH1 && REGNO (operands[0]) == 0 "TARGET_SH1 && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16) && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
|| (GET_CODE (operands[2]) == SUBREG || (GET_CODE (operands[2]) == SUBREG
&& REGNO (SUBREG_REG (operands[2])) < 16)) && REGNO (SUBREG_REG (operands[2])) < 16))
&& reg_unused_after (operands[0], insn)" && reg_unused_after (operands[0], insn)"
...@@ -11329,7 +11329,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -11329,7 +11329,7 @@ mov.l\\t1f,r0\\n\\
(set (mem:SF (match_dup 0)) (set (mem:SF (match_dup 0))
(match_operand:SF 2 "general_movsrc_operand" ""))] (match_operand:SF 2 "general_movsrc_operand" ""))]
"TARGET_SH2E && REGNO (operands[0]) == 0 "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG && ((REG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (operands[2]))) && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG || (GET_CODE (operands[2]) == SUBREG
&& FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2]))))) && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
...@@ -11343,7 +11343,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -11343,7 +11343,7 @@ mov.l\\t1f,r0\\n\\
(mem:SF (match_dup 0)))] (mem:SF (match_dup 0)))]
"TARGET_SH2E && REGNO (operands[0]) == 0 "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG && ((REG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (operands[2]))) && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG || (GET_CODE (operands[2]) == SUBREG
&& FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2]))))) && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
...@@ -11432,7 +11432,7 @@ mov.l\\t1f,r0\\n\\ ...@@ -11432,7 +11432,7 @@ mov.l\\t1f,r0\\n\\
operands[1] = XVECEXP (operands[1], 0, 0); operands[1] = XVECEXP (operands[1], 0, 0);
if (unit_size < 2) if (unit_size < 2)
{ {
if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (elt1) == CONST_INT) if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1))
operands[1] operands[1]
= GEN_INT (TARGET_LITTLE_ENDIAN = GEN_INT (TARGET_LITTLE_ENDIAN
? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8) ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8)
...@@ -13194,8 +13194,8 @@ mov.l\\t1f,r0\\n\\ ...@@ -13194,8 +13194,8 @@ mov.l\\t1f,r0\\n\\
" "
{ {
if (GET_MODE (operands[0]) != Pmode if (GET_MODE (operands[0]) != Pmode
|| GET_CODE (operands[1]) != CONST_INT || !CONST_INT_P (operands[1])
|| GET_CODE (operands[2]) != CONST_INT) || !CONST_INT_P (operands[2]))
FAIL; FAIL;
if (! TARGET_SHMEDIA) if (! TARGET_SHMEDIA)
operands[0] = force_reg (Pmode, operands[0]); operands[0] = force_reg (Pmode, operands[0]);
......
gcc/config/sh/symbian.c
...@@ -217,7 +217,7 @@ sh_symbian_mark_dllexport (tree decl) ...@@ -217,7 +217,7 @@ sh_symbian_mark_dllexport (tree decl)
tree idp; tree idp;
rtlname = XEXP (DECL_RTL (decl), 0); rtlname = XEXP (DECL_RTL (decl), 0);
if (GET_CODE (rtlname) == MEM) if (MEM_P (rtlname))
rtlname = XEXP (rtlname, 0); rtlname = XEXP (rtlname, 0);
gcc_assert (GET_CODE (rtlname) == SYMBOL_REF); gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
oldname = XSTR (rtlname, 0); oldname = XSTR (rtlname, 0);
...@@ -262,7 +262,7 @@ sh_symbian_mark_dllimport (tree decl) ...@@ -262,7 +262,7 @@ sh_symbian_mark_dllimport (tree decl)
rtx newrtl; rtx newrtl;
rtlname = XEXP (DECL_RTL (decl), 0); rtlname = XEXP (DECL_RTL (decl), 0);
if (GET_CODE (rtlname) == MEM) if (MEM_P (rtlname))
rtlname = XEXP (rtlname, 0); rtlname = XEXP (rtlname, 0);
gcc_assert (GET_CODE (rtlname) == SYMBOL_REF); gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
oldname = XSTR (rtlname, 0); oldname = XSTR (rtlname, 0);
...@@ -312,8 +312,8 @@ sh_symbian_encode_section_info (tree decl, rtx rtl, int first) ...@@ -312,8 +312,8 @@ sh_symbian_encode_section_info (tree decl, rtx rtl, int first)
else if ( (TREE_CODE (decl) == FUNCTION_DECL else if ( (TREE_CODE (decl) == FUNCTION_DECL
|| TREE_CODE (decl) == VAR_DECL) || TREE_CODE (decl) == VAR_DECL)
&& DECL_RTL (decl) != NULL_RTX && DECL_RTL (decl) != NULL_RTX
&& GET_CODE (DECL_RTL (decl)) == MEM && MEM_P (DECL_RTL (decl))
&& GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM && MEM_P (XEXP (DECL_RTL (decl), 0))
&& GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
&& sh_symbian_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0))) && sh_symbian_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
{ {
......
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