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riscv-gcc-1
Commit f1ab9717 by Marcus Shawcroft
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Reverting previous commit. 

From-SVN: r211410
parent c7f65aae
Showing with 10 additions and 14 deletions
gcc/ChangeLog
2014-06-10 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs)
(aarch64_save_or_restore_callee_save_registers): Fix layout.
2014-06-10 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Fix
......
gcc/config/aarch64/aarch64.c
......@@ -1917,6 +1917,7 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
rtx (*gen_mem_ref)(enum machine_mode, rtx)
= (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
{
if (aarch64_register_saved_on_entry (regno))
......@@ -1934,12 +1935,10 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
{
/* Empty loop. */
}
if (regno2 <= V31_REGNUM &&
aarch64_register_saved_on_entry (regno2))
{
rtx mem2;
/* Next highest register to be saved. */
mem2 = gen_mem_ref (DFmode,
plus_constant
......@@ -1965,8 +1964,8 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
gen_rtx_REG (DFmode, regno2));
}
/* The first part of a frame-related parallel insn is
always assumed to be relevant to the frame
/* The first part of a frame-related parallel insn
is always assumed to be relevant to the frame
calculations; subsequent parts, are only
frame-related if explicitly marked. */
RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
......@@ -1988,13 +1987,14 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
RTX_FRAME_RELATED_P (insn) = 1;
}
}
}
/* offset from the stack pointer of where the saves and
restore's have to happen. */
static void
aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
bool restore)
{
rtx insn;
......@@ -2027,7 +2027,6 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
aarch64_register_saved_on_entry (regno2))
{
rtx mem2;
/* Next highest register to be saved. */
mem2 = gen_mem_ref (Pmode,
plus_constant
......@@ -2051,11 +2050,12 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno2));
}
/* The first part of a frame-related parallel insn is
always assumed to be relevant to the frame
/* The first part of a frame-related parallel insn
is always assumed to be relevant to the frame
calculations; subsequent parts, are only
frame-related if explicitly marked. */
RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0,
1)) = 1;
regno = regno2;
start_offset += increment * 2;
}
......@@ -2075,6 +2075,7 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
}
aarch64_save_or_restore_fprs (start_offset, increment, restore, base_rtx);
}
/* AArch64 stack frames generated by this compiler look like:
......
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