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riscv-gcc-1
Commit f19f1e5e by Richard Henderson Committed by Richard Henderson
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ia64: -mfused-madd cleanup 

	* config.gcc [ia64-*] (extra_options): Add fused-madd.opt.
	* config/ia64/ia64.opt: Remove mfused-madd.
	* config/ia64/ia64.c (ia64_rtx_costs): Handle FP MULT, PLUS, FMA.
	* config/ia64/vms.h (TARGET_DEFAULT): Remove MASK_FUSED_MADD.
	* config/ia64/vms64.h (TARGET_DEFAULT): Likewise.
	* config/ia64/ia64.h (TARGET_DEFAULT): Likewise.
	* config/ia64/hpux.h (TARGET_DEFAULT): Likewise.
	* config/ia64/vect.md (addv2sf3, subv2sf3): Generate FMA.
	(*addv2sf3_1, *addv2sf3_2, *subv2sf3_1, *subv2sf3_2): Remove.
	(fmav2sf4): Rename from fpma; use FMA code.
	(fmsv2sf4): Rename from fpms; use FMA code.
	(fnmav2sf4): Rename from *fpnma; use FMA code.
	* config/ia64/ia64.md (MODE_SDF): New iterator.
	(suffix): New mode attribute.
	(*maddsf4, *msubsf4, *nmaddsf4): Remove.
	(fmssf4): Rename from *fmssf4.
	(fnmasf4): Rename from *nfmasf4.
	(*madddf4, *madddf4_trunc, *msubdf4, *msubdf4_trunc): Remove.
	(*nmadddf4, *nmadddf4_truncsf): Remove.
	(fmsdf4): Rename from *fmsdf4.
	(fnmadf4): Rename from *nfmadf4.
	(*fmadf_trunc_sf, *fmsdf_trunc_sf, *fnmadf_trunc_sf): New.
	(*maddxf4, *maddxf4_truncsf, *maddxf4_truncdf): Remove.
	(*msubxf4, *msubxf4_truncsf, *msubxf4_truncdf): Remove.
	(*nmaddxf4, *nmaddxf4_truncsf, *nmaddxf4_truncdf): Remove.
	(fmsxf4): Rename from *fmsxf4.
	(fnmaxf4): Rename from *nfmaxf4.
	(*fmaxf_trunc_<MODE_SDF>, *fmsxf_trunc_<MODE_SDF>): New.
	(*fnmaxf_trunc_<MODE_SDF>): New.

From-SVN: r166780
parent b6cfe8ac
Showing with 73 additions and 111 deletions
gcc/ChangeLog
2010-11-15 Richard Henderson <rth@redhat.com>
* config.gcc [ia64-*] (extra_options): Add fused-madd.opt.
* config/ia64/ia64.opt: Remove mfused-madd.
* config/ia64/ia64.c (ia64_rtx_costs): Handle FP MULT, PLUS, FMA.
* config/ia64/vms.h (TARGET_DEFAULT): Remove MASK_FUSED_MADD.
* config/ia64/vms64.h (TARGET_DEFAULT): Likewise.
* config/ia64/ia64.h (TARGET_DEFAULT): Likewise.
* config/ia64/hpux.h (TARGET_DEFAULT): Likewise.
* config/ia64/vect.md (addv2sf3, subv2sf3): Generate FMA.
(*addv2sf3_1, *addv2sf3_2, *subv2sf3_1, *subv2sf3_2): Remove.
(fmav2sf4): Rename from fpma; use FMA code.
(fmsv2sf4): Rename from fpms; use FMA code.
(fnmav2sf4): Rename from *fpnma; use FMA code.
* config/ia64/ia64.md (MODE_SDF): New iterator.
(suffix): New mode attribute.
(*maddsf4, *msubsf4, *nmaddsf4): Remove.
(fmssf4): Rename from *fmssf4.
(fnmasf4): Rename from *nfmasf4.
(*madddf4, *madddf4_trunc, *msubdf4, *msubdf4_trunc): Remove.
(*nmadddf4, *nmadddf4_truncsf): Remove.
(fmsdf4): Rename from *fmsdf4.
(fnmadf4): Rename from *nfmadf4.
(*fmadf_trunc_sf, *fmsdf_trunc_sf, *fnmadf_trunc_sf): New.
(*maddxf4, *maddxf4_truncsf, *maddxf4_truncdf): Remove.
(*msubxf4, *msubxf4_truncsf, *msubxf4_truncdf): Remove.
(*nmaddxf4, *nmaddxf4_truncsf, *nmaddxf4_truncdf): Remove.
(fmsxf4): Rename from *fmsxf4.
(fnmaxf4): Rename from *nfmaxf4.
(*fmaxf_trunc_<MODE_SDF>, *fmsxf_trunc_<MODE_SDF>): New.
(*fnmaxf_trunc_<MODE_SDF>): New.
2010-11-15 Jakub Jelinek <jakub@redhat.com> 2010-11-15 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/46461 PR tree-optimization/46461
gcc/config.gcc
...@@ -335,7 +335,7 @@ x86_64-*-*) ...@@ -335,7 +335,7 @@ x86_64-*-*)
ia64-*-*) ia64-*-*)
extra_headers=ia64intrin.h extra_headers=ia64intrin.h
need_64bit_hwint=yes need_64bit_hwint=yes
extra_options="${extra_options} g.opt" extra_options="${extra_options} g.opt fused-madd.opt"
;; ;;
hppa*-*-*) hppa*-*-*)
cpu_type=pa cpu_type=pa
......
gcc/config/ia64/hpux.h
...@@ -106,7 +106,7 @@ do { \ ...@@ -106,7 +106,7 @@ do { \
#undef TARGET_DEFAULT #undef TARGET_DEFAULT
#define TARGET_DEFAULT \ #define TARGET_DEFAULT \
(MASK_DWARF2_ASM | MASK_BIG_ENDIAN | MASK_ILP32 | MASK_FUSED_MADD) (MASK_DWARF2_ASM | MASK_BIG_ENDIAN | MASK_ILP32)
/* ??? Might not be needed anymore. */ /* ??? Might not be needed anymore. */
#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) ((MODE) == TFmode) #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) ((MODE) == TFmode)
......
gcc/config/ia64/ia64.c
...@@ -5273,13 +5273,18 @@ ia64_rtx_costs (rtx x, int code, int outer_code, int *total, ...@@ -5273,13 +5273,18 @@ ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
*total = COSTS_N_INSNS (3); *total = COSTS_N_INSNS (3);
return true; return true;
case FMA:
*total = COSTS_N_INSNS (4);
return true;
case MULT: case MULT:
/* For multiplies wider than HImode, we have to go to the FPU, /* For multiplies wider than HImode, we have to go to the FPU,
which normally involves copies. Plus there's the latency which normally involves copies. Plus there's the latency
of the multiply itself, and the latency of the instructions to of the multiply itself, and the latency of the instructions to
transfer integer regs to FP regs. */ transfer integer regs to FP regs. */
/* ??? Check for FP mode. */ if (FLOAT_MODE_P (GET_MODE (x)))
if (GET_MODE_SIZE (GET_MODE (x)) > 2) *total = COSTS_N_INSNS (4);
else if (GET_MODE_SIZE (GET_MODE (x)) > 2)
*total = COSTS_N_INSNS (10); *total = COSTS_N_INSNS (10);
else else
*total = COSTS_N_INSNS (2); *total = COSTS_N_INSNS (2);
...@@ -5287,6 +5292,13 @@ ia64_rtx_costs (rtx x, int code, int outer_code, int *total, ...@@ -5287,6 +5292,13 @@ ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
case PLUS: case PLUS:
case MINUS: case MINUS:
if (FLOAT_MODE_P (GET_MODE (x)))
{
*total = COSTS_N_INSNS (4);
return true;
}
/* FALLTHRU */
case ASHIFT: case ASHIFT:
case ASHIFTRT: case ASHIFTRT:
case LSHIFTRT: case LSHIFTRT:
......
gcc/config/ia64/ia64.h
...@@ -96,7 +96,7 @@ enum ia64_inline_type ...@@ -96,7 +96,7 @@ enum ia64_inline_type
/* Default target_flags if no switches are specified */ /* Default target_flags if no switches are specified */
#ifndef TARGET_DEFAULT #ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_FUSED_MADD) #define TARGET_DEFAULT (MASK_DWARF2_ASM)
#endif #endif
#ifndef TARGET_CPU_DEFAULT #ifndef TARGET_CPU_DEFAULT
......
gcc/config/ia64/ia64.opt
...@@ -178,8 +178,4 @@ msel-sched-dont-check-control-spec ...@@ -178,8 +178,4 @@ msel-sched-dont-check-control-spec
Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0) Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
Don't generate checks for control speculation in selective scheduling Don't generate checks for control speculation in selective scheduling
mfused-madd
Target Report Mask(FUSED_MADD)
Enable fused multiply/add and multiply/subtract instructions
; This comment is to ensure we retain the blank line above. ; This comment is to ensure we retain the blank line above.
gcc/config/ia64/vect.md
...@@ -903,106 +903,29 @@ ...@@ -903,106 +903,29 @@
"fpnegabs %0 = %1" "fpnegabs %0 = %1"
[(set_attr "itanium_class" "fmisc")]) [(set_attr "itanium_class" "fmisc")])
;; In order to convince combine to merge plus and mult to a useful fpma,
;; we need a couple of extra patterns.
(define_expand "addv2sf3" (define_expand "addv2sf3"
[(parallel
[(set (match_operand:V2SF 0 "fr_register_operand" "") [(set (match_operand:V2SF 0 "fr_register_operand" "")
(plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "") (fma:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
(match_operand:V2SF 2 "fr_register_operand" ""))) (match_dup 3)
(use (match_dup 3))])] (match_operand:V2SF 2 "fr_register_operand" "")))]
"" ""
{ {
rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
if (!TARGET_FUSED_MADD)
{
emit_insn (gen_fpma (operands[0], operands[1], operands[3], operands[2]));
DONE;
}
}) })
;; The split condition here could be combine_completed, if we had such.
(define_insn_and_split "*addv2sf3_1"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
(match_operand:V2SF 2 "fr_register_operand" "f")))
(use (match_operand:V2SF 3 "fr_register_operand" "f"))]
""
"#"
"reload_completed"
[(set (match_dup 0)
(plus:V2SF
(mult:V2SF (match_dup 1) (match_dup 3))
(match_dup 2)))]
"")
(define_insn_and_split "*addv2sf3_2"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(plus:V2SF
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
(match_operand:V2SF 2 "fr_register_operand" "f"))
(match_operand:V2SF 3 "fr_register_operand" "f")))
(use (match_operand:V2SF 4 "" "X"))]
""
"#"
""
[(set (match_dup 0)
(plus:V2SF
(mult:V2SF (match_dup 1) (match_dup 2))
(match_dup 3)))]
"")
;; In order to convince combine to merge minus and mult to a useful fpms,
;; we need a couple of extra patterns.
(define_expand "subv2sf3" (define_expand "subv2sf3"
[(parallel
[(set (match_operand:V2SF 0 "fr_register_operand" "") [(set (match_operand:V2SF 0 "fr_register_operand" "")
(minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "") (fma:V2SF
(match_operand:V2SF 2 "fr_register_operand" ""))) (match_operand:V2SF 1 "fr_register_operand" "")
(use (match_dup 3))])] (match_dup 3)
(neg:V2SF (match_operand:V2SF 2 "fr_register_operand" ""))))]
"" ""
{ {
rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
if (!TARGET_FUSED_MADD)
{
emit_insn (gen_fpms (operands[0], operands[1], operands[3], operands[2]));
DONE;
}
}) })
;; The split condition here could be combine_completed, if we had such.
(define_insn_and_split "*subv2sf3_1"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
(match_operand:V2SF 2 "fr_register_operand" "f")))
(use (match_operand:V2SF 3 "fr_register_operand" "f"))]
""
"#"
"reload_completed"
[(set (match_dup 0)
(minus:V2SF
(mult:V2SF (match_dup 1) (match_dup 3))
(match_dup 2)))]
"")
(define_insn_and_split "*subv2sf3_2"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(minus:V2SF
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
(match_operand:V2SF 2 "fr_register_operand" "f"))
(match_operand:V2SF 3 "fr_register_operand" "f")))
(use (match_operand:V2SF 4 "" "X"))]
""
"#"
""
[(set (match_dup 0)
(minus:V2SF
(mult:V2SF (match_dup 1) (match_dup 2))
(match_dup 3)))]
"")
(define_insn "mulv2sf3" (define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f") [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
...@@ -1011,22 +934,22 @@ ...@@ -1011,22 +934,22 @@
"fpmpy %0 = %1, %2" "fpmpy %0 = %1, %2"
[(set_attr "itanium_class" "fmac")]) [(set_attr "itanium_class" "fmac")])
(define_insn "fpma" (define_insn "fmav2sf4"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f") [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(plus:V2SF (fma:V2SF
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") (match_operand:V2SF 1 "fr_register_operand" "f")
(match_operand:V2SF 2 "fr_register_operand" "f")) (match_operand:V2SF 2 "fr_register_operand" "f")
(match_operand:V2SF 3 "fr_register_operand" "f")))] (match_operand:V2SF 3 "fr_register_operand" "f")))]
"" ""
"fpma %0 = %1, %2, %3" "fpma %0 = %1, %2, %3"
[(set_attr "itanium_class" "fmac")]) [(set_attr "itanium_class" "fmac")])
(define_insn "fpms" (define_insn "fmsv2sf4"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f") [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(minus:V2SF (fma:V2SF
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") (match_operand:V2SF 1 "fr_register_operand" "f")
(match_operand:V2SF 2 "fr_register_operand" "f")) (match_operand:V2SF 2 "fr_register_operand" "f")
(match_operand:V2SF 3 "fr_register_operand" "f")))] (neg:V2SF (match_operand:V2SF 3 "fr_register_operand" "f"))))]
"" ""
"fpms %0 = %1, %2, %3" "fpms %0 = %1, %2, %3"
[(set_attr "itanium_class" "fmac")]) [(set_attr "itanium_class" "fmac")])
...@@ -1040,12 +963,11 @@ ...@@ -1040,12 +963,11 @@
"fpnmpy %0 = %1, %2" "fpnmpy %0 = %1, %2"
[(set_attr "itanium_class" "fmac")]) [(set_attr "itanium_class" "fmac")])
(define_insn "*fpnma" (define_insn "fnmav2sf4"
[(set (match_operand:V2SF 0 "fr_register_operand" "=f") [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
(plus:V2SF (fma:V2SF
(neg:V2SF (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))
(mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") (match_operand:V2SF 2 "fr_register_operand" "f")
(match_operand:V2SF 2 "fr_register_operand" "f")))
(match_operand:V2SF 3 "fr_register_operand" "f")))] (match_operand:V2SF 3 "fr_register_operand" "f")))]
"" ""
"fpnma %0 = %1, %2, %3" "fpnma %0 = %1, %2, %3"
......
gcc/config/ia64/vms.h
...@@ -45,7 +45,7 @@ along with GCC; see the file COPYING3. If not see ...@@ -45,7 +45,7 @@ along with GCC; see the file COPYING3. If not see
/* Need .debug_line info generated from gcc and gas. */ /* Need .debug_line info generated from gcc and gas. */
#undef TARGET_DEFAULT #undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_GNU_AS | MASK_FUSED_MADD) #define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_GNU_AS)
#define VMS_DEBUG_MAIN_POINTER "TRANSFER$BREAK$GO" #define VMS_DEBUG_MAIN_POINTER "TRANSFER$BREAK$GO"
......
gcc/config/ia64/vms64.h
...@@ -36,6 +36,6 @@ along with GCC; see the file COPYING3. If not see ...@@ -36,6 +36,6 @@ along with GCC; see the file COPYING3. If not see
#define POINTER_SIZE 64 #define POINTER_SIZE 64
#undef TARGET_DEFAULT #undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_GNU_AS | MASK_FUSED_MADD | MASK_MALLOC64) #define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_GNU_AS | MASK_MALLOC64)
#include "config/vms/vms-crtl-64.h" #include "config/vms/vms-crtl-64.h"
gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c
/* { dg-do compile */ /* { dg-do compile */
/* { dg-options "-O2 -mno-fused-madd -ftree-vectorize" } */ /* { dg-options "-O2 -ffp-contract=off -ftree-vectorize" } */
/* { dg-final { scan-assembler "fpmpy" } } */ /* { dg-final { scan-assembler "fpmpy" } } */
/* fpma and fpms will show in either way because there are no /* fpma and fpms will show in either way because there are no
......
gcc/testsuite/gcc.target/ia64/mno-fused-madd.c
/* { dg-do compile */ /* { dg-do compile */
/* { dg-options "-O2 -mno-fused-madd" } */ /* { dg-options "-O2 -ffp-contract=off" } */
/* { dg-final { scan-assembler-not "fma" } } */ /* { dg-final { scan-assembler-not "fma" } } */
/* { dg-final { scan-assembler-not "fms" } } */ /* { dg-final { scan-assembler-not "fms" } } */
/* { dg-final { scan-assembler-not "fnma" } } */ /* { dg-final { scan-assembler-not "fnma" } } */
......
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