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riscv-gcc-1
Commit ee04b091 by Oleg Endo
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sh.md (mulsidi3, umulsidi3): Remove constraints in expander. 

	* config/sh/sh.md (mulsidi3, umulsidi3): Remove constraints in
	expander.  Use arith_reg_dest predicate.
	(rotldi3, rotrdi3): Remove constraints in expander.
	(adddi3_compact, subdi3_compact, mulsidi3_compact, umulsidi3_compact,
	ashlsi3_n, *ashlhi3_n, ashrsi2_16, ashrsi2_31, lshrsi3_n): Convert to
	insn_and_split.

From-SVN: r189603
parent 13f1f508
Showing with 65 additions and 116 deletions
gcc/ChangeLog
2012-07-18 Oleg Endo <olegendo@gcc.gnu.org> 2012-07-18 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.md (mulsidi3, umulsidi3): Remove constraints in
expander. Use arith_reg_dest predicate.
(rotldi3, rotrdi3): Remove constraints in expander.
(adddi3_compact, subdi3_compact, mulsidi3_compact, umulsidi3_compact,
ashlsi3_n, *ashlhi3_n, ashrsi2_16, ashrsi2_31, lshrsi3_n): Convert to
insn_and_split.
2012-07-18 Oleg Endo <olegendo@gcc.gnu.org>
PR target/33135 PR target/33135
* config/sh/sh.opt (mieee): Use Var instead of Mask. Correct * config/sh/sh.opt (mieee): Use Var instead of Mask. Correct
description. description.
......
gcc/config/sh/sh.md
...@@ -1431,21 +1431,14 @@ ...@@ -1431,21 +1431,14 @@
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_insn "adddi3_compact" (define_insn_and_split "adddi3_compact"
[(set (match_operand:DI 0 "arith_reg_dest" "=&r") [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
(plus:DI (match_operand:DI 1 "arith_reg_operand" "%0") (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
(match_operand:DI 2 "arith_reg_operand" "r"))) (match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1" "TARGET_SH1"
"#" "#"
[(set_attr "length" "6")]) "&& reload_completed"
(define_split
[(set (match_operand:DI 0 "arith_reg_dest" "")
(plus:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "arith_reg_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)] [(const_int 0)]
{ {
rtx high0 = gen_highpart (SImode, operands[0]); rtx high0 = gen_highpart (SImode, operands[0]);
...@@ -1556,21 +1549,14 @@ ...@@ -1556,21 +1549,14 @@
[(set_attr "type" "arith_media") [(set_attr "type" "arith_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_insn "subdi3_compact" (define_insn_and_split "subdi3_compact"
[(set (match_operand:DI 0 "arith_reg_dest" "=&r") [(set (match_operand:DI 0 "arith_reg_dest" "=&r")
(minus:DI (match_operand:DI 1 "arith_reg_operand" "0") (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
(match_operand:DI 2 "arith_reg_operand" "r"))) (match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1" "TARGET_SH1"
"#" "#"
[(set_attr "length" "6")]) "&& reload_completed"
(define_split
[(set (match_operand:DI 0 "arith_reg_dest" "")
(minus:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:DI 2 "arith_reg_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)] [(const_int 0)]
{ {
rtx high0 = gen_highpart (SImode, operands[0]); rtx high0 = gen_highpart (SImode, operands[0]);
...@@ -2861,9 +2847,9 @@ label: ...@@ -2861,9 +2847,9 @@ label:
[(set_attr "type" "dmpy")]) [(set_attr "type" "dmpy")])
(define_expand "mulsidi3" (define_expand "mulsidi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "")
(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))] (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
"TARGET_SH2 || TARGET_SHMEDIA" "TARGET_SH2 || TARGET_SHMEDIA"
{ {
if (TARGET_SH2) if (TARGET_SH2)
...@@ -2882,7 +2868,7 @@ label: ...@@ -2882,7 +2868,7 @@ label:
[(set_attr "type" "dmpy_media") [(set_attr "type" "dmpy_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_insn "mulsidi3_compact" (define_insn_and_split "mulsidi3_compact"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(mult:DI (mult:DI
(sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
...@@ -2890,16 +2876,8 @@ label: ...@@ -2890,16 +2876,8 @@ label:
(clobber (reg:SI MACH_REG)) (clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))] (clobber (reg:SI MACL_REG))]
"TARGET_SH2" "TARGET_SH2"
"#") "#"
"&& 1"
(define_split
[(set (match_operand:DI 0 "arith_reg_dest" "")
(mult:DI
(sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
(clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))]
"TARGET_SH2"
[(const_int 0)] [(const_int 0)]
{ {
rtx low_dst = gen_lowpart (SImode, operands[0]); rtx low_dst = gen_lowpart (SImode, operands[0]);
...@@ -2930,9 +2908,9 @@ label: ...@@ -2930,9 +2908,9 @@ label:
[(set_attr "type" "dmpy")]) [(set_attr "type" "dmpy")])
(define_expand "umulsidi3" (define_expand "umulsidi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "")
(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))] (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))]
"TARGET_SH2 || TARGET_SHMEDIA" "TARGET_SH2 || TARGET_SHMEDIA"
{ {
if (TARGET_SH2) if (TARGET_SH2)
...@@ -2951,7 +2929,7 @@ label: ...@@ -2951,7 +2929,7 @@ label:
[(set_attr "type" "dmpy_media") [(set_attr "type" "dmpy_media")
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_insn "umulsidi3_compact" (define_insn_and_split "umulsidi3_compact"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "=r")
(mult:DI (mult:DI
(zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")) (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
...@@ -2959,15 +2937,8 @@ label: ...@@ -2959,15 +2937,8 @@ label:
(clobber (reg:SI MACH_REG)) (clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))] (clobber (reg:SI MACL_REG))]
"TARGET_SH2" "TARGET_SH2"
"#") "#"
"&& 1"
(define_split
[(set (match_operand:DI 0 "arith_reg_dest" "")
(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
(clobber (reg:SI MACH_REG))
(clobber (reg:SI MACL_REG))]
"TARGET_SH2"
[(const_int 0)] [(const_int 0)]
{ {
rtx low_dst = gen_lowpart (SImode, operands[0]); rtx low_dst = gen_lowpart (SImode, operands[0]);
...@@ -3366,9 +3337,9 @@ label: ...@@ -3366,9 +3337,9 @@ label:
;; ------------------------------------------------------------------------- ;; -------------------------------------------------------------------------
(define_expand "rotldi3" (define_expand "rotldi3"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "")
(rotate:DI (match_operand:DI 1 "arith_reg_operand" "r") (rotate:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:HI 2 "mextr_bit_offset" "i")))] (match_operand:HI 2 "mextr_bit_offset" "")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
"if (! mextr_bit_offset (operands[2], HImode)) FAIL;") "if (! mextr_bit_offset (operands[2], HImode)) FAIL;")
...@@ -3387,9 +3358,9 @@ label: ...@@ -3387,9 +3358,9 @@ label:
[(set_attr "type" "arith_media")]) [(set_attr "type" "arith_media")])
(define_expand "rotrdi3" (define_expand "rotrdi3"
[(set (match_operand:DI 0 "arith_reg_dest" "=r") [(set (match_operand:DI 0 "arith_reg_dest" "")
(rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r") (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "")
(match_operand:HI 2 "mextr_bit_offset" "i")))] (match_operand:HI 2 "mextr_bit_offset" "")))]
"TARGET_SHMEDIA" "TARGET_SHMEDIA"
{ {
if (! mextr_bit_offset (operands[2], HImode)) if (! mextr_bit_offset (operands[2], HImode))
...@@ -3567,13 +3538,19 @@ label: ...@@ -3567,13 +3538,19 @@ label:
shll%O2 %0" shll%O2 %0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
(define_insn "ashlsi3_n" (define_insn_and_split "ashlsi3_n"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
(match_operand:SI 2 "const_int_operand" "n"))) (match_operand:SI 2 "const_int_operand" "n")))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])" "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
"#" "#"
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
{
gen_shifty_op (ASHIFT, operands);
DONE;
}
[(set (attr "length") [(set (attr "length")
(cond [(match_test "shift_insns_rtx (insn)") (cond [(match_test "shift_insns_rtx (insn)")
(const_string "2") (const_string "2")
...@@ -3584,18 +3561,6 @@ label: ...@@ -3584,18 +3561,6 @@ label:
(const_string "8"))) (const_string "8")))
(set_attr "type" "arith")]) (set_attr "type" "arith")])
(define_split
[(set (match_operand:SI 0 "arith_reg_dest" "")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
{
gen_shifty_op (ASHIFT, operands);
DONE;
})
(define_insn "ashlsi3_media" (define_insn "ashlsi3_media"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
(ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r") (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
...@@ -3631,21 +3596,6 @@ label: ...@@ -3631,21 +3596,6 @@ label:
FAIL; FAIL;
}) })
(define_insn "*ashlhi3_n"
[(set (match_operand:HI 0 "arith_reg_dest" "=r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
(match_operand:HI 2 "const_int_operand" "n")))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
"#"
[(set (attr "length")
(cond [(match_test "shift_insns_rtx (insn)")
(const_string "2")
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
(const_string "4")]
(const_string "6")))
(set_attr "type" "arith")])
(define_expand "ashlhi3" (define_expand "ashlhi3"
[(parallel [(set (match_operand:HI 0 "arith_reg_operand" "") [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "") (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
...@@ -3661,17 +3611,26 @@ label: ...@@ -3661,17 +3611,26 @@ label:
operands[1] = copy_to_mode_reg (HImode, operands[1]); operands[1] = copy_to_mode_reg (HImode, operands[1]);
}) })
(define_split (define_insn_and_split "*ashlhi3_n"
[(set (match_operand:HI 0 "arith_reg_dest" "") [(set (match_operand:HI 0 "arith_reg_dest" "=r")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "") (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
(match_operand:HI 2 "const_int_operand" ""))) (match_operand:HI 2 "const_int_operand" "n")))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed" "TARGET_SH1"
"#"
"&& reload_completed"
[(use (reg:SI R0_REG))] [(use (reg:SI R0_REG))]
{ {
gen_shifty_hi_op (ASHIFT, operands); gen_shifty_hi_op (ASHIFT, operands);
DONE; DONE;
}) }
[(set (attr "length")
(cond [(match_test "shift_insns_rtx (insn)")
(const_string "2")
(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
(const_string "4")]
(const_string "6")))
(set_attr "type" "arith")])
;; ;;
;; arithmetic shift right ;; arithmetic shift right
...@@ -3694,19 +3653,13 @@ label: ...@@ -3694,19 +3653,13 @@ label:
;; ??? This should be a define expand. ;; ??? This should be a define expand.
(define_insn "ashrsi2_16" (define_insn_and_split "ashrsi2_16"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r") (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
(const_int 16)))] (const_int 16)))]
"TARGET_SH1" "TARGET_SH1"
"#" "#"
[(set_attr "length" "4")]) "&& 1"
(define_split
[(set (match_operand:SI 0 "arith_reg_dest" "")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(const_int 16)))]
"TARGET_SH1"
[(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16))) [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
(set (match_dup 0) (sign_extend:SI (match_dup 2)))] (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
{ {
...@@ -3715,21 +3668,14 @@ label: ...@@ -3715,21 +3668,14 @@ label:
;; ??? This should be a define expand. ;; ??? This should be a define expand.
(define_insn "ashrsi2_31" (define_insn_and_split "ashrsi2_31"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
(const_int 31))) (const_int 31)))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1" "TARGET_SH1"
"#" "#"
[(set_attr "length" "4")]) "&& 1"
(define_split
[(set (match_operand:SI 0 "arith_reg_dest" "")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(const_int 31)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
[(const_int 0)] [(const_int 0)]
{ {
emit_insn (gen_ashlsi_c (operands[0], operands[1])); emit_insn (gen_ashlsi_c (operands[0], operands[1]));
...@@ -3799,7 +3745,7 @@ label: ...@@ -3799,7 +3745,7 @@ label:
(set_attr "highpart" "ignore")]) (set_attr "highpart" "ignore")])
(define_expand "ashrsi3" (define_expand "ashrsi3"
[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "") [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
(ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "") (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "nonmemory_operand" ""))) (match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:SI T_REG))])] (clobber (reg:SI T_REG))])]
...@@ -3846,13 +3792,19 @@ label: ...@@ -3846,13 +3792,19 @@ label:
"shlr%O2 %0" "shlr%O2 %0"
[(set_attr "type" "arith")]) [(set_attr "type" "arith")])
(define_insn "lshrsi3_n" (define_insn_and_split "lshrsi3_n"
[(set (match_operand:SI 0 "arith_reg_dest" "=r") [(set (match_operand:SI 0 "arith_reg_dest" "=r")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
(match_operand:SI 2 "const_int_operand" "n"))) (match_operand:SI 2 "const_int_operand" "n")))
(clobber (reg:SI T_REG))] (clobber (reg:SI T_REG))]
"TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])" "TARGET_SH1 && ! sh_dynamicalize_shift_p (operands[2])"
"#" "#"
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
{
gen_shifty_op (LSHIFTRT, operands);
DONE;
}
[(set (attr "length") [(set (attr "length")
(cond [(match_test "shift_insns_rtx (insn)") (cond [(match_test "shift_insns_rtx (insn)")
(const_string "2") (const_string "2")
...@@ -3863,18 +3815,6 @@ label: ...@@ -3863,18 +3815,6 @@ label:
(const_string "8"))) (const_string "8")))
(set_attr "type" "arith")]) (set_attr "type" "arith")])
(define_split
[(set (match_operand:SI 0 "arith_reg_dest" "")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
{
gen_shifty_op (LSHIFTRT, operands);
DONE;
})
(define_insn "lshrsi3_media" (define_insn "lshrsi3_media"
[(set (match_operand:SI 0 "arith_reg_dest" "=r,r") [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
(lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r") (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r")
......
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