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riscv-gcc-1
Commit ed4c4348 by Richard Earnshaw Committed by Richard Earnshaw
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arm.h (SECONDARY_INPUT_RELOAD_CLASS): Only need a secondary reload if reloading a MEM. 

* arm.h (SECONDARY_INPUT_RELOAD_CLASS): Only need a secondary reload
if reloading a MEM.
* arm.h (arm_adjust_cost): Renamed bogus prototype from
arm_adjust_code.
(bad_signed_byte_operand): Add prototype.
* arm.c (arm_override_options): Make I unsigned.
(const_ok_for_arm): Add casts to the constants.
(load_multiple_operation): Don't redeclare elt in sub-block.
(arm_gen_movstrqi): Delete external declaration of optimize.
(gen_compare_reg): Declare parameter fp.
* arm.c (final_prescan_insn): Only initialize scanbody if the insn
has a pattern.

From-SVN: r20738
parent 3c303f52
Showing with 33 additions and 11 deletions
gcc/ChangeLog
Fri Jun 26 06:58:54 1998 Richard Earnshaw (rearnsha@arm.com)
* arm.h (SECONDARY_INPUT_RELOAD_CLASS): Only need a secondary reload
if reloading a MEM.
* arm.h (arm_adjust_cost): Renamed bogus prototype from
arm_adjust_code.
(bad_signed_byte_operand): Add prototype.
* arm.c (arm_override_options): Make I unsigned.
(const_ok_for_arm): Add casts to the constants.
(load_multiple_operation): Don't redeclare elt in sub-block.
(arm_gen_movstrqi): Delete external declaration of optimize.
(gen_compare_reg): Declare parameter fp.
* arm.c (final_prescan_insn): Only initialize scanbody if the insn
has a pattern.
Fri Jun 26 09:31:24 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* alpha.c: Include system.h and toplev.h.
......
gcc/config/arm/arm.c
......@@ -221,7 +221,7 @@ arm_override_options ()
{
int arm_thumb_aware = 0;
int flags = 0;
int i;
unsigned i;
struct arm_cpu_select *ptr;
static struct cpu_default {
int cpu;
......@@ -406,13 +406,14 @@ int
const_ok_for_arm (i)
HOST_WIDE_INT i;
{
unsigned HOST_WIDE_INT mask = ~0xFF;
unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
/* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
be all zero, or all one. */
if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
&& ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
!= (((HOST_WIDE_INT) -1) & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
!= ((~(unsigned HOST_WIDE_INT) 0)
& ~(unsigned HOST_WIDE_INT) 0xffffffff)))
return FALSE;
/* Fast return for 0 and powers of 2 */
......@@ -426,7 +427,7 @@ const_ok_for_arm (i)
mask =
(mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
>> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
} while (mask != ~0xFF);
} while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
return FALSE;
}
......@@ -2293,7 +2294,7 @@ load_multiple_operation (op, mode)
for (; i < count; i++)
{
rtx elt = XVECEXP (op, 0, i);
elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
|| GET_CODE (SET_DEST (elt)) != REG
......@@ -2922,7 +2923,6 @@ arm_gen_movstrqi (operands)
rtx part_bytes_reg = NULL;
rtx mem;
int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
extern int optimize;
if (GET_CODE (operands[2]) != CONST_INT
|| GET_CODE (operands[3]) != CONST_INT
......@@ -3294,6 +3294,7 @@ rtx
gen_compare_reg (code, x, y, fp)
enum rtx_code code;
rtx x, y;
int fp;
{
enum machine_mode mode = SELECT_CC_MODE (code, x, y);
rtx cc_reg = gen_rtx (REG, mode, 24);
......@@ -5727,8 +5728,6 @@ final_prescan_insn (insn, opvec, noperands)
if (!this_insn)
break;
scanbody = PATTERN (this_insn);
switch (GET_CODE (this_insn))
{
case CODE_LABEL:
......@@ -5803,8 +5802,9 @@ final_prescan_insn (insn, opvec, noperands)
/* If this is an unconditional branch to the same label, succeed.
If it is to another label, do nothing. If it is conditional,
fail. */
/* XXX Probably, the test for the SET and the PC are unnecessary. */
/* XXX Probably, the tests for SET and the PC are unnecessary. */
scanbody = PATTERN (this_insn);
if (GET_CODE (scanbody) == SET
&& GET_CODE (SET_DEST (scanbody)) == PC)
{
......@@ -5839,6 +5839,7 @@ final_prescan_insn (insn, opvec, noperands)
case INSN:
/* Instructions using or affecting the condition codes make it
fail. */
scanbody = PATTERN (this_insn);
if ((GET_CODE (scanbody) == SET
|| GET_CODE (scanbody) == PARALLEL)
&& get_attr_conds (this_insn) != CONDS_NOCOND)
......
gcc/config/arm/arm.h
......@@ -874,7 +874,10 @@ enum reg_class
/* If we need to load shorts byte-at-a-time, then we need a scratch. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
(((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \
(((MODE) == HImode && TARGET_SHORT_BY_BYTES \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS)
/* Try a machine-dependent way of reloading an illegitimate address
......@@ -2028,7 +2031,7 @@ struct rtx_def *legitimize_pic_address (/* struct rtx_def *,
int is_pic (/* struct rtx_def * */);
void arm_finalize_pic (/* void */);
int arm_rtx_costs (/* struct rtx_def *, enum rtx_code, enum rtx_code */);
int arm_adjust_code (/* struct rtx_def *, struct rtx_def *,
int arm_adjust_cost (/* struct rtx_def *, struct rtx_def *,
struct rtx_def *, int */);
int const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
int neg_const_double_rtx_ok_for_fpu (/* struct rtx_def * */);
......@@ -2042,6 +2045,7 @@ int arm_add_operand (/* struct rtx_def *, enum machine_mode */);
int arm_not_operand (/* struct rtx_def *, enum machine_mode */);
int offsettable_memory_operand (/* struct rtx_def *, enum machine_mode */);
int alignable_memory_operand (/* struct rtx_def *, enum machine_mode */);
int bad_signed_byte_operand (/* struct rtx_def *, enum machine_mode */);
int fpu_rhs_operand (/* struct rtx_def *, enum machine_mode */);
int fpu_add_operand (/* struct rtx_def *, enum machine_mode */);
int power_of_two_operand (/* struct rtx_def *, enum machine_mode */);
......
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