[AArch64]Remove be_checked_get_lane, check bounds with __builtin_aarch64_im_lane_boundsi.

gcc/:

	PR target/63870
	* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane):
	Delete.
	* config/aarch64/aarch64-simd.md (aarch64_be_checked_get_lane<mode\>):
	Delete.
	* config/aarch64/arm_neon.h (aarch64_vget_lane_any): Use GCC
	vector extensions, __aarch64_lane, __builtin_aarch64_im_lane_boundsi.
	(__aarch64_vget_lane_f32, __aarch64_vget_lane_f64,
	__aarch64_vget_lane_p8, __aarch64_vget_lane_p16,
	__aarch64_vget_lane_s8, __aarch64_vget_lane_s16,
	__aarch64_vget_lane_s32, __aarch64_vget_lane_s64,
	__aarch64_vget_lane_u8, __aarch64_vget_lane_u16,
	__aarch64_vget_lane_u32, __aarch64_vget_lane_u64,
	__aarch64_vgetq_lane_f32, __aarch64_vgetq_lane_f64,
	__aarch64_vgetq_lane_p8, __aarch64_vgetq_lane_p16,
	__aarch64_vgetq_lane_s8, __aarch64_vgetq_lane_s16,
	__aarch64_vgetq_lane_s32, __aarch64_vgetq_lane_s64,
	__aarch64_vgetq_lane_u8, __aarch64_vgetq_lane_u16,
	__aarch64_vgetq_lane_u32, __aarch64_vgetq_lane_u64): Delete.
	(__aarch64_vdup_lane_any): Use __aarch64_vget_lane_any, remove
	'q2' argument.
	(__aarch64_vdup_lane_f32, __aarch64_vdup_lane_f64,
	__aarch64_vdup_lane_p8, __aarch64_vdup_lane_p16,
	__aarch64_vdup_lane_s8, __aarch64_vdup_lane_s16,
	__aarch64_vdup_lane_s32, __aarch64_vdup_lane_s64,
	__aarch64_vdup_lane_u8, __aarch64_vdup_lane_u16,
	__aarch64_vdup_lane_u32, __aarch64_vdup_lane_u64,
	__aarch64_vdup_laneq_f32, __aarch64_vdup_laneq_f64,
	__aarch64_vdup_laneq_p8, __aarch64_vdup_laneq_p16,
	__aarch64_vdup_laneq_s8, __aarch64_vdup_laneq_s16,
	__aarch64_vdup_laneq_s32, __aarch64_vdup_laneq_s64,
	__aarch64_vdup_laneq_u8, __aarch64_vdup_laneq_u16,
	__aarch64_vdup_laneq_u32, __aarch64_vdup_laneq_u64): Remove argument
	to __aarch64_vdup_lane_any.
	(vget_lane_f32, vget_lane_f64, vget_lane_p8, vget_lane_p16,
	vget_lane_s8, vget_lane_s16, vget_lane_s32, vget_lane_s64,
	vget_lane_u8, vget_lane_u16, vget_lane_u32, vget_lane_u64,
	vgetq_lane_f32, vgetq_lane_f64, vgetq_lane_p8, vgetq_lane_p16,
	vgetq_lane_s8, vgetq_lane_s16, vgetq_lane_s32, vgetq_lane_s64,
	vgetq_lane_u8, vgetq_lane_u16, vgetq_lane_u32, vgetq_lane_u64,
	vdupb_lane_p8, vdupb_lane_s8, vdupb_lane_u8, vduph_lane_p16,
	vduph_lane_s16, vduph_lane_u16, vdups_lane_f32, vdups_lane_s32,
	vdups_lane_u32, vdupb_laneq_p8, vdupb_laneq_s8, vdupb_laneq_u8,
	vduph_laneq_p16, vduph_laneq_s16, vduph_laneq_u16, vdups_laneq_f32,
	vdups_laneq_s32, vdups_laneq_u32, vdupd_laneq_f64, vdupd_laneq_s64,
	vdupd_laneq_u64, vfmas_lane_f32, vfma_laneq_f64, vfmad_laneq_f64,
	vfmas_laneq_f32, vfmss_lane_f32, vfms_laneq_f64, vfmsd_laneq_f64,
	vfmss_laneq_f32, vmla_lane_f32, vmla_lane_s16, vmla_lane_s32,
	vmla_lane_u16, vmla_lane_u32, vmla_laneq_f32, vmla_laneq_s16,
	vmla_laneq_s32, vmla_laneq_u16, vmla_laneq_u32, vmlaq_lane_f32,
	vmlaq_lane_s16, vmlaq_lane_s32, vmlaq_lane_u16, vmlaq_lane_u32,
	vmlaq_laneq_f32, vmlaq_laneq_s16, vmlaq_laneq_s32, vmlaq_laneq_u16,
	vmlaq_laneq_u32, vmls_lane_f32, vmls_lane_s16, vmls_lane_s32,
	vmls_lane_u16, vmls_lane_u32, vmls_laneq_f32, vmls_laneq_s16,
	vmls_laneq_s32, vmls_laneq_u16, vmls_laneq_u32, vmlsq_lane_f32,
	vmlsq_lane_s16, vmlsq_lane_s32, vmlsq_lane_u16, vmlsq_lane_u32,
	vmlsq_laneq_f32, vmlsq_laneq_s16, vmlsq_laneq_s32, vmlsq_laneq_u16,
	vmlsq_laneq_u32, vmul_lane_f32, vmul_lane_s16, vmul_lane_s32,
	vmul_lane_u16, vmul_lane_u32, vmuld_lane_f64, vmuld_laneq_f64,
	vmuls_lane_f32, vmuls_laneq_f32, vmul_laneq_f32, vmul_laneq_f64,
	vmul_laneq_s16, vmul_laneq_s32, vmul_laneq_u16, vmul_laneq_u32,
	vmulq_lane_f32, vmulq_lane_s16, vmulq_lane_s32, vmulq_lane_u16,
	vmulq_lane_u32, vmulq_laneq_f32, vmulq_laneq_f64, vmulq_laneq_s16,
	vmulq_laneq_s32, vmulq_laneq_u16, vmulq_laneq_u32) : Use
	__aarch64_vget_lane_any.

gcc/testsuite/:

	* gcc.target/aarch64/simd/vget_lane_f32_indices_1.c: New test.
	* gcc.target/aarch64/simd/vget_lane_f64_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_p16_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_p8_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_s16_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_s32_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_s64_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_s8_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_u16_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_u32_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_u64_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vget_lane_u8_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_f32_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_f64_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_p16_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_p8_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_s16_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_s32_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_s64_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_s8_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_u16_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_u32_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_u64_indices_1.c: Likewise.
	* gcc.target/aarch64/simd/vgetq_lane_u8_indices_1.c: Likewise.

From-SVN: r218536

gcc/ChangeLog

 2014-12-09  Alan Lawrence  <alan.lawrence@arm.com>
 
 	PR target/63870
+	* config/aarch64/aarch64-simd-builtins.def (be_checked_get_lane):
+	Delete.
+	* config/aarch64/aarch64-simd.md (aarch64_be_checked_get_lane<mode\>):
+	Delete.
+	* config/aarch64/arm_neon.h (aarch64_vget_lane_any): Use GCC
+	vector extensions, __aarch64_lane, __builtin_aarch64_im_lane_boundsi.
+	(__aarch64_vget_lane_f32, __aarch64_vget_lane_f64,
+	__aarch64_vget_lane_p8, __aarch64_vget_lane_p16,
+	__aarch64_vget_lane_s8, __aarch64_vget_lane_s16,
+	__aarch64_vget_lane_s32, __aarch64_vget_lane_s64,
+	__aarch64_vget_lane_u8, __aarch64_vget_lane_u16,
+	__aarch64_vget_lane_u32, __aarch64_vget_lane_u64,
+	__aarch64_vgetq_lane_f32, __aarch64_vgetq_lane_f64,
+	__aarch64_vgetq_lane_p8, __aarch64_vgetq_lane_p16,
+	__aarch64_vgetq_lane_s8, __aarch64_vgetq_lane_s16,
+	__aarch64_vgetq_lane_s32, __aarch64_vgetq_lane_s64,
+	__aarch64_vgetq_lane_u8, __aarch64_vgetq_lane_u16,
+	__aarch64_vgetq_lane_u32, __aarch64_vgetq_lane_u64): Delete.
+	(__aarch64_vdup_lane_any): Use __aarch64_vget_lane_any, remove
+	'q2' argument.
+	(__aarch64_vdup_lane_f32, __aarch64_vdup_lane_f64,
+	__aarch64_vdup_lane_p8, __aarch64_vdup_lane_p16,
+	__aarch64_vdup_lane_s8, __aarch64_vdup_lane_s16,
+	__aarch64_vdup_lane_s32, __aarch64_vdup_lane_s64,
+	__aarch64_vdup_lane_u8, __aarch64_vdup_lane_u16,
+	__aarch64_vdup_lane_u32, __aarch64_vdup_lane_u64,
+	__aarch64_vdup_laneq_f32, __aarch64_vdup_laneq_f64,
+	__aarch64_vdup_laneq_p8, __aarch64_vdup_laneq_p16,
+	__aarch64_vdup_laneq_s8, __aarch64_vdup_laneq_s16,
+	__aarch64_vdup_laneq_s32, __aarch64_vdup_laneq_s64,
+	__aarch64_vdup_laneq_u8, __aarch64_vdup_laneq_u16,
+	__aarch64_vdup_laneq_u32, __aarch64_vdup_laneq_u64): Remove argument
+	to __aarch64_vdup_lane_any.
+	(vget_lane_f32, vget_lane_f64, vget_lane_p8, vget_lane_p16,
+	vget_lane_s8, vget_lane_s16, vget_lane_s32, vget_lane_s64,
+	vget_lane_u8, vget_lane_u16, vget_lane_u32, vget_lane_u64,
+	vgetq_lane_f32, vgetq_lane_f64, vgetq_lane_p8, vgetq_lane_p16,
+	vgetq_lane_s8, vgetq_lane_s16, vgetq_lane_s32, vgetq_lane_s64,
+	vgetq_lane_u8, vgetq_lane_u16, vgetq_lane_u32, vgetq_lane_u64,
+	vdupb_lane_p8, vdupb_lane_s8, vdupb_lane_u8, vduph_lane_p16,
+	vduph_lane_s16, vduph_lane_u16, vdups_lane_f32, vdups_lane_s32,
+	vdups_lane_u32, vdupb_laneq_p8, vdupb_laneq_s8, vdupb_laneq_u8,
+	vduph_laneq_p16, vduph_laneq_s16, vduph_laneq_u16, vdups_laneq_f32,
+	vdups_laneq_s32, vdups_laneq_u32, vdupd_laneq_f64, vdupd_laneq_s64,
+	vdupd_laneq_u64, vfmas_lane_f32, vfma_laneq_f64, vfmad_laneq_f64,
+	vfmas_laneq_f32, vfmss_lane_f32, vfms_laneq_f64, vfmsd_laneq_f64,
+	vfmss_laneq_f32, vmla_lane_f32, vmla_lane_s16, vmla_lane_s32,
+	vmla_lane_u16, vmla_lane_u32, vmla_laneq_f32, vmla_laneq_s16,
+	vmla_laneq_s32, vmla_laneq_u16, vmla_laneq_u32, vmlaq_lane_f32,
+	vmlaq_lane_s16, vmlaq_lane_s32, vmlaq_lane_u16, vmlaq_lane_u32,
+	vmlaq_laneq_f32, vmlaq_laneq_s16, vmlaq_laneq_s32, vmlaq_laneq_u16,
+	vmlaq_laneq_u32, vmls_lane_f32, vmls_lane_s16, vmls_lane_s32,
+	vmls_lane_u16, vmls_lane_u32, vmls_laneq_f32, vmls_laneq_s16,
+	vmls_laneq_s32, vmls_laneq_u16, vmls_laneq_u32, vmlsq_lane_f32,
+	vmlsq_lane_s16, vmlsq_lane_s32, vmlsq_lane_u16, vmlsq_lane_u32,
+	vmlsq_laneq_f32, vmlsq_laneq_s16, vmlsq_laneq_s32, vmlsq_laneq_u16,
+	vmlsq_laneq_u32, vmul_lane_f32, vmul_lane_s16, vmul_lane_s32,
+	vmul_lane_u16, vmul_lane_u32, vmuld_lane_f64, vmuld_laneq_f64,
+	vmuls_lane_f32, vmuls_laneq_f32, vmul_laneq_f32, vmul_laneq_f64,
+	vmul_laneq_s16, vmul_laneq_s32, vmul_laneq_u16, vmul_laneq_u32,
+	vmulq_lane_f32, vmulq_lane_s16, vmulq_lane_s32, vmulq_lane_u16,
+	vmulq_lane_u32, vmulq_laneq_f32, vmulq_laneq_f64, vmulq_laneq_s16,
+	vmulq_laneq_s32, vmulq_laneq_u16, vmulq_laneq_u32) : Use
+	__aarch64_vget_lane_any.
+
+2014-12-09  Alan Lawrence  <alan.lawrence@arm.com>
+
+	PR target/63870
 	* gcc/config/aarch64-builtins.c (aarch64_simd_expand_args): Update error
 	message for SIMD_ARG_CONSTANT.
 

gcc/config/aarch64/aarch64-simd-builtins.def

@@ -49,9 +49,6 @@
   BUILTIN_VS (UNOP, ctz, 2)
   BUILTIN_VB (UNOP, popcount, 2)
 
-  /* be_checked_get_lane does its own lane swapping, so not a lane index.  */
-  BUILTIN_VALL (GETREG, be_checked_get_lane, 0)
-
   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
   BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)

gcc/config/aarch64/aarch64-simd.md

@@ -2438,22 +2438,9 @@
   [(set_attr "type" "neon_to_gp<q>")]
 )
 
-(define_expand "aarch64_be_checked_get_lane<mode>"
-  [(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand")
-   (match_operand:VALL 1 "register_operand")
-   (match_operand:SI 2 "immediate_operand")]
-  "TARGET_SIMD"
-  {
-    operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
-    emit_insn (gen_aarch64_get_lane<mode> (operands[0],
-					   operands[1],
-					   operands[2]));
-    DONE;
-  }
-)
-
 ;; Lane extraction of a value, neither sign nor zero extension
 ;; is guaranteed so upper bits should be considered undefined.
+;; RTL uses GCC vector extension indices throughout so flip only for assembly.
 (define_insn "aarch64_get_lane<mode>"
   [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=r, w, Utv")
 	(vec_select:<VEL>

gcc/testsuite/ChangeLog

 2014-12-09  Alan Lawrence  <alan.lawrence@arm.com>
 
 	PR target/63870
+	* gcc.target/aarch64/simd/vget_lane_f32_indices_1.c: New test.
+	* gcc.target/aarch64/simd/vget_lane_f64_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_p16_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_p8_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_s16_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_s32_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_s64_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_s8_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_u16_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_u32_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_u64_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vget_lane_u8_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_f32_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_f64_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_p16_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_p8_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_s16_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_s32_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_s64_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_s8_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_u16_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_u32_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_u64_indices_1.c: Likewise.
+	* gcc.target/aarch64/simd/vgetq_lane_u8_indices_1.c: Likewise.
+
+2014-12-09  Alan Lawrence  <alan.lawrence@arm.com>
+
+	PR target/63870
 	* gcc.target/aarch64/arg-type-diagnostics-1.c: Call intrinsic, update
 	expected error message.
 

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f32_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+float32_t
+test_vget_lane_f32_before (float32x2_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vget_lane_f32 (in, -1);
+}
+
+float32_t
+test_vget_lane_f32_beyond (float32x2_t in)
+{
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vget_lane_f32 (in, 2);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_f64_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+float64_t
+test_vget_lane_f64_before (float64x1_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  return vget_lane_f64 (in, -1);
+}
+
+float64_t
+test_vget_lane_f64_beyond (float64x1_t in)
+{
+  /* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  return vget_lane_f64 (in, 1);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p16_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+poly16_t
+test_vget_lane_p16_before (poly16x4_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vget_lane_p16 (in, -1);
+}
+
+poly16_t
+test_vget_lane_p16_beyond (poly16x4_t in)
+{
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vget_lane_p16 (in, 4);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_p8_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+poly8_t
+test_vget_lane_p8_before (poly8x8_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vget_lane_p8 (in, -1);
+}
+
+poly8_t
+test_vget_lane_p8_beyond (poly8x8_t in)
+{
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vget_lane_p8 (in, 8);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s16_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int16_t
+test_vget_lane_s16_before (int16x4_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vget_lane_s16 (in, -1);
+}
+
+int16_t
+test_vget_lane_s16_beyond (int16x4_t in)
+{
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vget_lane_s16 (in, 4);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s32_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int32_t
+test_vget_lane_s32_before (int32x2_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vget_lane_s32 (in, -1);
+}
+
+int32_t
+test_vget_lane_s32_beyond (int32x2_t in)
+{
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vget_lane_s32 (in, 2);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s64_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int64_t
+test_vget_lane_s64_before (int64x1_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  return vget_lane_s64 (in, -1);
+}
+
+int64_t
+test_vget_lane_s64_beyond (int64x1_t in)
+{
+  /* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  return vget_lane_s64 (in, 1);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_s8_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int8_t
+test_vget_lane_s8_before (int8x8_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vget_lane_s8 (in, -1);
+}
+
+int8_t
+test_vget_lane_s8_beyond (int8x8_t in)
+{
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vget_lane_s8 (in, 8);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u16_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint16_t
+test_vget_lane_u16_before (uint16x4_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vget_lane_u16 (in, -1);
+}
+
+uint16_t
+test_vget_lane_u16_beyond (uint16x4_t in)
+{
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vget_lane_u16 (in, 4);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u32_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint32_t
+test_vget_lane_u32_before (uint32x2_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vget_lane_u32 (in, -1);
+}
+
+uint32_t
+test_vget_lane_u32_beyond (uint32x2_t in)
+{
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vget_lane_u32 (in, 2);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u64_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint64_t
+test_vget_lane_u64_before (uint64x1_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  return vget_lane_u64 (in, -1);
+}
+
+uint64_t
+test_vget_lane_u64_beyond (uint64x1_t in)
+{
+  /* { dg-error "lane 1 out of range 0 - 0" "" {target *-*-*} 0 } */
+  return vget_lane_u64 (in, 1);
+}

gcc/testsuite/gcc.target/aarch64/simd/vget_lane_u8_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint8_t
+test_vget_lane_u8_before (uint8x8_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vget_lane_u8 (in, -1);
+}
+
+uint8_t
+test_vget_lane_u8_beyond (uint8x8_t in)
+{
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vget_lane_u8 (in, 8);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f32_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+float32_t
+test_vgetq_lane_f32_before (float32x4_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vgetq_lane_f32 (in, -1);
+}
+
+float32_t
+test_vgetq_lane_f32_beyond (float32x4_t in)
+{
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vgetq_lane_f32 (in, 4);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_f64_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+float64_t
+test_vgetq_lane_f64_before (float64x2_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vgetq_lane_f64 (in, -1);
+}
+
+float64_t
+test_vgetq_lane_f64_beyond (float64x2_t in)
+{
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vgetq_lane_f64 (in, 2);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p16_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+poly16_t
+test_vgetq_lane_p16_before (poly16x8_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vgetq_lane_p16 (in, -1);
+}
+
+poly16_t
+test_vgetq_lane_p16_beyond (poly16x8_t in)
+{
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vgetq_lane_p16 (in, 8);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_p8_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+poly8_t
+test_vgetq_lane_p8_before (poly8x16_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 15" "" {target *-*-*} 0 } */
+  return vgetq_lane_p8 (in, -1);
+}
+
+poly8_t
+test_vgetq_lane_p8_beyond (poly8x16_t in)
+{
+  /* { dg-error "lane 16 out of range 0 - 15" "" {target *-*-*} 0 } */
+  return vgetq_lane_p8 (in, 16);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s16_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int16_t
+test_vgetq_lane_s16_before (int16x8_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vgetq_lane_s16 (in, -1);
+}
+
+int16_t
+test_vgetq_lane_s16_beyond (int16x8_t in)
+{
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vgetq_lane_s16 (in, 8);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s32_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int32_t
+test_vgetq_lane_s32_before (int32x4_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vgetq_lane_s32 (in, -1);
+}
+
+int32_t
+test_vgetq_lane_s32_beyond (int32x4_t in)
+{
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vgetq_lane_s32 (in, 4);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s64_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int64_t
+test_vgetq_lane_s64_before (int64x2_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vgetq_lane_s64 (in, -1);
+}
+
+int64_t
+test_vgetq_lane_s64_beyond (int64x2_t in)
+{
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vgetq_lane_s64 (in, 2);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_s8_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+int8_t
+test_vgetq_lane_s8_before (int8x16_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 15" "" {target *-*-*} 0 } */
+  return vgetq_lane_s8 (in, -1);
+}
+
+int8_t
+test_vgetq_lane_s8_beyond (int8x16_t in)
+{
+  /* { dg-error "lane 16 out of range 0 - 15" "" {target *-*-*} 0 } */
+  return vgetq_lane_s8 (in, 16);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u16_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint16_t
+test_vgetq_lane_u16_before (uint16x8_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vgetq_lane_u16 (in, -1);
+}
+
+uint16_t
+test_vgetq_lane_u16_beyond (uint16x8_t in)
+{
+  /* { dg-error "lane 8 out of range 0 - 7" "" {target *-*-*} 0 } */
+  return vgetq_lane_u16 (in, 8);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u32_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint32_t
+test_vgetq_lane_u32_before (uint32x4_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vgetq_lane_u32 (in, -1);
+}
+
+uint32_t
+test_vgetq_lane_u32_beyond (uint32x4_t in)
+{
+  /* { dg-error "lane 4 out of range 0 - 3" "" {target *-*-*} 0 } */
+  return vgetq_lane_u32 (in, 4);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u64_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint64_t
+test_vgetq_lane_u64_before (uint64x2_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vgetq_lane_u64 (in, -1);
+}
+
+uint64_t
+test_vgetq_lane_u64_beyond (uint64x2_t in)
+{
+  /* { dg-error "lane 2 out of range 0 - 1" "" {target *-*-*} 0 } */
+  return vgetq_lane_u64 (in, 2);
+}

gcc/testsuite/gcc.target/aarch64/simd/vgetq_lane_u8_indices_1.c

+/* { dg-do assemble } */
+
+#include <arm_neon.h>
+
+uint8_t
+test_vgetq_lane_u8_before (uint8x16_t in)
+{
+  /* { dg-error "lane -1 out of range 0 - 15" "" {target *-*-*} 0 } */
+  return vgetq_lane_u8 (in, -1);
+}
+
+uint8_t
+test_vgetq_lane_u8_beyond (uint8x16_t in)
+{
+  /* { dg-error "lane 16 out of range 0 - 15" "" {target *-*-*} 0 } */
+  return vgetq_lane_u8 (in, 16);
+}