2017-09-11 Vidya Praveen <vidyapraveen@arm.com>

	Revert r251800 and r251799.

From-SVN: r251980

gcc/ChangeLog

+2017-09-11  Vidya Praveen  <vidyapraveen@arm.com>
+
+	Revert r251800 and r251799.
+
 2017-09-11  Martin Jambor  <mjambor@suse.cz>
 
 	PR hsa/82119

gcc/common/config/arm/arm-common.c

@@ -574,7 +574,7 @@ arm_canon_arch_option (int argc, const char **argv)
 	{
 	  /* The easiest and safest way to remove the default fpu
 	     capabilities is to look for a '+no..' option that removes
-	     the base FPU bit (isa_bit_vfpv2).  If that doesn't exist
+	     the base FPU bit (isa_bit_VFPv2).  If that doesn't exist
 	     then the best we can do is strip out all the bits that
 	     might be part of the most capable FPU we know about,
 	     which is "crypto-neon-fp-armv8".  */
@@ -586,7 +586,7 @@ arm_canon_arch_option (int argc, const char **argv)
 		   ++ext)
 		{
 		  if (ext->remove
-		      && check_isa_bits_for (ext->isa_bits, isa_bit_vfpv2))
+		      && check_isa_bits_for (ext->isa_bits, isa_bit_VFPv2))
 		    {
 		      arm_initialize_isa (fpu_isa, ext->isa_bits);
 		      bitmap_and_compl (target_isa, target_isa, fpu_isa);
@@ -620,7 +620,7 @@ arm_canon_arch_option (int argc, const char **argv)
     {
       /* Clearing the VFPv2 bit is sufficient to stop any extention that
 	 builds on the FPU from matching.  */
-      bitmap_clear_bit (target_isa, isa_bit_vfpv2);
+      bitmap_clear_bit (target_isa, isa_bit_VFPv2);
     }
 
   /* If we don't have a selected architecture by now, something's
@@ -692,8 +692,8 @@ arm_canon_arch_option (int argc, const char **argv)
      capable FPU variant that we do support.  This is sufficient for
      multilib selection.  */
 
-  if (bitmap_bit_p (target_isa_unsatisfied, isa_bit_vfpv2)
-      && bitmap_bit_p (fpu_isa, isa_bit_vfpv2))
+  if (bitmap_bit_p (target_isa_unsatisfied, isa_bit_VFPv2)
+      && bitmap_bit_p (fpu_isa, isa_bit_VFPv2))
     {
       std::list<candidate_extension *>::iterator ipoint = extensions.begin ();
 

gcc/config.gcc

@@ -593,7 +593,7 @@ x86_64-*-*)
 	tm_file="vxworks-dummy.h ${tm_file}"
 	;;
 arm*-*-*)
-	tm_p_file="arm/arm-flags.h ${tm_p_file} arm/aarch-common-protos.h"
+	tm_p_file="arm/arm-flags.h arm/arm-isa.h ${tm_p_file} arm/aarch-common-protos.h"
 	tm_file="vxworks-dummy.h ${tm_file}"
 	;;
 mips*-*-* | sh*-*-* | sparc*-*-*)

gcc/config/arm/arm-isa.h

+/* ISA feature bits for ARM.
+   Copyright (C) 2016-2017 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef ARM_ISA_FEATURE_H
+#define ARM_ISA_FEATURE_H
+
+enum isa_feature
+  {
+    isa_nobit,		/* Must be first.  */
+    isa_bit_ARMv3m,	/* Extended multiply.  */
+    isa_bit_mode26,	/* 26-bit mode support.  */
+    isa_bit_mode32,	/* 32-bit mode support.  */
+    isa_bit_ARMv4,	/* Architecture rel 4.  */
+    isa_bit_ARMv5,	/* Architecture rel 5.	*/
+    isa_bit_thumb,	/* Thumb aware.  */
+    isa_bit_ARMv5e,	/* Architecture rel 5e.  */
+    isa_bit_xscale,	/* XScale.  */
+    isa_bit_ARMv6,	/* Architecture rel 6.  */
+    isa_bit_ARMv6k,	/* Architecture rel 6k.  */
+    isa_bit_thumb2,	/* Thumb-2.  */
+    isa_bit_notm,	/* Instructions not present in 'M' profile.  */
+    isa_bit_be8,	/* Architecture uses be8 mode in big-endian.  */
+    isa_bit_tdiv,	/* Thumb division instructions.  */
+    isa_bit_ARMv7em,	/* Architecture rel 7e-m.  */
+    isa_bit_ARMv7,	/* Architecture rel 7.  */
+    isa_bit_adiv,	/* ARM division instructions.  */
+    isa_bit_ARMv8,	/* Architecture rel 8.  */
+    isa_bit_crc32,	/* ARMv8 CRC32 instructions.  */
+    isa_bit_iwmmxt,	/* XScale v2 (Wireless MMX).  */
+    isa_bit_iwmmxt2,	/* XScale Wireless MMX2.  */
+    isa_bit_ARMv8_1,	/* Architecture rel 8.1.  */
+    isa_bit_ARMv8_2,	/* Architecutre rel 8.2.  */
+    isa_bit_cmse,	/* M-Profile security extensions.  */
+    /* Floating point and Neon extensions.  */
+    /* VFPv1 is not supported in GCC.  */
+    isa_bit_VFPv2,	/* Vector floating point v2.  */
+    isa_bit_VFPv3,	/* Vector floating point v3.  */
+    isa_bit_VFPv4,	/* Vector floating point v4.  */
+    isa_bit_FPv5,	/* Floating point v5.  */
+    isa_bit_lpae,	/* ARMv7-A LPAE.  */
+    isa_bit_neon,	/* Advanced SIMD instructions.  */
+    isa_bit_fp16conv,	/* Conversions to/from fp16 (VFPv3 extension).  */
+    isa_bit_fp_dbl,	/* Double precision operations supported.  */
+    isa_bit_fp_d32,	/* 32 Double precision registers.  */
+    isa_bit_crypto,	/* Crypto extension to ARMv8.  */
+    isa_bit_fp16,	/* FP16 data processing (half-precision float).  */
+
+    /* ISA Quirks (errata?).  Don't forget to add this to the list of
+       all quirks below.  */
+    isa_quirk_no_volatile_ce,	/* No volatile memory in IT blocks.  */
+    isa_quirk_ARMv6kz,		/* Previously mis-identified by GCC.  */
+    isa_quirk_cm3_ldrd,		/* Cortex-M3 LDRD quirk.  */
+
+    /* Aren't currently, but probably should be tuning bits.  */
+    isa_bit_smallmul,	/* Slow multiply operations.  */
+
+    /* Tuning bits.  Should be elsewhere.  */
+    isa_tune_co_proc,	/* Has co-processor bus.  */
+    isa_tune_ldsched,	/* Load scheduling necessary.  */
+    isa_tune_strong,	/* StrongARM.  */
+    isa_tune_wbuf,	/* Schedule for write buffer ops (ARM6 & 7 only).  */
+
+    /* Must be last, used to dimension arrays.  */
+    isa_num_bits
+  };
+
+/* Helper macros for use when defining CPUs and architectures.
+
+   There must be no parenthesees in these lists, since they are used
+   to initialize arrays.  */
+
+#define ISA_ARMv2	isa_bit_notm
+#define ISA_ARMv3	ISA_ARMv2, isa_bit_mode32
+#define ISA_ARMv3m	ISA_ARMv3, isa_bit_ARMv3m
+#define ISA_ARMv4	ISA_ARMv3m, isa_bit_ARMv4
+#define ISA_ARMv4t	ISA_ARMv4, isa_bit_thumb
+#define ISA_ARMv5	ISA_ARMv4, isa_bit_ARMv5
+#define ISA_ARMv5t	ISA_ARMv5, isa_bit_thumb
+#define ISA_ARMv5e	ISA_ARMv5, isa_bit_ARMv5e
+#define ISA_ARMv5te	ISA_ARMv5e, isa_bit_thumb
+#define ISA_ARMv5tej	ISA_ARMv5te
+#define ISA_ARMv6	ISA_ARMv5te, isa_bit_ARMv6, isa_bit_be8
+#define ISA_ARMv6j	ISA_ARMv6
+#define ISA_ARMv6k	ISA_ARMv6, isa_bit_ARMv6k
+#define ISA_ARMv6z	ISA_ARMv6
+#define ISA_ARMv6kz	ISA_ARMv6k, isa_quirk_ARMv6kz
+#define ISA_ARMv6zk	ISA_ARMv6k
+#define ISA_ARMv6t2	ISA_ARMv6, isa_bit_thumb2
+
+/* This is suspect.  ARMv6-m doesn't really pull in any useful features
+   from ARMv5* or ARMv6.  */
+#define ISA_ARMv6m	isa_bit_mode32, isa_bit_ARMv3m, isa_bit_ARMv4, \
+    isa_bit_thumb, isa_bit_ARMv5, isa_bit_ARMv5e, isa_bit_ARMv6
+/* This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
+   integer SIMD instructions that are in ARMv6T2.  */
+#define ISA_ARMv7	ISA_ARMv6m, isa_bit_thumb2, isa_bit_ARMv7
+#define ISA_ARMv7a	ISA_ARMv7, isa_bit_notm, isa_bit_ARMv6k
+#define ISA_ARMv7ve	ISA_ARMv7a, isa_bit_adiv, isa_bit_tdiv, isa_bit_lpae
+#define ISA_ARMv7r	ISA_ARMv7a, isa_bit_tdiv
+#define ISA_ARMv7m	ISA_ARMv7, isa_bit_tdiv
+#define ISA_ARMv7em	ISA_ARMv7m, isa_bit_ARMv7em
+#define ISA_ARMv8a	ISA_ARMv7ve, isa_bit_ARMv8
+#define ISA_ARMv8_1a	ISA_ARMv8a, isa_bit_crc32, isa_bit_ARMv8_1
+#define ISA_ARMv8_2a	ISA_ARMv8_1a, isa_bit_ARMv8_2
+#define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
+#define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
+#define ISA_ARMv8r	ISA_ARMv8a
+
+/* List of all cryptographic extensions to stripout if crypto is
+   disabled.  Currently, that's trivial, but we define it anyway for
+   consistency with the SIMD and FP disable lists.  */
+#define ISA_ALL_CRYPTO	isa_bit_crypto
+
+/* List of all SIMD bits to strip out if SIMD is disabled.  This does
+   strip off 32 D-registers, but does not remove support for
+   double-precision FP.  */
+#define ISA_ALL_SIMD	isa_bit_fp_d32, isa_bit_neon, ISA_ALL_CRYPTO
+
+/* List of all FPU bits to strip out if -mfpu is used to override the
+   default.  isa_bit_fp16 is deliberately missing from this list.  */
+#define ISA_ALL_FPU_INTERNAL						\
+  isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5,		\
+  isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD
+
+/* Similarly, but including fp16 and other extensions that aren't part of
+   -mfpu support.  */
+#define ISA_ALL_FP	isa_bit_fp16, ISA_ALL_FPU_INTERNAL
+
+/* Useful combinations.  */
+#define ISA_VFPv2	isa_bit_VFPv2
+#define ISA_VFPv3	ISA_VFPv2, isa_bit_VFPv3
+#define ISA_VFPv4	ISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv
+#define ISA_FPv5	ISA_VFPv4, isa_bit_FPv5
+
+#define ISA_FP_DBL	isa_bit_fp_dbl
+#define ISA_FP_D32	ISA_FP_DBL, isa_bit_fp_d32
+#define ISA_FP_ARMv8	ISA_FPv5, ISA_FP_D32
+#define ISA_NEON	ISA_FP_D32, isa_bit_neon
+#define ISA_CRYPTO	ISA_NEON, isa_bit_crypto
+
+/* List of all quirk bits to strip out when comparing CPU features with
+   architectures.  */
+#define ISA_ALL_QUIRKS	isa_quirk_no_volatile_ce, isa_quirk_ARMv6kz,	\
+    isa_quirk_cm3_ldrd
+
+/* Helper macro so that we can concatenate multiple features together
+   with arm-*.def files, since macro substitution can't have commas within an
+   argument that lacks parenthesis.  */
+#define ISA_FEAT(X)	X,
+#endif

gcc/config/arm/arm.c

@@ -3361,22 +3361,22 @@ arm_option_override (void)
 
   /* Initialize boolean versions of the architectural flags, for use
      in the arm.md file.  */
-  arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m);
-  arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4);
+  arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv3m);
+  arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv4);
   arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
-  arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5);
-  arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5e);
+  arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5);
+  arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5e);
   arm_arch5te = arm_arch5e
     && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
-  arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6);
-  arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_armv6k);
+  arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6);
+  arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6k);
   arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm);
   arm_arch6m = arm_arch6 && !arm_arch_notm;
-  arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7);
-  arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_armv7em);
-  arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8);
-  arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_1);
-  arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2);
+  arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7);
+  arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7em);
+  arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8);
+  arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_1);
+  arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_2);
   arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
   arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
   arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
@@ -3406,9 +3406,9 @@ arm_option_override (void)
 
   /* And finally, set up some quirks.  */
   arm_arch_no_volatile_ce
-    = bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_volatile_ce);
-  arm_arch6kz = arm_arch6k && bitmap_bit_p (arm_active_target.isa,
-					    isa_bit_quirk_armv6kz);
+    = bitmap_bit_p (arm_active_target.isa, isa_quirk_no_volatile_ce);
+  arm_arch6kz
+    = arm_arch6k && bitmap_bit_p (arm_active_target.isa, isa_quirk_ARMv6kz);
 
   /* V5 code we generate is completely interworking capable, so we turn off
      TARGET_INTERWORK here to avoid many tests later on.  */
@@ -3453,7 +3453,7 @@ arm_option_override (void)
       else if (TARGET_HARD_FLOAT_ABI)
 	{
 	  arm_pcs_default = ARM_PCS_AAPCS_VFP;
-	  if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2))
+	  if (!bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv2))
 	    error ("-mfloat-abi=hard: selected processor lacks an FPU");
 	}
       else
@@ -3556,7 +3556,7 @@ arm_option_override (void)
   /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores.  */
   if (fix_cm3_ldrd == 2)
     {
-      if (bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_cm3_ldrd))
+      if (bitmap_bit_p (arm_active_target.isa, isa_quirk_cm3_ldrd))
 	fix_cm3_ldrd = 1;
       else
 	fix_cm3_ldrd = 0;

gcc/config/arm/arm.h

@@ -122,7 +122,7 @@ extern tree arm_fp16_type_node;
 /* Use hardware floating point instructions. */
 #define TARGET_HARD_FLOAT	(arm_float_abi != ARM_FLOAT_ABI_SOFT	\
 				 && bitmap_bit_p (arm_active_target.isa, \
-						  isa_bit_vfpv2))
+						  isa_bit_VFPv2))
 #define TARGET_SOFT_FLOAT	(!TARGET_HARD_FLOAT)
 /* User has permitted use of FP instructions, if they exist for this
    target.  */
@@ -169,10 +169,10 @@ extern tree arm_fp16_type_node;
 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32))
 
 /* FPU supports VFPv3 instructions.  */
-#define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3))
+#define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv3))
 
 /* FPU supports FPv5 instructions.  */
-#define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5))
+#define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_FPv5))
 
 /* FPU only supports VFP single-precision instructions.  */
 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE)
@@ -194,7 +194,7 @@ extern tree arm_fp16_type_node;
   (TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5))
 
 /* FPU supports fused-multiply-add operations.  */
-#define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4))
+#define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4))
 
 /* FPU supports Crypto extensions.  */
 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto))

gcc/config/arm/t-arm

@@ -20,7 +20,6 @@
 
 TM_H += arm-cpu.h
 GTM_H += arm-cpu.h
-OPTIONS_H_EXTRA += arm-isa.h
 
 # All md files - except for arm.md.
 # This list should be kept in alphabetical order and updated whenever an md
@@ -88,14 +87,6 @@ s-arm-cpu: $(srcdir)/config/arm/parsecpu.awk \
 	$(SHELL) $(srcdir)/../move-if-change tmp-arm-cpu.h arm-cpu.h
 	$(STAMP) s-arm-cpu
 
-arm-isa.h: s-arm-isa ; @true
-s-arm-isa: $(srcdir)/config/arm/parsecpu.awk \
-  $(srcdir)/config/arm/arm-cpus.in
-	$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=isa \
-		$(srcdir)/config/arm/arm-cpus.in > tmp-arm-isa.h
-	$(SHELL) $(srcdir)/../move-if-change tmp-arm-isa.h arm-isa.h
-	$(STAMP) s-arm-isa
-
 arm-cpu-data.h: s-arm-data ; @true
 s-arm-data: $(srcdir)/config/arm/parsecpu.awk \
   $(srcdir)/config/arm/arm-cpus.in