Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
R
riscv-gcc-1
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
riscv-gcc-1
Commits
e912eadf
Commit
e912eadf
authored
May 09, 2003
by
Richard Earnshaw
Committed by
Richard Earnshaw
May 09, 2003
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
* arm.md (clzsi2): The CLZ instruction is predicable.
From-SVN: r66637
parent
638db43e
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
6 additions
and
1 deletions
+6
-1
gcc/ChangeLog
+4
-0
gcc/config/arm/arm.md
+2
-1
No files found.
gcc/ChangeLog
View file @
e912eadf
2003-05-09 Richard Earnshaw <rearnsha@arm.com>
* arm.md (clzsi2): The CLZ instruction is predicable.
2003-05-09 Bob Wilson <bob.wilson@acm.org>
* config/xtensa/xtensa.c: Formatting.
...
...
gcc/config/arm/arm.md
View file @
e912eadf
...
...
@@ -8515,7 +8515,8 @@
[
(set (match_operand:SI 0 "s_register_operand" "=r")
(clz:SI (match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_ARM && arm_arch5"
"clz
\\
t%0, %1")
"clz%?
\\
t%0, %1"
[
(set_attr "predicable" "yes")
]
)
(define_expand "ffssi2"
[
(set (match_operand:SI 0 "s_register_operand" "")
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment