ia64.c (ia64_encode_addr_area): Use gcc_assert and gcc_unreachable as appropriate.

	* config/ia64/ia64.c (ia64_encode_addr_area): Use gcc_assert and
	gcc_unreachable as appropriate.
	(ia64_expand_load_address, ia64_expand_tls_address,
	ia64_split_tmode, ia64_split_tmode_move, ia64_expand_compare,
	ia64_expand_vecint_compare, ia64_expand_vecint_minmax,
	next_scratch_gr_reg, ia64_initial_elimination_offset,
	ia64_expand_prologue, ia64_expand_epilogue,
	ia64_output_dwarf_dtprel, ia64_print_operand,
	ia64_register_move_cost, first_instruction, rws_access_regno,
	update_set_flags, rtx_needs_barrier, group_barrier_needed_p,
	ia64_sched_init, ia64_variable_issue,
	ia64_first_cycle_multipass_dfs_lookahead_guard,
	ia64_dfa_new_cycle, issue_nops_and_insn, get_template, bundling,
	ia64_st_address_bypass_p, ia64_ld_address_bypass_p, process_set,
	process_for_unwind_directive, ia64_hpux_file_end): Likewise.
	* config/ia64/ia64.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
	* config/ia64/ia64.md (*arm_movdi_vfp, *movdf_vfp): Likewise.
	* config/ia64/predicates.md (got_symbolic_operand,
	sdata_symbolic_operand): Likewise.
	* config/ia64/vect.md (vcondv2sf): Likewise.

From-SVN: r98817

gcc/ChangeLog

+2005-04-27  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/ia64/ia64.c (ia64_encode_addr_area): Use gcc_assert and
+	gcc_unreachable as appropriate.
+	(ia64_expand_load_address, ia64_expand_tls_address,
+	ia64_split_tmode, ia64_split_tmode_move, ia64_expand_compare,
+	ia64_expand_vecint_compare, ia64_expand_vecint_minmax,
+	next_scratch_gr_reg, ia64_initial_elimination_offset,
+	ia64_expand_prologue, ia64_expand_epilogue,
+	ia64_output_dwarf_dtprel, ia64_print_operand,
+	ia64_register_move_cost, first_instruction, rws_access_regno,
+	update_set_flags, rtx_needs_barrier, group_barrier_needed_p,
+	ia64_sched_init, ia64_variable_issue,
+	ia64_first_cycle_multipass_dfs_lookahead_guard,
+	ia64_dfa_new_cycle, issue_nops_and_insn, get_template, bundling,
+	ia64_st_address_bypass_p, ia64_ld_address_bypass_p, process_set,
+	process_for_unwind_directive, ia64_hpux_file_end): Likewise.
+	* config/ia64/ia64.h (ASM_OUTPUT_ADDR_VEC_ELT): Likewise.
+	* config/ia64/ia64.md (*arm_movdi_vfp, *movdf_vfp): Likewise.
+	* config/ia64/predicates.md (got_symbolic_operand,
+	sdata_symbolic_operand): Likewise.
+	* config/ia64/vect.md (vcondv2sf): Likewise.
+
 2005-04-27  Matt Thomas <matt@3am-software.com>
 
 	* config/vax/vax.c (legitimate_constant_address_p): New.  Formerly
@@ -6,30 +29,27 @@
 	(INDEX_REGISTER_P): New.
 	(BASE_REGISTER_P): New.
 	(indirectable_constant_address_p): New.  Adapted from
-		INDIRECTABLE_CONSTANT_ADDRESS_P in vax.h.
-		Use SYMBOL_REF_LOCAL_P.
+	INDIRECTABLE_CONSTANT_ADDRESS_P in vax.h. Use SYMBOL_REF_LOCAL_P.
 	(indirectable_address_p): New.  Adapted from
 	INDIRECTABLE_ADDRESS_P in vax.h.
 	(nonindexed_address_p): New.  Adapted from
 	GO_IF_NONINDEXED_ADDRESS in vax.h.
-	(index_temp_p): New.  Adapted from
-		INDEX_TERM_P in vax.h.
-	(reg_plus_index_p): New.  Adapted from
-		GO_IF_REG_PLUS_INDEX in vax.h.
+	(index_temp_p): New.  Adapted from INDEX_TERM_P in vax.h.
+	(reg_plus_index_p): New.  Adapted from GO_IF_REG_PLUS_INDEX in vax.h.
 	(legitimate_address_p): New.  Adapted from
-		GO_IF_LEGITIMATE_ADDRESS in vax.h
+	GO_IF_LEGITIMATE_ADDRESS in vax.h.
 	(vax_mode_dependent_address_p): New.  Adapted from
-		GO_IF_MODE_DEPENDENT_ADDRESS in vax.h
+	GO_IF_MODE_DEPENDENT_ADDRESS in vax.h.
 	* config/vax/vax.h (CONSTANT_ADDRESS_P): Use
-		legitimate_constant_address_p
+	legitimate_constant_address_p.
 	(CONSTANT_P): Use legitimate_constant_p.
 	(INDIRECTABLE_CONSTANT_ADDRESS_P): Removed.
 	(INDIRECTABLE_ADDRESS_P): Removed.
 	(GO_IF_NONINDEXED_ADDRESS): Removed.
 	(INDEX_TEMP_P): Removed.
 	(GO_IF_REG_PLUS_INDEX): Removed.
-	(GO_IF_LEGITIMATE_ADDRESS): Use legitimate_address_p.
-		Two definitions, depending on whether REG_OK_STRICT is defined.
+	(GO_IF_LEGITIMATE_ADDRESS): Use legitimate_address_p. Two
+	definitions, depending on whether REG_OK_STRICT is defined.
 	(GO_IF_MODE_DEPENDENT_ADDRESS): Use vax_mode_dependent_address_p.
 	Two definitions, depending on whether REG_OK_STRICT is defined.
 	* config/vax/vax-protos.h (legitimate_constant_address_p): Prototype

gcc/config/ia64/ia64.h

@@ -1796,7 +1796,7 @@ do {									\
 /* This is how to output an element of a case-vector that is absolute.
    (Ia64 does not use such vectors, but we must define this macro anyway.)  */
 
-#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) gcc_unreachable ()
 
 /* Jump tables only need 8 byte alignment.  */
 

gcc/config/ia64/ia64.md

@@ -363,9 +363,8 @@
     "mov pr = %1, -1"
   };
 
-  if (which_alternative == 2 && ! TARGET_NO_PIC
-      && symbolic_operand (operands[1], VOIDmode))
-    abort ();
+  gcc_assert (which_alternative != 2 || TARGET_NO_PIC
+              || !symbolic_operand (operands[1], VOIDmode));
 
   return alt[which_alternative];
 }
@@ -700,10 +699,11 @@
 
   if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
     {
+      rtx out[2];
+
       /* We're hoping to transform everything that deals with XFmode
 	 quantities and GR registers early in the compiler.  */
-      if (no_new_pseudos)
-	abort ();
+      gcc_assert (!no_new_pseudos);
 
       /* Struct to register can just use TImode instead.  */
       if ((GET_CODE (operands[1]) == SUBREG
@@ -735,9 +735,7 @@
       if (register_operand (operands[1], XFmode))
 	operands[1] = spill_xfmode_operand (operands[1], 1);
 
-      if (GET_CODE (operands[1]) == MEM)
-	{
-	  rtx out[2];
+      gcc_assert (GET_CODE (operands[1]) == MEM);
 
       out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0));
       out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0) + 1);
@@ -747,15 +745,11 @@
       DONE;
     }
 
-      abort ();
-    }
-
   if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
     {
       /* We're hoping to transform everything that deals with XFmode
 	 quantities and GR registers early in the compiler.  */
-      if (no_new_pseudos)
-	abort ();
+      gcc_assert (!no_new_pseudos);
 
       /* Op0 can't be a GR_REG here, as that case is handled above.
 	 If op0 is a register, then we spill op1, so that we now have a
@@ -768,10 +762,11 @@
 	  operands[1] = spill_xfmode_operand (op1, 0);
 	}
 
-      else if (GET_CODE (operands[0]) == MEM)
+      else
 	{
 	  rtx in[2];
 
+          gcc_assert (GET_CODE (operands[0]) == MEM);
 	  in[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]));
 	  in[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
 
@@ -779,9 +774,6 @@
 	  emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
 	  DONE;
 	}
-
-      else
-	abort ();
     }
 
   if (! reload_in_progress && ! reload_completed)
@@ -2825,13 +2817,13 @@
   "TARGET_INLINE_SQRT"
 {
   rtx insn;
-  if (TARGET_INLINE_SQRT == INL_MIN_LAT)
 #if 0
+  if (TARGET_INLINE_SQRT == INL_MIN_LAT)
     insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]);
+  else
 #else
-    abort ();
+  gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
 #endif
-  else
   insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]);
   emit_insn (insn);
   DONE;
@@ -3323,13 +3315,13 @@
   "TARGET_INLINE_SQRT"
 {
   rtx insn;
-  if (TARGET_INLINE_SQRT == INL_MIN_LAT)
 #if 0
+  if (TARGET_INLINE_SQRT == INL_MIN_LAT)
     insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]);
+  else
 #else
-    abort ();
+  gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
 #endif
-  else
   insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]);
   emit_insn (insn);
   DONE;
@@ -3998,13 +3990,13 @@
   "TARGET_INLINE_SQRT"
 {
   rtx insn;
-  if (TARGET_INLINE_SQRT == INL_MIN_LAT)
 #if 0
+  if (TARGET_INLINE_SQRT == INL_MIN_LAT)
     insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]);
+  else
 #else
-    abort ();
+  gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT);
 #endif
-  else
   insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]);
   emit_insn (insn);
   DONE;
@@ -4351,7 +4343,7 @@
 			  (match_operand:DI 3 "nonmemory_operand" "r"))
 		 (match_operand:DI 4 "nonmemory_operand" "rI")))]
   "reload_in_progress"
-  "* abort ();"
+  "* gcc_unreachable ();"
   "reload_completed"
   [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
 			       (match_dup 3)))
@@ -5103,7 +5095,7 @@
 	   "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO,  rK")))]
   "ia64_move_ok (operands[0], operands[2])
    && ia64_move_ok (operands[0], operands[3])"
-  { abort (); }
+  { gcc_unreachable (); }
   [(set_attr "predicable" "no")])
 
 (define_split
@@ -5206,7 +5198,7 @@
 		    "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
   "ia64_move_ok (operands[0], operands[2])
    && ia64_move_ok (operands[0], operands[3])"
-  { abort (); }
+  { gcc_unreachable (); }
   [(set_attr "predicable" "no")])
 
 (define_insn "*abssi2_internal"
@@ -5605,12 +5597,10 @@
       start_sequence ();
       set = single_set (last);
 
-      if (! rtx_equal_p (SET_DEST (set), op0)
-	  || GET_CODE (SET_SRC (set)) != MEM)
-	abort ();
+      gcc_assert (rtx_equal_p (SET_DEST (set), op0)
+		  && GET_CODE (SET_SRC (set)) == MEM);
       addr = XEXP (SET_SRC (set), 0);
-      if (rtx_equal_p (addr, op0))
-	abort ();
+      gcc_assert (!rtx_equal_p (addr, op0));
     }
 
   /* Jump table elements are stored pc-relative.  That is, a displacement
@@ -5958,10 +5948,8 @@
   int i = (INTVAL (operands[1]));
   int j = (INTVAL (operands[2]));
 
-  if (i != 0 && i != 1)
-    abort ();
-  if (j < 0 || j > 3)
-    abort ();
+  gcc_assert (i == 0 || i == 1);
+  gcc_assert (j >= 0 && j <= 3);
   return alt[i][j];
 }
   [(set_attr "itanium_class" "lfetch")])

gcc/config/ia64/predicates.md

@@ -66,7 +66,7 @@
       return (INTVAL (op) & 0x3fff) == 0;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 })
 
@@ -125,7 +125,7 @@
       return (offset >= 0 && offset <= size);
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 })
 

gcc/config/ia64/vect.md

@@ -893,7 +893,7 @@
       break;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 
   cmp = gen_reg_rtx (V2SFmode);