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Commit e7ab5593 by Nick Clifton Committed by Nick Clifton
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mn10300.c: Fold code to 80-character width. 

        * config/mn10300/mn10300.c: Fold code to 80-character width.
        Replace GET_CODE (foo) == REG with REG_P (foo).  Likewise for
        MEM, CONST_INT and CONST_DOUBLE.
        (targetm): Move initialization to end of file.
        (print_operand): Rename to mn10300_print_operand.
        (print_operand_address): Rename to mn10300_print_operand_address.
        (can_use_return_insn): Rename to mn10300_can_use_return_insn.
        (expand_prologue): Rename to mn10300_expand_prologue.
        (expand_epilogue): Rename to mn10300_expand_epilogue.
        (initial_offset): Rename to mn10300_initial_offset.
        (function_arg): Rename to mn10300_function_arg.
        (mask_ok_for_mem_btst): Rename to mn10300_mask_ok_for_mem_btst.
        (symbolic_operand): Rename to mn10300_symbolic_operand.
        (legitimize_pic_address): Rename to mn10300_legitimize_pic_address.
        (legitimate_pic_operand_p): Rename to mn10300_legitimate_pic_operand_p.
        * config/mn10300/mn10300-protos.h: Update prototypes.
        * config/mn10300/mn10300.h: Fold code to 80-character width.
        Replace GET_CODE (foo) == REG with REG_P (foo).  Likewise for
        MEM, CONST_INT and CONST_DOUBLE.
        (CPP_SPEC): Move to...
        (TARGET_CPU_CPP_BUILTINS): ... here.
        * config/mn10300/mn10300.md: Fold code to 80-character width.
        Replace GET_CODE (foo) == REG with REG_P (foo).  Likewise for
        MEM, CONST_INT and CONST_DOUBLE.

From-SVN: r165778
parent 9dc3f7de
Showing with 384 additions and 337 deletions
gcc/ChangeLog
2010-10-21 Nick Clifton <nickc@redhat.com>
* config/mn10300/mn10300.c: Fold code to 80-character width.
Replace GET_CODE (foo) == REG with REG_P (foo). Likewise for
MEM, CONST_INT and CONST_DOUBLE.
(targetm): Move initialization to end of file.
(print_operand): Rename to mn10300_print_operand.
(print_operand_address): Rename to mn10300_print_operand_address.
(can_use_return_insn): Rename to mn10300_can_use_return_insn.
(expand_prologue): Rename to mn10300_expand_prologue.
(expand_epilogue): Rename to mn10300_expand_epilogue.
(initial_offset): Rename to mn10300_initial_offset.
(function_arg): Rename to mn10300_function_arg.
(mask_ok_for_mem_btst): Rename to mn10300_mask_ok_for_mem_btst.
(symbolic_operand): Rename to mn10300_symbolic_operand.
(legitimize_pic_address): Rename to mn10300_legitimize_pic_address.
(legitimate_pic_operand_p): Rename to mn10300_legitimate_pic_operand_p.
* config/mn10300/mn10300-protos.h: Update prototypes.
* config/mn10300/mn10300.h: Fold code to 80-character width.
Replace GET_CODE (foo) == REG with REG_P (foo). Likewise for
MEM, CONST_INT and CONST_DOUBLE.
(CPP_SPEC): Move to...
(TARGET_CPU_CPP_BUILTINS): ... here.
* config/mn10300/mn10300.md: Fold code to 80-character width.
Replace GET_CODE (foo) == REG with REG_P (foo). Likewise for
MEM, CONST_INT and CONST_DOUBLE.
2010-10-21 Ira Rosen <irar@il.ibm.com>
PR tree-optimization/46049
gcc/config/mn10300/mn10300-protos.h
......@@ -3,29 +3,29 @@
Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
This file is part of GCC.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define Mmode enum machine_mode
#define Cstar const char *
#define Rclas enum reg_class
#ifdef RTX_CODE
extern rtx legitimize_pic_address (rtx, rtx);
extern int legitimate_pic_operand_p (rtx);
extern rtx mn10300_legitimize_pic_address (rtx, rtx);
extern int mn10300_legitimate_pic_operand_p (rtx);
extern bool mn10300_function_value_regno_p (const unsigned int);
extern void mn10300_gen_multiple_store (int);
extern int mn10300_get_live_callee_saved_regs (void);
......@@ -33,25 +33,25 @@ extern bool mn10300_hard_regno_mode_ok (unsigned int, Mmode);
extern bool mn10300_legitimate_constant_p (rtx);
extern bool mn10300_modes_tieable (Mmode, Mmode);
extern Cstar mn10300_output_cmp (rtx, rtx);
extern void mn10300_print_operand (FILE *, rtx, int);
extern void mn10300_print_operand_address (FILE *, rtx);
extern void mn10300_print_reg_list (FILE *, int);
extern Rclas mn10300_secondary_reload_class (Rclas, Mmode, rtx);
extern Mmode mn10300_select_cc_mode (rtx);
extern int mn10300_store_multiple_operation (rtx, Mmode);
extern int mn10300_symbolic_operand (rtx, Mmode);
extern bool mn10300_wide_const_load_uses_clr (rtx operands[2]);
extern void print_operand (FILE *, rtx, int);
extern void print_operand_address (FILE *, rtx);
extern int store_multiple_operation (rtx, Mmode);
extern int symbolic_operand (rtx, Mmode);
#endif /* RTX_CODE */
#ifdef TREE_CODE
extern struct rtx_def *function_arg (CUMULATIVE_ARGS *, Mmode, tree, int);
extern struct rtx_def * mn10300_function_arg (CUMULATIVE_ARGS *, Mmode, tree, int);
#endif /* TREE_CODE */
extern int can_use_return_insn (void);
extern void expand_prologue (void);
extern void expand_epilogue (void);
extern int initial_offset (int, int);
extern int mask_ok_for_mem_btst (int, int);
extern int mn10300_can_use_return_insn (void);
extern void mn10300_expand_prologue (void);
extern void mn10300_expand_epilogue (void);
extern int mn10300_initial_offset (int, int);
extern int mn10300_mask_ok_for_mem_btst (int, int);
#undef Mmode
#undef Cstar
......
gcc/config/mn10300/mn10300.c
......@@ -3,21 +3,21 @@
2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
This file is part of GCC.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
......@@ -65,102 +65,12 @@ enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
+ 4 * df_regs_ever_live_p (3) \
+ 4 * df_regs_ever_live_p (6) \
+ 4 * df_regs_ever_live_p (7) \
+ 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \
|| df_regs_ever_live_p (16) || df_regs_ever_live_p (17)))
+ 16 * (df_regs_ever_live_p (14) \
|| df_regs_ever_live_p (15) \
|| df_regs_ever_live_p (16) \
|| df_regs_ever_live_p (17)))
static bool mn10300_handle_option (size_t, const char *, int);
static void mn10300_option_override (void);
static bool mn10300_legitimate_address_p (enum machine_mode, rtx, bool);
static int mn10300_address_cost_1 (rtx, int *);
static int mn10300_address_cost (rtx, bool);
static bool mn10300_rtx_costs (rtx, int, int, int *, bool);
static void mn10300_file_start (void);
static bool mn10300_return_in_memory (const_tree, const_tree);
static rtx mn10300_builtin_saveregs (void);
static void mn10300_va_start (tree, rtx);
static rtx mn10300_legitimize_address (rtx, rtx, enum machine_mode);
static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
const_tree, bool);
static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
static unsigned int mn10300_case_values_threshold (void);
static void mn10300_encode_section_info (tree, rtx, int);
static void mn10300_asm_trampoline_template (FILE *);
static void mn10300_trampoline_init (rtx, tree, rtx);
static rtx mn10300_function_value (const_tree, const_tree, bool);
static rtx mn10300_libcall_value (enum machine_mode, const_rtx);
static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
/* Initialize the GCC target structure. */
#undef TARGET_EXCEPT_UNWIND_INFO
#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS mn10300_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST mn10300_address_cost
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START mn10300_file_start
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION mn10300_handle_option
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE mn10300_option_override
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
#undef TARGET_CALLEE_COPIES
#define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
#undef TARGET_EXPAND_BUILTIN_SAVEREGS
#define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
#undef TARGET_EXPAND_BUILTIN_VA_START
#define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
#undef TARGET_CASE_VALUES_THRESHOLD
#define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
#define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
#undef TARGET_FUNCTION_VALUE
#define TARGET_FUNCTION_VALUE mn10300_function_value
#undef TARGET_LIBCALL_VALUE
#define TARGET_LIBCALL_VALUE mn10300_libcall_value
#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
struct gcc_target targetm = TARGET_INITIALIZER;
/* Implement TARGET_HANDLE_OPTION. */
......@@ -204,12 +114,11 @@ mn10300_file_start (void)
fprintf (asm_out_file, "\t.am33\n");
}
/* Print operand X using operand code CODE to assembly language output file
FILE. */
void
print_operand (FILE *file, rtx x, int code)
mn10300_print_operand (FILE *file, rtx x, int code)
{
switch (code)
{
......@@ -308,14 +217,14 @@ print_operand (FILE *file, rtx x, int code)
/* This is used for the operand to a call instruction;
if it's a REG, enclose it in parens, else output
the operand normally. */
if (GET_CODE (x) == REG)
if (REG_P (x))
{
fputc ('(', file);
print_operand (file, x, 0);
mn10300_print_operand (file, x, 0);
fputc (')', file);
}
else
print_operand (file, x, 0);
mn10300_print_operand (file, x, 0);
break;
case 'D':
......@@ -373,7 +282,7 @@ print_operand (FILE *file, rtx x, int code)
break;;
case VOIDmode:
case DImode:
print_operand_address (file,
mn10300_print_operand_address (file,
GEN_INT (CONST_DOUBLE_LOW (x)));
break;
default:
......@@ -430,7 +339,7 @@ print_operand (FILE *file, rtx x, int code)
gcc_unreachable ();
case VOIDmode:
case DImode:
print_operand_address (file,
mn10300_print_operand_address (file,
GEN_INT (CONST_DOUBLE_HIGH (x)));
break;
default:
......@@ -454,7 +363,7 @@ print_operand (FILE *file, rtx x, int code)
case 'A':
fputc ('(', file);
if (GET_CODE (XEXP (x, 0)) == REG)
if (REG_P ((XEXP (x, 0))))
output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
else
output_address (XEXP (x, 0));
......@@ -476,7 +385,7 @@ print_operand (FILE *file, rtx x, int code)
shift count as an error. So we mask off the high bits
of the immediate here. */
case 'S':
if (GET_CODE (x) == CONST_INT)
if (CONST_INT_P ((x)))
{
fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
break;
......@@ -522,7 +431,7 @@ print_operand (FILE *file, rtx x, int code)
case LABEL_REF:
case CODE_LABEL:
case UNSPEC:
print_operand_address (file, x);
mn10300_print_operand_address (file, x);
break;
default:
gcc_unreachable ();
......@@ -534,16 +443,16 @@ print_operand (FILE *file, rtx x, int code)
/* Output assembly language output for the address ADDR to FILE. */
void
print_operand_address (FILE *file, rtx addr)
mn10300_print_operand_address (FILE *file, rtx addr)
{
switch (GET_CODE (addr))
{
case POST_INC:
print_operand_address (file, XEXP (addr, 0));
mn10300_print_operand_address (file, XEXP (addr, 0));
fputc ('+', file);
break;
case REG:
print_operand (file, addr, 0);
mn10300_print_operand (file, addr, 0);
break;
case PLUS:
{
......@@ -556,9 +465,9 @@ print_operand_address (FILE *file, rtx addr)
base = XEXP (addr, 1), index = XEXP (addr, 0);
else
gcc_unreachable ();
print_operand (file, index, 0);
mn10300_print_operand (file, index, 0);
fputc (',', file);
print_operand (file, base, 0);;
mn10300_print_operand (file, base, 0);;
break;
}
case SYMBOL_REF:
......@@ -623,7 +532,7 @@ mn10300_print_reg_list (FILE *file, int mask)
}
int
can_use_return_insn (void)
mn10300_can_use_return_insn (void)
{
/* size includes the fixed stack space needed for function calls. */
int size = get_frame_size () + crtl->outgoing_args_size;
......@@ -739,7 +648,7 @@ mn10300_gen_multiple_store (int mask)
}
void
expand_prologue (void)
mn10300_expand_prologue (void)
{
HOST_WIDE_INT size;
......@@ -754,11 +663,14 @@ expand_prologue (void)
{
int num_regs_to_save = fp_regs_to_save (), i;
HOST_WIDE_INT xsize;
enum { save_sp_merge,
enum
{
save_sp_merge,
save_sp_no_merge,
save_sp_partial_merge,
save_a0_merge,
save_a0_no_merge } strategy;
save_a0_no_merge
} strategy;
unsigned int strategy_size = (unsigned)-1, this_strategy_size;
rtx reg;
......@@ -996,7 +908,7 @@ expand_prologue (void)
}
void
expand_epilogue (void)
mn10300_expand_epilogue (void)
{
HOST_WIDE_INT size;
......@@ -1237,7 +1149,8 @@ expand_epilogue (void)
registers it saves. Return 0 otherwise. */
int
store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
mn10300_store_multiple_operation (rtx op,
enum machine_mode mode ATTRIBUTE_UNUSED)
{
int count;
int mask;
......@@ -1252,7 +1165,7 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
/* Check that first instruction has the form (set (sp) (plus A B)) */
elt = XVECEXP (op, 0, 0);
if (GET_CODE (elt) != SET
|| GET_CODE (SET_DEST (elt)) != REG
|| (! REG_P (SET_DEST (elt)))
|| REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
|| GET_CODE (SET_SRC (elt)) != PLUS)
return 0;
......@@ -1262,9 +1175,9 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
the stack. We therefore expect the first instruction to create
COUNT-1 stack slots. */
elt = SET_SRC (elt);
if (GET_CODE (XEXP (elt, 0)) != REG
if ((! REG_P (XEXP (elt, 0)))
|| REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
|| GET_CODE (XEXP (elt, 1)) != CONST_INT
|| (! CONST_INT_P (XEXP (elt, 1)))
|| INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
return 0;
......@@ -1282,8 +1195,8 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
/* Check that element i is a (set (mem M) R) and that R is valid. */
elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
|| GET_CODE (SET_DEST (elt)) != MEM
|| GET_CODE (SET_SRC (elt)) != REG
|| (! MEM_P (SET_DEST (elt)))
|| (! REG_P (SET_SRC (elt)))
|| REGNO (SET_SRC (elt)) >= last)
return 0;
......@@ -1295,9 +1208,9 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
/* Check that M has the form (plus (sp) (const_int -I*4)) */
elt = XEXP (SET_DEST (elt), 0);
if (GET_CODE (elt) != PLUS
|| GET_CODE (XEXP (elt, 0)) != REG
|| (! REG_P (XEXP (elt, 0)))
|| REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
|| GET_CODE (XEXP (elt, 1)) != CONST_INT
|| (! CONST_INT_P (XEXP (elt, 1)))
|| INTVAL (XEXP (elt, 1)) != -i * 4)
return 0;
}
......@@ -1314,6 +1227,7 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
MODE into a register in register class RCLASS.
We might be able to simplify this. */
enum reg_class
mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
rtx in)
......@@ -1329,8 +1243,8 @@ mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
/* Memory loads less than a full word wide can't have an
address or stack pointer destination. They must use
a data register as an intermediate register. */
if ((GET_CODE (in) == MEM
|| (GET_CODE (inner) == REG
if ((MEM_P ((in))
|| (REG_P ((inner))
&& REGNO (inner) >= FIRST_PSEUDO_REGISTER))
&& (mode == QImode || mode == HImode)
&& (rclass == ADDRESS_REGS || rclass == SP_REGS
......@@ -1360,13 +1274,13 @@ mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
{
/* We can't load directly into an FP register from a
constant address. */
if (GET_CODE (in) == MEM
if (MEM_P ((in))
&& CONSTANT_ADDRESS_P (XEXP (in, 0)))
return DATA_OR_EXTENDED_REGS;
/* Handle case were a pseudo may not get a hard register
but has an equivalent memory location defined. */
if (GET_CODE (inner) == REG
if (REG_P ((inner))
&& REGNO (inner) >= FIRST_PSEUDO_REGISTER
&& reg_equiv_mem [REGNO (inner)]
&& CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0)))
......@@ -1378,7 +1292,7 @@ mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
}
int
initial_offset (int from, int to)
mn10300_initial_offset (int from, int to)
{
/* The difference between the argument pointer and the frame pointer
is the size of the callee register save area. */
......@@ -1497,7 +1411,7 @@ mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
from a function. If the result is NULL_RTX, the argument is pushed. */
rtx
function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
mn10300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
tree type, int named ATTRIBUTE_UNUSED)
{
rtx result = NULL_RTX;
......@@ -1651,12 +1565,12 @@ mn10300_output_cmp (rtx operand, rtx insn)
/* We allow the search to go through call insns. We record
the fact that we've past a CALL_INSN and reject matches which
use call clobbered registers. */
if (GET_CODE (temp) == CODE_LABEL
|| GET_CODE (temp) == JUMP_INSN
if (LABEL_P (temp)
|| JUMP_P (temp)
|| GET_CODE (temp) == BARRIER)
break;
if (GET_CODE (temp) == CALL_INSN)
if (CALL_P (temp))
past_call = 1;
if (GET_CODE (temp) == NOTE)
......@@ -1727,7 +1641,7 @@ mn10300_output_cmp (rtx operand, rtx insn)
/* Similarly, but when using a zero_extract pattern for a btst where
the source operand might end up in memory. */
int
mask_ok_for_mem_btst (int len, int bit)
mn10300_mask_ok_for_mem_btst (int len, int bit)
{
unsigned int mask = 0;
......@@ -1748,8 +1662,10 @@ mask_ok_for_mem_btst (int len, int bit)
/* Return 1 if X contains a symbolic expression. We know these
expressions will have one of a few well defined forms, so
we need only check those forms. */
int
symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
mn10300_symbolic_operand (rtx op,
enum machine_mode mode ATTRIBUTE_UNUSED)
{
switch (GET_CODE (op))
{
......@@ -1760,7 +1676,7 @@ symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
op = XEXP (op, 0);
return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
&& GET_CODE (XEXP (op, 1)) == CONST_INT);
&& CONST_INT_P ((XEXP (op, 1))));
default:
return 0;
}
......@@ -1778,18 +1694,19 @@ symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
But on a few ports with segmented architectures and indexed addressing
(mn10300, hppa) it is used to rewrite certain problematical addresses. */
static rtx
mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
enum machine_mode mode ATTRIBUTE_UNUSED)
{
if (flag_pic && ! legitimate_pic_operand_p (x))
x = legitimize_pic_address (oldx, NULL_RTX);
if (flag_pic && ! mn10300_legitimate_pic_operand_p (x))
x = mn10300_legitimize_pic_address (oldx, NULL_RTX);
/* Uh-oh. We might have an address for x[n-100000]. This needs
special handling to avoid creating an indexed memory address
with x-100000 as the base. */
if (GET_CODE (x) == PLUS
&& symbolic_operand (XEXP (x, 1), VOIDmode))
&& mn10300_symbolic_operand (XEXP (x, 1), VOIDmode))
{
/* Ugly. We modify things here so that the address offset specified
by the index expression is computed first, then added to x to form
......@@ -1808,7 +1725,8 @@ mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
regx1 = force_reg (Pmode,
gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2));
gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1,
regy2));
return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
}
}
......@@ -1817,8 +1735,9 @@ mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
@GOTOFF in `reg'. */
rtx
legitimize_pic_address (rtx orig, rtx reg)
mn10300_legitimize_pic_address (rtx orig, rtx reg)
{
if (GET_CODE (orig) == LABEL_REF
|| (GET_CODE (orig) == SYMBOL_REF
......@@ -1844,11 +1763,12 @@ legitimize_pic_address (rtx orig, rtx reg)
/* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
isn't protected by a PIC unspec; nonzero otherwise. */
int
legitimate_pic_operand_p (rtx x)
mn10300_legitimate_pic_operand_p (rtx x)
{
register const char *fmt;
register int i;
const char *fmt;
int i;
if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
return 0;
......@@ -1869,10 +1789,11 @@ legitimate_pic_operand_p (rtx x)
int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j)))
return 0;
}
else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
else if (fmt[i] == 'e'
&& ! mn10300_legitimate_pic_operand_p (XEXP (x, i)))
return 0;
}
......@@ -1897,7 +1818,7 @@ static bool
mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
{
if (CONSTANT_ADDRESS_P (x)
&& (! flag_pic || legitimate_pic_operand_p (x)))
&& (! flag_pic || mn10300_legitimate_pic_operand_p (x)))
return TRUE;
if (RTX_OK_FOR_BASE_P (x, strict))
......@@ -1929,12 +1850,12 @@ mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
if (base != 0 && index != 0)
{
if (GET_CODE (index) == CONST_INT)
if (CONST_INT_P ((index)))
return TRUE;
if (GET_CODE (index) == CONST
&& GET_CODE (XEXP (index, 0)) != PLUS
&& (! flag_pic
|| (legitimate_pic_operand_p (index)
|| (mn10300_legitimate_pic_operand_p (index)
&& GET_MODE_SIZE (mode) == 4)))
return TRUE;
}
......@@ -1958,7 +1879,7 @@ mn10300_legitimate_constant_p (rtx x)
if (GET_CODE (x) == PLUS)
{
if (GET_CODE (XEXP (x, 1)) != CONST_INT)
if (! CONST_INT_P (XEXP (x, 1)))
return false;
x = XEXP (x, 0);
}
......@@ -1981,7 +1902,7 @@ mn10300_legitimate_constant_p (rtx x)
}
/* We must have drilled down to a symbol. */
if (!symbolic_operand (x, Pmode))
if (! mn10300_symbolic_operand (x, Pmode))
return false;
break;
......@@ -2066,7 +1987,8 @@ mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
}
static bool
mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRIBUTE_UNUSED)
mn10300_rtx_costs (rtx x, int code, int outer_code, int *total,
bool speed ATTRIBUTE_UNUSED)
{
switch (code)
{
......@@ -2128,7 +2050,7 @@ mn10300_wide_const_load_uses_clr (rtx operands[2])
{
long val[2] = {0, 0};
if (GET_CODE (operands[0]) != REG
if (! REG_P (operands[0])
|| REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
return false;
......@@ -2173,7 +2095,7 @@ mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
{
rtx symbol;
if (GET_CODE (rtl) != MEM)
if (! MEM_P (rtl))
return;
symbol = XEXP (rtl, 0);
if (GET_CODE (symbol) != SYMBOL_REF)
......@@ -2331,3 +2253,72 @@ mn10300_select_cc_mode (rtx x)
return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ? CC_FLOATmode : CCmode;
}
/* Initialize the GCC target structure. */
#undef TARGET_EXCEPT_UNWIND_INFO
#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
#undef TARGET_LEGITIMIZE_ADDRESS
#define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS mn10300_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST mn10300_address_cost
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START mn10300_file_start
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION mn10300_handle_option
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE mn10300_option_override
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
#undef TARGET_CALLEE_COPIES
#define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
#undef TARGET_EXPAND_BUILTIN_SAVEREGS
#define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
#undef TARGET_EXPAND_BUILTIN_VA_START
#define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
#undef TARGET_CASE_VALUES_THRESHOLD
#define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
#undef TARGET_LEGITIMATE_ADDRESS_P
#define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
#define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
#undef TARGET_FUNCTION_VALUE
#define TARGET_FUNCTION_VALUE mn10300_function_value
#undef TARGET_LIBCALL_VALUE
#define TARGET_LIBCALL_VALUE mn10300_libcall_value
#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
struct gcc_target targetm = TARGET_INITIALIZER;
gcc/config/mn10300/mn10300.h
......@@ -4,22 +4,21 @@
2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
This file is part of GCC.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef ASM_SPEC
#undef LIB_SPEC
......@@ -38,14 +37,21 @@ along with GCC; see the file COPYING3. If not see
builtin_define ("__MN10300__"); \
builtin_assert ("cpu=mn10300"); \
builtin_assert ("machine=mn10300"); \
\
if (TARGET_AM33_2) \
{ \
builtin_define ("__AM33__=2"); \
builtin_define ("__AM33_2__"); \
} \
else if (TARGET_AM33) \
builtin_define ("__AM33__=1"); \
} \
while (0)
#define CPP_SPEC "%{mam33:-D__AM33__} %{mam33-2:-D__AM33__=2 -D__AM33_2__}"
extern GTY(()) int mn10300_unspec_int_label_counter;
enum processor_type {
enum processor_type
{
PROCESSOR_MN10300,
PROCESSOR_AM33,
PROCESSOR_AM33_2
......@@ -254,7 +260,8 @@ extern enum processor_type mn10300_processor;
For any two classes, it is very desirable that there be another
class that represents their union. */
enum reg_class {
enum reg_class
{
NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
......@@ -274,7 +281,8 @@ enum reg_class {
"DATA_OR_EXTENDED_REGS", "ADDRESS_OR_EXTENDED_REGS", \
"SP_OR_EXTENDED_REGS", "SP_OR_ADDRESS_OR_EXTENDED_REGS", \
"FP_REGS", "FP_ACC_REGS", "CC_REGS", \
"GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
"GENERAL_REGS", "ALL_REGS", "LIM_REGS" \
}
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
......@@ -414,11 +422,11 @@ enum reg_class {
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
((X) == stack_pointer_rtx && (CLASS) != SP_REGS \
? ADDRESS_OR_EXTENDED_REGS \
: (GET_CODE (X) == MEM \
|| (GET_CODE (X) == REG \
: (MEM_P (X) \
|| (REG_P (X) \
&& REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| (GET_CODE (X) == SUBREG \
&& GET_CODE (SUBREG_REG (X)) == REG \
&& REG_P (SUBREG_REG (X)) \
&& REGNO (SUBREG_REG (X)) >= FIRST_PSEUDO_REGISTER) \
? LIMIT_RELOAD_CLASS (GET_MODE (X), CLASS) \
: (CLASS)))
......@@ -483,7 +491,7 @@ enum reg_class {
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
OFFSET = initial_offset (FROM, TO)
OFFSET = mn10300_initial_offset (FROM, TO)
/* We can debug without frame pointers on the mn10300, so eliminate
them whenever possible. */
......@@ -494,11 +502,10 @@ enum reg_class {
#define REG_PARM_STACK_SPACE(DECL) 8
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
#define ACCUMULATE_OUTGOING_ARGS 1
#if 1
/* So we can allocate space for return pointers once for the function
instead of around every call. */
#define STACK_POINTER_OFFSET 4
#endif
/* 1 if N is a possible register number for function argument passing.
On the MN10300, d0 and d1 are used in this way. */
......@@ -516,7 +523,11 @@ enum reg_class {
of arguments scanned so far. */
#define CUMULATIVE_ARGS struct cum_arg
struct cum_arg {int nbytes; };
struct cum_arg
{
int nbytes;
};
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
......@@ -550,7 +561,7 @@ struct cum_arg {int nbytes; };
(otherwise it is an extra parameter matching an ellipsis). */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg (&CUM, MODE, TYPE, NAMED)
mn10300_function_arg (&(CUM), MODE, TYPE, NAMED)
#define FUNCTION_VALUE_REGNO_P(N) mn10300_function_value_regno_p (N)
......@@ -614,7 +625,8 @@ struct cum_arg {int nbytes; };
/* Zero if this needs fixing up to become PIC. */
#define LEGITIMATE_PIC_OPERAND_P(X) (legitimate_pic_operand_p (X))
#define LEGITIMATE_PIC_OPERAND_P(X) \
mn10300_legitimate_pic_operand_p (X)
/* Register to hold the addressing base for
position independent code access to data items. */
......@@ -740,11 +752,14 @@ struct cum_arg {int nbytes; };
/* This is how we tell the assembler that two symbols have the same value. */
#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
do { assemble_name(FILE, NAME1); \
fputs(" = ", FILE); \
assemble_name(FILE, NAME2); \
fputc('\n', FILE); } while (0)
do \
{ \
assemble_name (FILE, NAME1); \
fputs (" = ", FILE); \
assemble_name (FILE, NAME2); \
fputc ('\n', FILE); \
} \
while (0)
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
......@@ -774,12 +789,14 @@ struct cum_arg {int nbytes; };
/* Print an instruction operand X on file FILE.
look in mn10300.c for details */
#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE,X,CODE)
#define PRINT_OPERAND(FILE, X, CODE) \
mn10300_print_operand (FILE, X, CODE)
/* Print a memory operand whose address is X, on file FILE.
This uses a function in output-vax.c. */
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
mn10300_print_operand_address (FILE, ADDR)
/* This is how to output an element of a case-vector that is absolute. */
......@@ -821,12 +838,14 @@ struct cum_arg {int nbytes; };
#define DEBUGGER_AUTO_OFFSET(X) \
((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
+ (frame_pointer_needed \
? 0 : -initial_offset (FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM)))
? 0 : - mn10300_initial_offset (FRAME_POINTER_REGNUM, \
STACK_POINTER_REGNUM)))
#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
((GET_CODE (X) == PLUS ? OFFSET : 0) \
+ (frame_pointer_needed \
? 0 : -initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM)))
? 0 : - mn10300_initial_offset (ARG_POINTER_REGNUM, \
STACK_POINTER_REGNUM)))
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
......
gcc/config/mn10300/mn10300.md
......@@ -72,7 +72,7 @@
case 0:
return \"nop\";
case 1:
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
rtx xoperands[2];
xoperands[0] = operands[0];
......@@ -82,7 +82,7 @@
}
if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
&& GET_CODE (operands[1]) == CONST_INT)
&& CONST_INT_P (operands[1]))
{
HOST_WIDE_INT val = INTVAL (operands[1]);
......@@ -118,7 +118,7 @@
case 2:
case 3:
case 4:
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
rtx xoperands[2];
xoperands[0] = operands[0];
......@@ -164,7 +164,7 @@
case 0:
return \"nop\";
case 1:
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
rtx xoperands[2];
xoperands[0] = operands[0];
......@@ -174,7 +174,7 @@
}
if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
&& GET_CODE (operands[1]) == CONST_INT)
&& CONST_INT_P (operands[1]))
{
HOST_WIDE_INT val = INTVAL (operands[1]);
......@@ -210,7 +210,7 @@
case 2:
case 3:
case 4:
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
rtx xoperands[2];
xoperands[0] = operands[0];
......@@ -293,14 +293,14 @@
rtx temp;
if (SYMBOLIC_CONST_P (operands[1]))
{
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (Pmode, operands[1]);
else
{
temp = (!can_create_pseudo_p ()
? operands[0]
: gen_reg_rtx (Pmode));
operands[1] = legitimize_pic_address (operands[1], temp);
operands[1] = mn10300_legitimize_pic_address (operands[1], temp);
}
}
else if (GET_CODE (operands[1]) == CONST
......@@ -308,7 +308,7 @@
&& SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
{
temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
temp);
operands[1] = expand_binop (SImode, add_optab, temp,
XEXP (XEXP (operands[1], 0), 1),
......@@ -346,7 +346,7 @@
case 11:
case 12:
case 13:
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
rtx xoperands[2];
xoperands[0] = operands[0];
......@@ -356,7 +356,7 @@
}
if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
&& GET_CODE (operands[1]) == CONST_INT)
&& CONST_INT_P (operands[1]))
{
HOST_WIDE_INT val = INTVAL (operands[1]);
......@@ -410,7 +410,7 @@
case 7:
case 8:
if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
&& GET_CODE (operands[1]) == CONST_INT)
&& CONST_INT_P (operands[1]))
{
HOST_WIDE_INT val = INTVAL (operands[1]);
......@@ -471,14 +471,14 @@
case 9:
case 10:
case 11:
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
{
rtx low, high;
split_double (operands[1], &low, &high);
val[0] = INTVAL (low);
val[1] = INTVAL (high);
}
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
if (GET_MODE (operands[1]) == DFmode)
{
......@@ -493,7 +493,7 @@
}
}
if (GET_CODE (operands[1]) == MEM
if (MEM_P (operands[1])
&& reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
{
rtx temp = operands[0];
......@@ -501,7 +501,7 @@
while (GET_CODE (temp) == SUBREG)
temp = SUBREG_REG (temp);
gcc_assert (GET_CODE (temp) == REG);
gcc_assert (REG_P (temp));
if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
XEXP (operands[1], 0)))
......@@ -510,7 +510,7 @@
return \"mov %L1,%L0\;mov %H1,%H0\";
}
else if (GET_CODE (operands[1]) == MEM
else if (MEM_P (operands[1])
&& CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
&& REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
{
......@@ -525,8 +525,8 @@
}
else
{
if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[0] == 0)
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
......@@ -534,8 +534,8 @@
else
output_asm_insn (\"mov %L1,%L0\", operands);
}
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& (REGNO_REG_CLASS (true_regnum (operands[0]))
== EXTENDED_REGS)
&& (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
......@@ -544,8 +544,8 @@
else
output_asm_insn (\"mov %L1,%L0\", operands);
if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[1] == 0)
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
......@@ -553,12 +553,12 @@
else
output_asm_insn (\"mov %H1,%H0\", operands);
}
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[0] == val[1])
output_asm_insn (\"mov %L0,%H0\", operands);
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& (REGNO_REG_CLASS (true_regnum (operands[0]))
== EXTENDED_REGS)
&& (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
......@@ -575,15 +575,15 @@
case 15:
return \"fmov %L1, %L0\;fmov %H1, %H0\";
case 16:
if (GET_CODE (operands[1]) == MEM
&& GET_CODE (XEXP (operands[1], 0)) == CONST_INT
if (MEM_P (operands[1])
&& CONST_INT_P (XEXP (operands[1], 0))
&& (INTVAL (XEXP (operands[1], 0)) & 7) == 0)
return \"fmov %D1, %D0\";
else
return \"fmov %L1, %L0\;fmov %H1, %H0\";
case 17:
if (GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == CONST_INT
if (MEM_P (operands[0])
&& CONST_INT_P (XEXP (operands[0], 0))
&& (INTVAL (XEXP (operands[0], 0)) & 7) == 0)
return \"fmov %D1, %D0\";
else
......@@ -637,16 +637,16 @@
return \"fmov %L1, %L0\;fmov %H1, %H0\";
case 7:
if (GET_CODE (operands[1]) == MEM
&& GET_CODE (XEXP (operands[1], 0)) == CONST_INT
if (MEM_P (operands[1])
&& CONST_INT_P (XEXP (operands[1], 0))
&& (INTVAL (XEXP (operands[1], 0)) & 7) == 0)
return \"fmov %D1, %D0\";
else
return \"fmov %L1, %L0\;fmov %H1, %H0\";
case 8:
if (GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == CONST_INT
if (MEM_P (operands[0])
&& CONST_INT_P (XEXP (operands[0], 0))
&& (INTVAL (XEXP (operands[0], 0)) & 7) == 0)
return \"fmov %D1, %D0\";
else
......@@ -665,14 +665,14 @@
case 15:
case 16:
case 17:
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
{
rtx low, high;
split_double (operands[1], &low, &high);
val[0] = INTVAL (low);
val[1] = INTVAL (high);
}
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
if (GET_MODE (operands[1]) == DFmode)
{
......@@ -687,7 +687,7 @@
}
}
if (GET_CODE (operands[1]) == MEM
if (MEM_P (operands[1])
&& reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
{
rtx temp = operands[0];
......@@ -695,7 +695,7 @@
while (GET_CODE (temp) == SUBREG)
temp = SUBREG_REG (temp);
gcc_assert (GET_CODE (temp) == REG);
gcc_assert (REG_P (temp));
if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
XEXP (operands[1], 0)))
......@@ -704,7 +704,7 @@
return \"mov %L1,%L0\;mov %H1,%H0\";
}
else if (GET_CODE (operands[1]) == MEM
else if (MEM_P (operands[1])
&& CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
&& REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
{
......@@ -719,8 +719,8 @@
}
else
{
if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[0] == 0)
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
......@@ -728,8 +728,8 @@
else
output_asm_insn (\"mov %L1,%L0\", operands);
}
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& (REGNO_REG_CLASS (true_regnum (operands[0]))
== EXTENDED_REGS)
&& (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
......@@ -738,8 +738,8 @@
else
output_asm_insn (\"mov %L1,%L0\", operands);
if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[1] == 0)
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
......@@ -747,12 +747,12 @@
else
output_asm_insn (\"mov %H1,%H0\", operands);
}
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[0] == val[1])
output_asm_insn (\"mov %L0,%H0\", operands);
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& (REGNO_REG_CLASS (true_regnum (operands[0]))
== EXTENDED_REGS)
&& (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
......@@ -803,14 +803,14 @@
case 8:
case 9:
case 10:
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
{
rtx low, high;
split_double (operands[1], &low, &high);
val[0] = INTVAL (low);
val[1] = INTVAL (high);
}
if (GET_CODE (operands[1]) == CONST_DOUBLE)
if (CONST_DOUBLE_P (operands[1]))
{
if (GET_MODE (operands[1]) == DFmode)
{
......@@ -825,7 +825,7 @@
}
}
if (GET_CODE (operands[1]) == MEM
if (MEM_P (operands[1])
&& reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
{
rtx temp = operands[0];
......@@ -833,7 +833,7 @@
while (GET_CODE (temp) == SUBREG)
temp = SUBREG_REG (temp);
gcc_assert (GET_CODE (temp) == REG);
gcc_assert (REG_P (temp));
if (reg_overlap_mentioned_p (gen_rtx_REG (SImode, REGNO (temp)),
XEXP (operands[1], 0)))
......@@ -842,7 +842,7 @@
return \"mov %L1,%L0\;mov %H1,%H0\";
}
else if (GET_CODE (operands[1]) == MEM
else if (MEM_P (operands[1])
&& CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
&& REGNO_REG_CLASS (REGNO (operands[0])) == ADDRESS_REGS)
{
......@@ -857,8 +857,8 @@
}
else
{
if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[0] == 0)
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
......@@ -866,8 +866,8 @@
else
output_asm_insn (\"mov %L1,%L0\", operands);
}
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& (REGNO_REG_CLASS (true_regnum (operands[0]))
== EXTENDED_REGS)
&& (((val[0] & 0x80) && ! (val[0] & 0xffffff00))
......@@ -876,8 +876,8 @@
else
output_asm_insn (\"mov %L1,%L0\", operands);
if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[1] == 0)
{
if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
......@@ -885,12 +885,12 @@
else
output_asm_insn (\"mov %H1,%H0\", operands);
}
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& val[0] == val[1])
output_asm_insn (\"mov %L0,%H0\", operands);
else if ((GET_CODE (operands[1]) == CONST_INT
|| GET_CODE (operands[1]) == CONST_DOUBLE)
else if ((CONST_INT_P (operands[1])
|| CONST_DOUBLE_P (operands[1]))
&& (REGNO_REG_CLASS (true_regnum (operands[0]))
== EXTENDED_REGS)
&& (((val[1] & 0x80) && ! (val[1] & 0xffffff00))
......@@ -965,10 +965,11 @@
/* We have to copy one of the sources into the destination, then
add the other source to the destination.
Carefully select which source to copy to the destination; a naive
implementation will waste a byte when the source classes are
different and the destination is an address register. Selecting
the lowest cost register copy will optimize this sequence. */
Carefully select which source to copy to the destination; a
naive implementation will waste a byte when the source classes
are different and the destination is an address register.
Selecting the lowest cost register copy will optimize this
sequence. */
if (REGNO_REG_CLASS (true_regnum (operands[1]))
== REGNO_REG_CLASS (true_regnum (operands[0])))
return \"mov %1,%0\;add %2,%0\";
......@@ -1260,25 +1261,25 @@
"TARGET_AM33"
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xff)
return \"extbu %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xffff)
return \"exthu %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x7fffffff)
return \"add %0,%0\;lsr 1,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x3fffffff)
return \"asl2 %0\;lsr 2,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x1fffffff)
return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x0fffffff)
return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffe)
return \"lsr 1,%0\;add %0,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffc)
return \"lsr 2,%0\;asl2 %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff8)
return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff0)
return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
if (REG_P (operands[2]) && REG_P (operands[1])
&& true_regnum (operands[0]) != true_regnum (operands[1])
......@@ -1307,25 +1308,25 @@
""
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xff)
return \"extbu %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xffff)
return \"exthu %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x7fffffff)
return \"add %0,%0\;lsr 1,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x3fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x3fffffff)
return \"asl2 %0\;lsr 2,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x1fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x1fffffff)
return \"add %0,%0\;asl2 %0\;lsr 3,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x0fffffff)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0x0fffffff)
return \"asl2 %0\;asl2 %0\;lsr 4,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffe)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffe)
return \"lsr 1,%0\;add %0,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffffc)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffffc)
return \"lsr 2,%0\;asl2 %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff8)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff8)
return \"lsr 3,%0\;add %0,%0\;asl2 %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffffff0)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 0xfffffff0)
return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
return \"and %2,%0\";
}"
......@@ -1478,7 +1479,8 @@
[(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int 0))
(clobber (reg:CC CC_REG))
]
"GET_CODE (operands[0]) != MEM || (! MEM_VOLATILE_P (operands[0]) && GET_CODE (XEXP (operands[0], 0)) != PLUS)"
"(! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) != PLUS)"
"@
bclr 255,%A0
clr %0"
......@@ -1488,7 +1490,8 @@
[(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1))
(clobber (reg:CC CC_REG))
]
"GET_CODE (operands[0]) != MEM || (! MEM_VOLATILE_P (operands[0]) && GET_CODE (XEXP (operands[0], 0)) != PLUS)"
"( ! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) != PLUS)"
"@
bset 255,%A0
mov -1,%0"
......@@ -1554,7 +1557,7 @@
(clobber (reg:CC CC_REG))
]
"TARGET_AM33 &&
(GET_CODE (operands[2]) != MEM || GET_CODE (operands[1]) != MEM)"
((! MEM_P (operands[2])) || (! MEM_P (operands[1])))"
"@
bset %U2,%A0
bset %2,%0
......@@ -1571,7 +1574,7 @@
(match_operand:QI 2 "general_operand" "i,d,id")))
(clobber (reg:CC CC_REG))
]
"GET_CODE (operands[2]) != MEM || GET_CODE (operands[1]) != MEM"
"(! MEM_P (operands[2])) || (! MEM_P (operands[1]))"
"@
bset %U2,%A0
bset %2,%0
......@@ -1612,7 +1615,7 @@
(match_operand 1 "const_int_operand" "")
(match_operand 2 "const_int_operand" ""))
(const_int 0)))]
"mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
"mn10300_mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
"*
{
int len = INTVAL (operands[1]);
......@@ -1644,7 +1647,7 @@
xoperands[0] = operands[0];
xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
if (GET_CODE (operands[0]) == REG)
if (REG_P (operands[0]))
output_asm_insn (\"btst %1,%0\", xoperands);
else
output_asm_insn (\"btst %U1,%A0\", xoperands);
......@@ -1710,7 +1713,8 @@
attribute is not set correctly on the jump insn. */
emit_insn (gen_cmpsi (operands[0], operands[1]));
emit_jump_insn (gen_integer_conditional_branch (gen_rtx_fmt_ee (GET_CODE (operands[3]),
emit_jump_insn (gen_integer_conditional_branch
(gen_rtx_fmt_ee (GET_CODE (operands[3]),
CCmode,
gen_rtx_REG (CCmode, CC_REG),
const0_rtx),
......@@ -1786,7 +1790,8 @@
attribute is not set correctly on the jump insn. */
emit_insn (gen_am33_cmpsf (operands[0], operands[1]));
emit_jump_insn (gen_float_conditional_branch (gen_rtx_fmt_ee (GET_CODE (operands[3]),
emit_jump_insn (gen_float_conditional_branch
(gen_rtx_fmt_ee (GET_CODE (operands[3]),
CC_FLOATmode,
gen_rtx_REG (CC_FLOATmode, CC_REG),
const0_rtx),
......@@ -1804,7 +1809,8 @@
(define_insn "float_conditional_branch"
[(set (pc)
(if_then_else (match_operator 0 "comparison_operator" [(reg:CC_FLOAT CC_REG) (const_int 0)])
(if_then_else (match_operator 0 "comparison_operator"
[(reg:CC_FLOAT CC_REG) (const_int 0)])
(label_ref (match_operand 1 "" ""))
(pc)))]
"TARGET_AM33_2"
......@@ -2142,17 +2148,17 @@
"TARGET_AM33"
"*
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 1)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
return \"add %0,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 2)
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 2)
return \"asl2 %0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 3
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 3
&& REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
return \"asl2 %0\;add %0,%0\";
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 4
if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 4
&& REGNO_REG_CLASS (true_regnum (operands[0])) == DATA_REGS)
return \"asl2 %0\;asl2 %0\";
......@@ -2418,8 +2424,11 @@
)
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "register_operand")
(sqrt:SF (match_operand:SF 1 "register_operand")))]
[(parallel [(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "register_operand" "")))
(clobber (reg:CC_FLOAT CC_REG))
])
]
"TARGET_AM33_2 && flag_unsafe_math_optimizations"
"
{
......@@ -2455,7 +2464,7 @@
(define_insn "*addsf3_internal"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "register_operand" "%0,f")
(match_operand:SF 2 "general_operand" "f,?fF")))
(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
(clobber (reg:CC_FLOAT CC_REG))
]
"TARGET_AM33_2"
......@@ -2477,7 +2486,7 @@
(define_insn "*subsf3_internal"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,f")
(match_operand:SF 2 "general_operand" "f,?fF")))
(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
(clobber (reg:CC_FLOAT CC_REG))
]
"TARGET_AM33_2"
......@@ -2499,7 +2508,7 @@
(define_insn "*mulsf3_internal"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "register_operand" "%0,f")
(match_operand:SF 2 "general_operand" "f,?fF")))
(match_operand:SF 2 "nonmemory_operand" "f,?fF")))
(clobber (reg:CC_FLOAT CC_REG))
]
"TARGET_AM33_2"
......@@ -2570,14 +2579,14 @@
(define_expand "prologue"
[(const_int 0)]
""
"expand_prologue (); DONE;")
"mn10300_expand_prologue (); DONE;")
(define_expand "epilogue"
[(return)]
""
"
{
expand_epilogue ();
mn10300_expand_epilogue ();
DONE;
}")
......@@ -2606,14 +2615,15 @@
;; This instruction matches one generated by mn10300_gen_multiple_store()
(define_insn "store_movm"
[(match_parallel 0 "store_multiple_operation"
[(match_parallel 0 "mn10300_store_multiple_operation"
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])]
""
"*
{
fputs (\"\\tmovm \", asm_out_file);
mn10300_print_reg_list (asm_out_file,
store_multiple_operation (operands[0], VOIDmode));
mn10300_store_multiple_operation (operands[0],
VOIDmode));
fprintf (asm_out_file, \",(sp)\\n\");
return \"\";
}"
......@@ -2621,13 +2631,13 @@
(define_insn "return"
[(return)]
"can_use_return_insn ()"
"mn10300_can_use_return_insn ()"
"*
{
rtx next = next_active_insn (insn);
if (next
&& GET_CODE (next) == JUMP_INSN
&& JUMP_P (next)
&& GET_CODE (PATTERN (next)) == RETURN)
return \"\";
else
......
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