arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and gcc_unreachable as appropriate.

	* config/arm/arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and
	gcc_unreachable as appropriate.
	(THUMB_PRINT_OPERAND_ADDRESS): Likewise.
	* config/arm/arm.c (arm_override_options, arm_compute_func_type,
	use_return_insn, const_ok_for_op, arm_gen_constant,
	arm_canonicalize_comparison, legitimize_pic_address,
	thumb_find_work_register, arm_load_pic_register, arm_rtx_costs_1,
	arm_cirrus_insn_p, cirrus_reorg, minmax_code,
	load_multiple_sequence, emit_ldm_seq, store_multiple_sequence,
	emit_stm_seq, arm_gen_movmemqi, arm_select_dominance_cc_mode,
	arm_select_cc_mode, arm_reload_in_hi, arm_reload_out_hi,
	move_minipool_fix_forward_ref, move_minipool_fix_backward_ref,
	dump_minipool, create_fix_barrier, push_minipool_fix, arm_reorg,
	fp_immediate_constant, fp_const_from_val, vfp_output_fstmx,
	output_call, output_mov_long_double_fpa_from_arm,
	output_mov_long_double_arm_from_fpa,
	output_mov_double_fpa_from_arm, output_mov_double_arm_from_fpa,
	output_move_double, arithmetic_instr, shift_op, int_log2,
	output_return_instruction, arm_output_function_prologue,
	arm_output_epilogue, arm_output_function_epilogue,
	emit_multi_reg_push, arm_get_frame_offsets,
	arm_compute_initial_elimination_offset, arm_expand_prologue,
	arm_print_operand, arm_assemble_integer, get_arm_condition_code,
	arm_final_prescan_insn, arm_init_iwmmxt_builtins,
	arm_expand_binop_builtin, thumb_pushpop, thumb_far_jump_used_p,
	thumb_compute_initial_elimination_offset,
	thumb_output_function_prologue, thumb_load_double_from_address,
	thumb_output_move_mem_multiple, thumb_reload_out_hi,
	arm_emit_vector_const, arm_dbx_register_number): Likewise.
	* config/arm/pe.c (arm_mark_dllexport, arm_mark_dllimport): Likewise.
	* config/arm/arm.md (thumb_extendhisi2,
	*thumb_extendhisi2_insn_v6, *thumb_extendqisi2,
	*thumb_extendqisi2_v6, movhi, *thumb_movhi_insn,
	thumb_movhi_clobber, movqi, *arm_buneq, *arm_bltgt,
	*arm_buneq_reversed, *arm_bltgt_reversed, suneq, sltgt): Likewise.
	* config/arm/cirrus.md (*cirrus_arm_movdi,
	*cirrus_movdf_hard_insn): Likewise.
	* config/arm/vfp.md (*arm_movdi_vfp, *movdf_vfp): Likewise.

From-SVN: r98850

gcc/ChangeLog

+2005-04-27  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/arm/arm.h (ARM_PRINT_OPERAND_ADDRESS): Use gcc_assert and
+	gcc_unreachable as appropriate.
+	(THUMB_PRINT_OPERAND_ADDRESS): Likewise.
+	* config/arm/arm.c (arm_override_options, arm_compute_func_type,
+	use_return_insn, const_ok_for_op, arm_gen_constant,
+	arm_canonicalize_comparison, legitimize_pic_address,
+	thumb_find_work_register, arm_load_pic_register, arm_rtx_costs_1,
+	arm_cirrus_insn_p, cirrus_reorg, minmax_code,
+	load_multiple_sequence, emit_ldm_seq, store_multiple_sequence,
+	emit_stm_seq, arm_gen_movmemqi, arm_select_dominance_cc_mode,
+	arm_select_cc_mode, arm_reload_in_hi, arm_reload_out_hi,
+	move_minipool_fix_forward_ref, move_minipool_fix_backward_ref,
+	dump_minipool, create_fix_barrier, push_minipool_fix, arm_reorg,
+	fp_immediate_constant, fp_const_from_val, vfp_output_fstmx,
+	output_call, output_mov_long_double_fpa_from_arm,
+	output_mov_long_double_arm_from_fpa,
+	output_mov_double_fpa_from_arm, output_mov_double_arm_from_fpa,
+	output_move_double, arithmetic_instr, shift_op, int_log2,
+	output_return_instruction, arm_output_function_prologue,
+	arm_output_epilogue, arm_output_function_epilogue,
+	emit_multi_reg_push, arm_get_frame_offsets,
+	arm_compute_initial_elimination_offset, arm_expand_prologue,
+	arm_print_operand, arm_assemble_integer, get_arm_condition_code,
+	arm_final_prescan_insn, arm_init_iwmmxt_builtins,
+	arm_expand_binop_builtin, thumb_pushpop, thumb_far_jump_used_p,
+	thumb_compute_initial_elimination_offset,
+	thumb_output_function_prologue, thumb_load_double_from_address,
+	thumb_output_move_mem_multiple, thumb_reload_out_hi,
+	arm_emit_vector_const, arm_dbx_register_number): Likewise.
+	* config/arm/pe.c (arm_mark_dllexport, arm_mark_dllimport): Likewise.
+	* config/arm/arm.md (thumb_extendhisi2,
+	*thumb_extendhisi2_insn_v6, *thumb_extendqisi2,
+	*thumb_extendqisi2_v6, movhi, *thumb_movhi_insn,
+	thumb_movhi_clobber, movqi, *arm_buneq, *arm_bltgt,
+	*arm_buneq_reversed, *arm_bltgt_reversed, suneq, sltgt): Likewise.
+	* config/arm/cirrus.md (*cirrus_arm_movdi,
+	*cirrus_movdf_hard_insn): Likewise.
+	* config/arm/vfp.md (*arm_movdi_vfp, *movdf_vfp): Likewise.
+
 2005-04-27  Kazu Hirata  <kazu@cs.umass.edu>
 
 	* tree-flow.h (ssa_names): Change the type to VEC(tree,gc).

gcc/config/arm/arm.c

@@ -909,10 +909,8 @@ arm_override_options (void)
 		      }
 		  }
 
-	      if (best_fit == NULL)
-		abort ();
-	      else
-		sel = best_fit;
+	      gcc_assert (best_fit);
+	      sel = best_fit;
 	    }
 
 	  insn_flags = sel->flags;
@@ -924,8 +922,7 @@ arm_override_options (void)
 
   /* The processor for which we should tune should now have been
      chosen.  */
-  if (arm_tune == arm_none)
-    abort ();
+  gcc_assert (arm_tune != arm_none);
 
   tune_flags = all_cores[(int)arm_tune].flags;
   if (optimize_size)
@@ -1096,8 +1093,7 @@ arm_override_options (void)
       else
 	arm_fpu_tune = arm_fpu_arch;
       arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
-      if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
-	abort ();
+      gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
     }
 
   if (target_float_abi_name != NULL)
@@ -1288,8 +1284,7 @@ arm_compute_func_type (void)
   tree a;
   tree attr;
 
-  if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
-    abort ();
+  gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
 
   /* Decide if the current function is volatile.  Such functions
      never return, and many memory cycles can be saved by not storing
@@ -1402,8 +1397,7 @@ use_return_insn (int iscond, rtx sibling)
 	 argument ...  */
       if (sibling)
 	{
-	  if (GET_CODE (sibling) != CALL_INSN)
-	    abort ();
+	  gcc_assert (GET_CODE (sibling) == CALL_INSN);
 
 	  if (find_regno_fusage (sibling, USE, 3))
 	    return 0;
@@ -1512,7 +1506,7 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
       return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 }
 
@@ -1712,17 +1706,15 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
 				gen_rtx_SET (VOIDmode, target, source));
 	  return 1;
 	}
-      if (remainder == 0xffffffff)
-	{
-	  if (generate)
-	    emit_constant_insn (cond,
-				gen_rtx_SET (VOIDmode, target,
-					     gen_rtx_NOT (mode, source)));
-	  return 1;
-	}
-
-      /* We don't know how to handle this yet below.  */
-      abort ();
+      
+      /* We don't know how to handle other cases yet.  */
+      gcc_assert (remainder == 0xffffffff);
+      
+      if (generate)
+	emit_constant_insn (cond,
+			    gen_rtx_SET (VOIDmode, target,
+					 gen_rtx_NOT (mode, source)));
+      return 1;
 
     case MINUS:
       /* We treat MINUS as (val - source), since (source - val) is always
@@ -1749,7 +1741,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
       break;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 
   /* If we can do it in one insn get out quickly.  */
@@ -2294,7 +2286,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
       break;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 
   return code;
@@ -3034,10 +3026,8 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
 
       if (reg == 0)
 	{
-	  if (no_new_pseudos)
-	    abort ();
-	  else
-	    reg = gen_reg_rtx (Pmode);
+	  gcc_assert (!no_new_pseudos);
+	  reg = gen_reg_rtx (Pmode);
 
 	  subregs = 1;
 	}
@@ -3088,20 +3078,15 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
 
       if (reg == 0)
 	{
-	  if (no_new_pseudos)
-	    abort ();
-	  else
-	    reg = gen_reg_rtx (Pmode);
+	  gcc_assert (!no_new_pseudos);
+	  reg = gen_reg_rtx (Pmode);
 	}
 
-      if (GET_CODE (XEXP (orig, 0)) == PLUS)
-	{
-	  base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
-	  offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
-					   base == reg ? 0 : reg);
-	}
-      else
-	abort ();
+      gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
+      
+      base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
+      offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
+				       base == reg ? 0 : reg);
 
       if (GET_CODE (offset) == CONST_INT)
 	{
@@ -3109,10 +3094,8 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
 	     test the index for the appropriate mode.  */
 	  if (!arm_legitimate_index_p (mode, offset, SET, 0))
 	    {
-	      if (!no_new_pseudos)
-		offset = force_reg (Pmode, offset);
-	      else
-		abort ();
+	      gcc_assert (no_new_pseudos);
+	      offset = force_reg (Pmode, offset);
 	    }
 
 	  if (GET_CODE (offset) == CONST_INT)
@@ -3185,7 +3168,7 @@ thumb_find_work_register (unsigned long pushed_regs_mask)
 
   /* Something went wrong - thumb_compute_save_reg_mask()
      should have arranged for a suitable register to be pushed.  */
-  abort ();
+  gcc_unreachable ();
 }
 
 
@@ -3202,8 +3185,7 @@ arm_load_pic_register (unsigned int scratch)
   if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
     return;
 
-  if (!flag_pic)
-    abort ();
+  gcc_assert (flag_pic);
 
   l1 = gen_label_rtx ();
 
@@ -4017,7 +3999,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
 
     case MULT:
       /* This should have been handled by the CPU specific routines.  */
-      abort ();
+      gcc_unreachable ();
 
     case TRUNCATE:
       if (arm_arch3m && mode == SImode
@@ -4078,9 +4060,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
 	    return 1;
 
 	default:
-	  break;
+	  gcc_unreachable ();
 	}
-      abort ();
+      gcc_unreachable ();
 
     case CONST_INT:
       if (const_ok_for_arm (INTVAL (x)))
@@ -4978,7 +4960,7 @@ arm_cirrus_insn_p (rtx insn)
 {
   enum attr_cirrus attr;
 
-  /* get_attr aborts on USE and CLOBBER.  */
+  /* get_attr cannot accept USE or CLOBBER.  */
   if (!insn
       || GET_CODE (insn) != INSN
       || GET_CODE (PATTERN (insn)) == USE
@@ -5050,10 +5032,11 @@ cirrus_reorg (rtx first)
 	  /* Get Arm register number for ldr insn.  */
 	  if (GET_CODE (lhs) == REG)
 	    arm_regno = REGNO (lhs);
-	  else if (GET_CODE (rhs) == REG)
-	    arm_regno = REGNO (rhs);
 	  else
-	    abort ();
+	    {
+	      gcc_assert (GET_CODE (rhs) == REG);
+	      arm_regno = REGNO (rhs);
+	    }
 
 	  /* Next insn.  */
 	  first = next_nonnote_insn (first);
@@ -5079,7 +5062,7 @@ cirrus_reorg (rtx first)
 	}
     }
 
-  /* get_attr aborts on USE and CLOBBER.  */
+  /* get_attr cannot accept USE or CLOBBER.  */
   if (!first
       || GET_CODE (first) != INSN
       || GET_CODE (PATTERN (first)) == USE
@@ -5171,16 +5154,19 @@ minmax_code (rtx x)
 {
   enum rtx_code code = GET_CODE (x);
 
-  if (code == SMAX)
-    return GE;
-  else if (code == SMIN)
-    return LE;
-  else if (code == UMIN)
-    return LEU;
-  else if (code == UMAX)
-    return GEU;
-
-  abort ();
+  switch (code)
+    {
+    case SMAX:
+      return GE;
+    case SMIN:
+      return LE;
+    case UMIN:
+      return LEU;
+    case UMAX:
+      return GEU;
+    default:
+      gcc_unreachable ();
+    }
 }
 
 /* Return 1 if memory locations are adjacent.  */
@@ -5260,8 +5246,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
 
   /* Can only handle 2, 3, or 4 insns at present,
      though could be easily extended if required.  */
-  if (nops < 2 || nops > 4)
-    abort ();
+  gcc_assert (nops >= 2 && nops <= 4);
 
   /* Loop over the operands and check that the memory references are
      suitable (i.e. immediate offsets from the same base register).  At
@@ -5276,8 +5261,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
       if (GET_CODE (operands[nops + i]) == SUBREG)
 	operands[nops + i] = alter_subreg (operands + (nops + i));
 
-      if (GET_CODE (operands[nops + i]) != MEM)
-	abort ();
+      gcc_assert (GET_CODE (operands[nops + i]) == MEM);
 
       /* Don't reorder volatile memory references; it doesn't seem worth
 	 looking for the case where the order is ok anyway.  */
@@ -5461,7 +5445,7 @@ emit_ldm_seq (rtx *operands, int nops)
       break;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 
   sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
@@ -5489,8 +5473,7 @@ store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
 
   /* Can only handle 2, 3, or 4 insns at present, though could be easily
      extended if required.  */
-  if (nops < 2 || nops > 4)
-    abort ();
+  gcc_assert (nops >= 2 && nops <= 4);
 
   /* Loop over the operands and check that the memory references are
      suitable (i.e. immediate offsets from the same base register).  At
@@ -5505,8 +5488,7 @@ store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
       if (GET_CODE (operands[nops + i]) == SUBREG)
 	operands[nops + i] = alter_subreg (operands + (nops + i));
 
-      if (GET_CODE (operands[nops + i]) != MEM)
-	abort ();
+      gcc_assert (GET_CODE (operands[nops + i]) == MEM);
 
       /* Don't reorder volatile memory references; it doesn't seem worth
 	 looking for the case where the order is ok anyway.  */
@@ -5638,7 +5620,7 @@ emit_stm_seq (rtx *operands, int nops)
       break;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 
   sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
@@ -5889,21 +5871,18 @@ arm_gen_movmemqi (rtx *operands)
       emit_move_insn (mem, sreg);
       in_words_to_go--;
 
-      if (in_words_to_go)	/* Sanity check */
-	abort ();
+      gcc_assert (!in_words_to_go);	/* Sanity check */
     }
 
   if (in_words_to_go)
     {
-      if (in_words_to_go < 0)
-	abort ();
+      gcc_assert (in_words_to_go > 0);
 
       mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
       part_bytes_reg = copy_to_mode_reg (SImode, mem);
     }
 
-  if (last_bytes && part_bytes_reg == NULL)
-    abort ();
+  gcc_assert (!last_bytes || part_bytes_reg);
 
   if (BYTES_BIG_ENDIAN && last_bytes)
     {
@@ -6032,78 +6011,108 @@ arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
   switch (cond1)
     {
     case EQ:
-      if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
+      if (cond_or == DOM_CC_X_AND_Y)
 	return CC_DEQmode;
 
       switch (cond2)
 	{
+	case EQ: return CC_DEQmode;
 	case LE: return CC_DLEmode;
 	case LEU: return CC_DLEUmode;
 	case GE: return CC_DGEmode;
 	case GEU: return CC_DGEUmode;
-	default: break;
+	default: gcc_unreachable ();
 	}
 
-      break;
-
     case LT:
-      if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
+      if (cond_or == DOM_CC_X_AND_Y)
 	return CC_DLTmode;
-      if (cond2 == LE)
-	return CC_DLEmode;
-      if (cond2 == NE)
-	return CC_DNEmode;
-      break;
+      
+      switch (cond2)
+	{
+	case  LT:
+	    return CC_DLTmode;
+	case LE:
+	  return CC_DLEmode;
+	case NE:
+	  return CC_DNEmode;
+	default:
+	  gcc_unreachable ();
+	}
 
     case GT:
-      if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
+      if (cond_or == DOM_CC_X_AND_Y)
 	return CC_DGTmode;
-      if (cond2 == GE)
-	return CC_DGEmode;
-      if (cond2 == NE)
-	return CC_DNEmode;
-      break;
+
+      switch (cond2)
+	{
+	case GT:
+	  return CC_DGTmode;
+	case GE:
+	  return CC_DGEmode;
+	case NE:
+	  return CC_DNEmode;
+	default:
+	  gcc_unreachable ();
+	}
 
     case LTU:
-      if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
+      if (cond_or == DOM_CC_X_AND_Y)
 	return CC_DLTUmode;
-      if (cond2 == LEU)
-	return CC_DLEUmode;
-      if (cond2 == NE)
-	return CC_DNEmode;
-      break;
+
+      switch (cond2)
+	{
+	case LTU:
+	  return CC_DLTUmode;
+	case LEU:
+	  return CC_DLEUmode;
+	case NE:
+	  return CC_DNEmode;
+	default:
+	  gcc_unreachable ();
+	}
 
     case GTU:
-      if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
+      if (cond_or == DOM_CC_X_AND_Y)
 	return CC_DGTUmode;
-      if (cond2 == GEU)
-	return CC_DGEUmode;
-      if (cond2 == NE)
-	return CC_DNEmode;
-      break;
+      
+      switch (cond2)
+	{
+	case GTU:
+	  return CC_DGTUmode;
+	case GEU:
+	  return CC_DGEUmode;
+	case NE:
+	  return CC_DNEmode;
+	default:
+	  gcc_unreachable ();
+	}
 
     /* The remaining cases only occur when both comparisons are the
        same.  */
     case NE:
+      gcc_assert (cond1 == cond2);
       return CC_DNEmode;
 
     case LE:
+      gcc_assert (cond1 == cond2);
       return CC_DLEmode;
 
     case GE:
+      gcc_assert (cond1 == cond2);
       return CC_DGEmode;
 
     case LEU:
+      gcc_assert (cond1 == cond2);
       return CC_DLEUmode;
 
     case GEU:
+      gcc_assert (cond1 == cond2);
       return CC_DGEUmode;
 
     default:
-      break;
+      gcc_unreachable ();
     }
-
-  abort ();
 }
 
 enum machine_mode
@@ -6136,7 +6145,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
 	  return CCFPEmode;
 
 	default:
-	  abort ();
+	  gcc_unreachable ();
 	}
     }
 
@@ -6323,8 +6332,7 @@ arm_reload_in_hi (rtx *operands)
 	     ^ (HOST_WIDE_INT) 0x80000000)
 	    - (HOST_WIDE_INT) 0x80000000);
 
-      if (hi + lo != offset)
-	abort ();
+      gcc_assert (hi + lo == offset);
 
       if (hi != 0)
 	{
@@ -6470,8 +6478,7 @@ arm_reload_out_hi (rtx *operands)
 	     ^ (HOST_WIDE_INT) 0x80000000)
 	    - (HOST_WIDE_INT) 0x80000000);
 
-      if (hi + lo != offset)
-	abort ();
+      gcc_assert (hi + lo == offset);
 
       if (hi != 0)
 	{
@@ -6821,10 +6828,8 @@ static Mnode *
 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
 			       HOST_WIDE_INT max_address)
 {
-  /* This should never be true and the code below assumes these are
-     different.  */
-  if (mp == max_mp)
-    abort ();
+  /* The code below assumes these are different.  */
+  gcc_assert (mp != max_mp);
 
   if (max_mp == NULL)
     {
@@ -6996,10 +7001,8 @@ move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
 {
   HOST_WIDE_INT offset;
 
-  /* This should never be true, and the code below assumes these are
-     different.  */
-  if (mp == min_mp)
-    abort ();
+  /* The code below assumes these are different.  */
+  gcc_assert (mp != min_mp);
 
   if (min_mp == NULL)
     {
@@ -7279,8 +7282,7 @@ dump_minipool (rtx scan)
 
 #endif
 	    default:
-	      abort ();
-	      break;
+	      gcc_unreachable ();
 	    }
 	}
 
@@ -7352,8 +7354,7 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
 
       /* This code shouldn't have been called if there was a natural barrier
 	 within range.  */
-      if (GET_CODE (from) == BARRIER)
-	abort ();
+      gcc_assert (GET_CODE (from) != BARRIER);
 
       /* Count the length of this insn.  */
       count += get_attr_length (from);
@@ -7458,10 +7459,9 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
   fix->minipool = NULL;
 
   /* If an insn doesn't have a range defined for it, then it isn't
-     expecting to be reworked by this code.  Better to abort now than
+     expecting to be reworked by this code.  Better to stop now than
      to generate duff assembly code.  */
-  if (fix->forwards == 0 && fix->backwards == 0)
-    abort ();
+  gcc_assert (fix->forwards || fix->backwards);
 
   /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
      So there might be an empty word before the start of the pool.
@@ -7644,8 +7644,7 @@ arm_reorg (void)
   /* The first insn must always be a note, or the code below won't
      scan it properly.  */
   insn = get_insns ();
-  if (GET_CODE (insn) != NOTE)
-    abort ();
+  gcc_assert (GET_CODE (insn) == NOTE);
 
   /* Scan all the insns and record the operands that will need fixing.  */
   for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
@@ -7739,8 +7738,7 @@ arm_reorg (void)
 	  /* The last item on the list of fixes must be a barrier, so
 	     we can never run off the end of the list of fixes without
 	     last_barrier being set.  */
-	  if (ftmp == NULL)
-	    abort ();
+	  gcc_assert (ftmp);
 
 	  max_address = minipool_vector_head->max_address;
 	  /* Check that there isn't another fix that is in range that
@@ -7810,7 +7808,7 @@ fp_immediate_constant (rtx x)
     if (REAL_VALUES_EQUAL (r, values_fp[i]))
       return strings_fp[i];
 
-  abort ();
+  gcc_unreachable ();
 }
 
 /* As for fp_immediate_constant, but value is passed directly, not in rtx.  */
@@ -7826,7 +7824,7 @@ fp_const_from_val (REAL_VALUE_TYPE *r)
     if (REAL_VALUES_EQUAL (*r, values_fp[i]))
       return strings_fp[i];
 
-  abort ();
+  gcc_unreachable ();
 }
 
 /* Output the operands of a LDM/STM instruction to STREAM.
@@ -7904,8 +7902,7 @@ vfp_output_fstmx (rtx * operands)
   strcpy (pattern, "fstmfdx\t%m0!, {%P1");
   p = strlen (pattern);
 
-  if (GET_CODE (operands[1]) != REG)
-    abort ();
+  gcc_assert (GET_CODE (operands[1]) == REG);
 
   base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
   for (i = 1; i < XVECLEN (operands[2], 0); i++)
@@ -7999,8 +7996,7 @@ vfp_emit_fstmx (int base_reg, int count)
 const char *
 output_call (rtx *operands)
 {
-  if (arm_arch5)
-    abort ();		/* Patterns should call blx <reg> directly.  */
+  gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly.  */
 
   /* Handle calls to lr using ip (which may be clobbered in subr anyway).  */
   if (REGNO (operands[0]) == LR_REGNUM)
@@ -8065,8 +8061,7 @@ output_mov_long_double_fpa_from_arm (rtx *operands)
   int arm_reg0 = REGNO (operands[1]);
   rtx ops[3];
 
-  if (arm_reg0 == IP_REGNUM)
-    abort ();
+  gcc_assert (arm_reg0 != IP_REGNUM);
 
   ops[0] = gen_rtx_REG (SImode, arm_reg0);
   ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
@@ -8087,8 +8082,7 @@ output_mov_long_double_arm_from_fpa (rtx *operands)
   int arm_reg0 = REGNO (operands[0]);
   rtx ops[3];
 
-  if (arm_reg0 == IP_REGNUM)
-    abort ();
+  gcc_assert (arm_reg0 != IP_REGNUM);
 
   ops[0] = gen_rtx_REG (SImode, arm_reg0);
   ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
@@ -8143,8 +8137,7 @@ output_mov_double_fpa_from_arm (rtx *operands)
   int arm_reg0 = REGNO (operands[1]);
   rtx ops[2];
 
-  if (arm_reg0 == IP_REGNUM)
-    abort ();
+  gcc_assert (arm_reg0 != IP_REGNUM);
 
   ops[0] = gen_rtx_REG (SImode, arm_reg0);
   ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
@@ -8162,8 +8155,7 @@ output_mov_double_arm_from_fpa (rtx *operands)
   int arm_reg0 = REGNO (operands[0]);
   rtx ops[2];
 
-  if (arm_reg0 == IP_REGNUM)
-    abort ();
+  gcc_assert (arm_reg0 != IP_REGNUM);
 
   ops[0] = gen_rtx_REG (SImode, arm_reg0);
   ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
@@ -8188,160 +8180,152 @@ output_move_double (rtx *operands)
 
       otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
 
-      if (code1 == MEM)
+      gcc_assert (code1 == MEM);  /* Constraints should ensure this.  */
+
+      switch (GET_CODE (XEXP (operands[1], 0)))
 	{
-	  switch (GET_CODE (XEXP (operands[1], 0)))
+	case REG:
+	  output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
+	  break;
+	  
+	case PRE_INC:
+	  gcc_assert (TARGET_LDRD);
+	  output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
+	  break;
+	  
+	case PRE_DEC:
+	  output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
+	  break;
+	  
+	case POST_INC:
+	  output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
+	  break;
+	  
+	case POST_DEC:
+	  gcc_assert (TARGET_LDRD);
+	  output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
+	  break;
+	  
+	case PRE_MODIFY:
+	case POST_MODIFY:
+	  otherops[0] = operands[0];
+	  otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
+	  otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
+	  
+	  if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
 	    {
-	    case REG:
-	      output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
-	      break;
-
-  	    case PRE_INC:
-	      if (!TARGET_LDRD)
-		abort (); /* Should never happen now.  */
-	      output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
-	      break;
-
-	    case PRE_DEC:
-	      output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
-	      break;
-
-	    case POST_INC:
-	      output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
-	      break;
-
-	    case POST_DEC:
-	      if (!TARGET_LDRD)
-		abort (); /* Should never happen now.  */
-	      output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
-	      break;
-
-	    case PRE_MODIFY:
-	    case POST_MODIFY:
-	      otherops[0] = operands[0];
-	      otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
-	      otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
-
-	      if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
+	      if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
 		{
-		  if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
-		    {
-		      /* Registers overlap so split out the increment.  */
-		      output_asm_insn ("add%?\t%1, %1, %2", otherops);
-		      output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
-		    }
-		  else
-		    output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
+		  /* Registers overlap so split out the increment.  */
+		  output_asm_insn ("add%?\t%1, %1, %2", otherops);
+		  output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
 		}
 	      else
+		output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
+	    }
+	  else
+	    {
+	      /* We only allow constant increments, so this is safe.  */
+	      output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
+	    }
+	  break;
+	  
+	case LABEL_REF:
+	case CONST:
+	  output_asm_insn ("adr%?\t%0, %1", operands);
+	  output_asm_insn ("ldm%?ia\t%0, %M0", operands);
+	  break;
+	  
+	default:
+	  if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
+			       GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
+	    {
+	      otherops[0] = operands[0];
+	      otherops[1] = XEXP (XEXP (operands[1], 0), 0);
+	      otherops[2] = XEXP (XEXP (operands[1], 0), 1);
+	      
+	      if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
 		{
-		  /* We only allow constant increments, so this is safe.  */
-		  output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
-		}
-	      break;
-
-	    case LABEL_REF:
-	    case CONST:
-	      output_asm_insn ("adr%?\t%0, %1", operands);
-	      output_asm_insn ("ldm%?ia\t%0, %M0", operands);
-	      break;
-
-	    default:
-	      if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
-				   GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
-		{
-		  otherops[0] = operands[0];
-		  otherops[1] = XEXP (XEXP (operands[1], 0), 0);
-		  otherops[2] = XEXP (XEXP (operands[1], 0), 1);
-
-		  if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
+		  if (GET_CODE (otherops[2]) == CONST_INT)
 		    {
-		      if (GET_CODE (otherops[2]) == CONST_INT)
+		      switch ((int) INTVAL (otherops[2]))
 			{
-			  switch ((int) INTVAL (otherops[2]))
-			    {
-			    case -8:
-			      output_asm_insn ("ldm%?db\t%1, %M0", otherops);
-			      return "";
-			    case -4:
-			      output_asm_insn ("ldm%?da\t%1, %M0", otherops);
-			      return "";
-			    case 4:
-			      output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
-			      return "";
-			    }
+			case -8:
+			  output_asm_insn ("ldm%?db\t%1, %M0", otherops);
+			  return "";
+			case -4:
+			  output_asm_insn ("ldm%?da\t%1, %M0", otherops);
+			  return "";
+			case 4:
+			  output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
+			  return "";
 			}
-		      if (TARGET_LDRD
-			  && (GET_CODE (otherops[2]) == REG
-			      || (GET_CODE (otherops[2]) == CONST_INT
-				  && INTVAL (otherops[2]) > -256
-				  && INTVAL (otherops[2]) < 256)))
+		    }
+		  if (TARGET_LDRD
+		      && (GET_CODE (otherops[2]) == REG
+			  || (GET_CODE (otherops[2]) == CONST_INT
+			      && INTVAL (otherops[2]) > -256
+			      && INTVAL (otherops[2]) < 256)))
+		    {
+		      if (reg_overlap_mentioned_p (otherops[0],
+						   otherops[2]))
 			{
-			  if (reg_overlap_mentioned_p (otherops[0],
-						       otherops[2]))
-			    {
-			      /* Swap base and index registers over to
-				 avoid a conflict.  */
-			      otherops[1] = XEXP (XEXP (operands[1], 0), 1);
-			      otherops[2] = XEXP (XEXP (operands[1], 0), 0);
-
-			    }
-			  /* If both registers conflict, it will usually
-			     have been fixed by a splitter.  */
-			  if (reg_overlap_mentioned_p (otherops[0],
-							otherops[2]))
-			    {
-			      output_asm_insn ("add%?\t%1, %1, %2", otherops);
-			      output_asm_insn ("ldr%?d\t%0, [%1]",
-					       otherops);
-			      return "";
-			    }
-			  else
-			    {
-			      output_asm_insn ("ldr%?d\t%0, [%1, %2]",
-					       otherops);
-			      return "";
-			    }
+			  /* Swap base and index registers over to
+			     avoid a conflict.  */
+			  otherops[1] = XEXP (XEXP (operands[1], 0), 1);
+			  otherops[2] = XEXP (XEXP (operands[1], 0), 0);
+			  
 			}
-		      if (GET_CODE (otherops[2]) == CONST_INT)
+		      /* If both registers conflict, it will usually
+			 have been fixed by a splitter.  */
+		      if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
 			{
-			  if (!(const_ok_for_arm (INTVAL (otherops[2]))))
-			    output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
-			  else
-			    output_asm_insn ("add%?\t%0, %1, %2", otherops);
+			  output_asm_insn ("add%?\t%1, %1, %2", otherops);
+			  output_asm_insn ("ldr%?d\t%0, [%1]",
+					   otherops);
 			}
 		      else
-			output_asm_insn ("add%?\t%0, %1, %2", otherops);
+			output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
+		      return "";
 		    }
-		  else
-		    output_asm_insn ("sub%?\t%0, %1, %2", otherops);
-
-		  return "ldm%?ia\t%0, %M0";
-                }
-              else
-                {
-		  otherops[1] = adjust_address (operands[1], SImode, 4);
-		  /* Take care of overlapping base/data reg.  */
-		  if (reg_mentioned_p (operands[0], operands[1]))
+		  
+		  if (GET_CODE (otherops[2]) == CONST_INT)
 		    {
-		      output_asm_insn ("ldr%?\t%0, %1", otherops);
-		      output_asm_insn ("ldr%?\t%0, %1", operands);
+		      if (!(const_ok_for_arm (INTVAL (otherops[2]))))
+			output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
+		      else
+			output_asm_insn ("add%?\t%0, %1, %2", otherops);
 		    }
 		  else
-		    {
-		      output_asm_insn ("ldr%?\t%0, %1", operands);
-		      output_asm_insn ("ldr%?\t%0, %1", otherops);
-		    }
+		    output_asm_insn ("add%?\t%0, %1, %2", otherops);
+		}
+	      else
+		output_asm_insn ("sub%?\t%0, %1, %2", otherops);
+
+	      return "ldm%?ia\t%0, %M0";
+	    }
+	  else
+	    {
+	      otherops[1] = adjust_address (operands[1], SImode, 4);
+	      /* Take care of overlapping base/data reg.  */
+	      if (reg_mentioned_p (operands[0], operands[1]))
+		{
+		  output_asm_insn ("ldr%?\t%0, %1", otherops);
+		  output_asm_insn ("ldr%?\t%0, %1", operands);
+		}
+	      else
+		{
+		  output_asm_insn ("ldr%?\t%0, %1", operands);
+		  output_asm_insn ("ldr%?\t%0, %1", otherops);
 		}
 	    }
 	}
-      else
-	abort ();  /* Constraints should prevent this.  */
     }
-  else if (code0 == MEM && code1 == REG)
+  else
     {
-      if (REGNO (operands[1]) == IP_REGNUM)
-	abort ();
+      /* Constraints should ensure this.  */
+      gcc_assert (code0 == MEM && code1 == REG);
+      gcc_assert (REGNO (operands[1]) != IP_REGNUM);
 
       switch (GET_CODE (XEXP (operands[0], 0)))
         {
@@ -8350,8 +8334,7 @@ output_move_double (rtx *operands)
 	  break;
 
         case PRE_INC:
-	  if (!TARGET_LDRD)
-	    abort (); /* Should never happen now.  */
+	  gcc_assert (TARGET_LDRD);
 	  output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
 	  break;
 
@@ -8364,8 +8347,7 @@ output_move_double (rtx *operands)
 	  break;
 
         case POST_DEC:
-	  if (!TARGET_LDRD)
-	    abort (); /* Should never happen now.  */
+	  gcc_assert (TARGET_LDRD);
 	  output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
 	  break;
 
@@ -8420,9 +8402,6 @@ output_move_double (rtx *operands)
 	  output_asm_insn ("str%?\t%1, %0", otherops);
 	}
     }
-  else
-    /* Constraints should prevent this.  */
-    abort ();
 
   return "";
 }
@@ -8515,7 +8494,7 @@ arithmetic_instr (rtx op, int shift_first_arg)
       return "and";
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 }
 
@@ -8530,12 +8509,20 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
   const char * mnem;
   enum rtx_code code = GET_CODE (op);
 
-  if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
-    *amountp = -1;
-  else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
-    *amountp = INTVAL (XEXP (op, 1));
-  else
-    abort ();
+  switch (GET_CODE (XEXP (op, 1)))
+    {
+    case REG:
+    case SUBREG:
+      *amountp = -1;
+      break;
+
+    case CONST_INT:
+      *amountp = INTVAL (XEXP (op, 1));
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
 
   switch (code)
     {
@@ -8552,8 +8539,7 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
       break;
 
     case ROTATE:
-      if (*amountp == -1)
-	abort ();
+      gcc_assert (*amountp != -1);
       *amountp = 32 - *amountp;
 
       /* Fall through.  */
@@ -8565,14 +8551,12 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
     case MULT:
       /* We never have to worry about the amount being other than a
 	 power of 2, since this case can never be reloaded from a reg.  */
-      if (*amountp != -1)
-	*amountp = int_log2 (*amountp);
-      else
-	abort ();
+      gcc_assert (*amountp != -1);
+      *amountp = int_log2 (*amountp);
       return "asl";
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 
   if (*amountp != -1)
@@ -8611,8 +8595,7 @@ int_log2 (HOST_WIDE_INT power)
 
   while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
     {
-      if (shift > 31)
-	abort ();
+      gcc_assert (shift <= 31);
       shift++;
     }
 
@@ -8955,8 +8938,7 @@ output_return_instruction (rtx operand, int really_return, int reverse)
       return "";
     }
 
-  if (current_function_calls_alloca && !really_return)
-    abort ();
+  gcc_assert (!current_function_calls_alloca || really_return);
 
   sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
 
@@ -8991,11 +8973,7 @@ output_return_instruction (rtx operand, int really_return, int reverse)
 	      live_regs_mask |=   (1 << SP_REGNUM);
 	    }
 	  else
-	    {
-	      if (! IS_INTERRUPT (func_type)
-		  && ! TARGET_REALLY_IWMMXT)
-		abort ();
-	    }
+	    gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
 	}
 
       /* On some ARM architectures it is faster to use LDR rather than
@@ -9030,8 +9008,7 @@ output_return_instruction (rtx operand, int really_return, int reverse)
 
 	      offsets = arm_get_frame_offsets ();
 	      stack_adjust = offsets->outgoing_args - offsets->saved_regs;
-	      if (stack_adjust != 0 && stack_adjust != 4)
-		abort ();
+	      gcc_assert (stack_adjust == 0 || stack_adjust == 4);
 
 	      if (stack_adjust && arm_arch5)
 		sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
@@ -9180,8 +9157,7 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
     }
 
   /* Sanity check.  */
-  if (arm_ccfsm_state || arm_target_insn)
-    abort ();
+  gcc_assert (!arm_ccfsm_state && !arm_target_insn);
 
   func_type = arm_current_func_type ();
 
@@ -9274,11 +9250,9 @@ arm_output_epilogue (rtx sibling)
       return "";
     }
 
-  if (current_function_calls_eh_return
-      && ! really_return)
-    /* If we are throwing an exception, then we really must
-       be doing a return,  so we can't tail-call.  */
-    abort ();
+  /* If we are throwing an exception, then we really must be doing a
+     return, so we can't tail-call.  */
+  gcc_assert (!current_function_calls_eh_return || really_return);
 
   offsets = arm_get_frame_offsets ();
   saved_regs_mask = arm_compute_save_reg_mask ();
@@ -9399,8 +9373,7 @@ arm_output_epilogue (rtx sibling)
 	 frame generation actually contains the old stack pointer.  So a
 	 quick way to unwind the stack is just pop the IP register directly
 	 into the stack pointer.  */
-      if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
-	abort ();
+      gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
       saved_regs_mask &= ~ (1 << IP_REGNUM);
       saved_regs_mask |=   (1 << SP_REGNUM);
 
@@ -9620,11 +9593,10 @@ arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
       /* We need to take into account any stack-frame rounding.  */
       offsets = arm_get_frame_offsets ();
 
-      if (use_return_insn (FALSE, NULL)
-	  && return_used_this_function
-	  && offsets->saved_regs != offsets->outgoing_args
-	  && !frame_pointer_needed)
-	abort ();
+      gcc_assert (!use_return_insn (FALSE, NULL)
+		  || !return_used_this_function
+		  || offsets->saved_regs == offsets->outgoing_args
+		  || frame_pointer_needed);
 
       /* Reset the ARM-specific per-function variables.  */
       after_arm_reorg = 0;
@@ -9650,8 +9622,7 @@ emit_multi_reg_push (unsigned long mask)
     if (mask & (1 << i))
       num_regs++;
 
-  if (num_regs == 0 || num_regs > 16)
-    abort ();
+  gcc_assert (num_regs && num_regs <= 16);
 
   /* We don't record the PC in the dwarf frame information.  */
   num_dwarf_regs = num_regs;
@@ -9978,8 +9949,7 @@ arm_get_frame_offsets (void)
       /* Ensure SP remains doubleword aligned.  */
       if (offsets->outgoing_args & 7)
 	offsets->outgoing_args += 4;
-      if (offsets->outgoing_args & 7)
-	abort ();
+      gcc_assert (!(offsets->outgoing_args & 7));
     }
 
   return offsets;
@@ -10029,9 +9999,9 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
 	  return offsets->outgoing_args - (offsets->saved_args + 4);
 
 	default:
-	  abort ();
+	  gcc_unreachable ();
 	}
-      break;
+      gcc_unreachable ();
 
     case FRAME_POINTER_REGNUM:
       switch (to)
@@ -10051,9 +10021,9 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
 	  return offsets->outgoing_args - offsets->soft_frame;
 
 	default:
-	  abort ();
+	  gcc_unreachable ();
 	}
-      break;
+      gcc_unreachable ();
 
     default:
       /* You cannot eliminate from the stack pointer.
@@ -10061,7 +10031,7 @@ arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
 	 pointer to the stack pointer, but this will never
 	 happen, since if a stack frame is not needed the
 	 hard frame pointer will never be used.  */
-      abort ();
+      gcc_unreachable ();
     }
 }
 
@@ -10110,7 +10080,7 @@ arm_expand_prologue (void)
 	     stack decrement per function, and this is not it.  If
 	     this instruction is labeled as being part of the frame
 	     creation sequence then dwarf2out_frame_debug_expr will
-	     abort when it encounters the assignment of IP to FP
+	     die when it encounters the assignment of IP to FP
 	     later on, since the use of SP here establishes SP as
 	     the CFA register and not IP.
 
@@ -10620,8 +10590,8 @@ arm_print_operand (FILE *stream, rtx x, int code)
     case 'X':			/* Cirrus register in D mode.  */
     case 'Y':			/* Cirrus register in FX mode.  */
     case 'Z':			/* Cirrus register in DX mode.  */
-      if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
-	abort ();
+      gcc_assert (GET_CODE (x) == REG
+		  && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
 
       fprintf (stream, "mv%s%s",
 	       code == 'W' ? "f"
@@ -10726,21 +10696,26 @@ arm_print_operand (FILE *stream, rtx x, int code)
 	  return;
 	}
 
-      if (GET_CODE (x) == REG)
-	asm_fprintf (stream, "%r", REGNO (x));
-      else if (GET_CODE (x) == MEM)
+      switch (GET_CODE (x))
 	{
+	case REG:
+	  asm_fprintf (stream, "%r", REGNO (x));
+	  break;
+
+	case MEM:
 	  output_memory_reference_mode = GET_MODE (x);
 	  output_address (XEXP (x, 0));
-	}
-      else if (GET_CODE (x) == CONST_DOUBLE)
-	fprintf (stream, "#%s", fp_immediate_constant (x));
-      else if (GET_CODE (x) == NEG)
-	abort (); /* This should never happen now.  */
-      else
-	{
+	  break;
+
+	case CONST_DOUBLE:
+	  fprintf (stream, "#%s", fp_immediate_constant (x));
+	  break;
+
+	default:
+	  gcc_assert (GET_CODE (x) != NEG);
 	  fputc ('#', stream);
 	  output_addr_const (stream, x);
+	  break;
 	}
     }
 }
@@ -10778,8 +10753,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
     {
       int i, units;
 
-      if (GET_CODE (x) != CONST_VECTOR)
-	abort ();
+      gcc_assert (GET_CODE (x) == CONST_VECTOR);
 
       units = CONST_VECTOR_NUNITS (x);
 
@@ -10789,7 +10763,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
 	case V4HImode: size = 2; break;
 	case V8QImode: size = 1; break;
 	default:
-	  abort ();
+	  gcc_unreachable ();
 	}
 
       for (i = 0; i < units; i++)
@@ -10867,8 +10841,7 @@ get_arm_condition_code (rtx comparison)
     case CC_DLTUmode: code = ARM_CC;
 
     dominance:
-      if (comp_code != EQ && comp_code != NE)
-	abort ();
+      gcc_assert (comp_code == EQ || comp_code == NE);
 
       if (comp_code == EQ)
 	return ARM_INVERSE_CONDITION_CODE (code);
@@ -10881,7 +10854,7 @@ get_arm_condition_code (rtx comparison)
 	case EQ: return ARM_EQ;
 	case GE: return ARM_PL;
 	case LT: return ARM_MI;
-	default: abort ();
+	default: gcc_unreachable ();
 	}
 
     case CC_Zmode:
@@ -10889,7 +10862,7 @@ get_arm_condition_code (rtx comparison)
 	{
 	case NE: return ARM_NE;
 	case EQ: return ARM_EQ;
-	default: abort ();
+	default: gcc_unreachable ();
 	}
 
     case CC_Nmode:
@@ -10897,7 +10870,7 @@ get_arm_condition_code (rtx comparison)
 	{
 	case NE: return ARM_MI;
 	case EQ: return ARM_PL;
-	default: abort ();
+	default: gcc_unreachable ();
 	}
 
     case CCFPEmode:
@@ -10922,7 +10895,7 @@ get_arm_condition_code (rtx comparison)
 	  /* UNEQ and LTGT do not have a representation.  */
 	case UNEQ: /* Fall through.  */
 	case LTGT: /* Fall through.  */
-	default: abort ();
+	default: gcc_unreachable ();
 	}
 
     case CC_SWPmode:
@@ -10938,7 +10911,7 @@ get_arm_condition_code (rtx comparison)
 	case GTU: return ARM_CC;
 	case LEU: return ARM_CS;
 	case LTU: return ARM_HI;
-	default: abort ();
+	default: gcc_unreachable ();
 	}
 
     case CC_Cmode:
@@ -10946,7 +10919,7 @@ get_arm_condition_code (rtx comparison)
       {
       case LTU: return ARM_CS;
       case GEU: return ARM_CC;
-      default: abort ();
+      default: gcc_unreachable ();
       }
 
     case CCmode:
@@ -10962,13 +10935,11 @@ get_arm_condition_code (rtx comparison)
 	case GTU: return ARM_HI;
 	case LEU: return ARM_LS;
 	case LTU: return ARM_CC;
-	default: abort ();
+	default: gcc_unreachable ();
 	}
 
-    default: abort ();
+    default: gcc_unreachable ();
     }
-
-  abort ();
 }
 
 void
@@ -11046,8 +11017,7 @@ arm_final_prescan_insn (rtx insn)
 	return;
     }
 
-  if (arm_ccfsm_state != 0 && !reverse)
-    abort ();
+  gcc_assert (!arm_ccfsm_state || reverse);
   if (GET_CODE (insn) != JUMP_INSN)
     return;
 
@@ -11095,7 +11065,7 @@ arm_final_prescan_insn (rtx insn)
 	  then_not_else = FALSE;
         }
       else
-	abort ();
+	gcc_unreachable ();
 
       /* See how many insns this branch skips, and what kind of insns.  If all
 	 insns are okay, and the label or unconditional branch to the same
@@ -11262,14 +11232,16 @@ arm_final_prescan_insn (rtx insn)
 	{
 	  if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
 	    arm_target_label = CODE_LABEL_NUMBER (label);
-	  else if (seeking_return || arm_ccfsm_state == 2)
+	  else
 	    {
+	      gcc_assert (seeking_return || arm_ccfsm_state == 2);
+	      
 	      while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
 	        {
 		  this_insn = next_nonnote_insn (this_insn);
-		  if (this_insn && (GET_CODE (this_insn) == BARRIER
-				    || GET_CODE (this_insn) == CODE_LABEL))
-		    abort ();
+		  gcc_assert (!this_insn
+			      || (GET_CODE (this_insn) != BARRIER
+				  && GET_CODE (this_insn) != CODE_LABEL));
 	        }
 	      if (!this_insn)
 	        {
@@ -11281,12 +11253,9 @@ arm_final_prescan_insn (rtx insn)
 	        }
 	      arm_target_insn = this_insn;
 	    }
-	  else
-	    abort ();
 	  if (jump_clobbers)
 	    {
-	      if (reverse)
-		abort ();
+	      gcc_assert (!reverse);
 	      arm_current_cc =
 		  get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
 							    0), 0), 1));
@@ -11866,7 +11835,7 @@ arm_init_iwmmxt_builtins (void)
 	  break;
 
 	default:
-	  abort ();
+	  gcc_unreachable ();
 	}
 
       def_mbuiltin (d->mask, d->name, type, d->code);
@@ -12012,10 +11981,7 @@ arm_expand_binop_builtin (enum insn_code icode,
       || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
     target = gen_reg_rtx (tmode);
 
-  /* In case the insn wants input operands in modes different from
-     the result, abort.  */
-  if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
-    abort ();
+  gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
 
   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
     op0 = copy_to_mode_reg (mode0, op0);
@@ -12322,8 +12288,7 @@ thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
   int lo_mask = mask & 0xFF;
   int pushed_words = 0;
 
-  if (mask == 0)
-    abort ();
+  gcc_assert (mask);
 
   if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
     {
@@ -12779,8 +12744,7 @@ thumb_far_jump_used_p (void)
 int
 is_called_in_ARM_mode (tree func)
 {
-  if (TREE_CODE (func) != FUNCTION_DECL)
-    abort ();
+  gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
 
   /* Ignore the problem about functions whose address is taken.  */
   if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
@@ -13024,7 +12988,7 @@ thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
 	  return offsets->saved_regs - offsets->saved_args;
 
 	default:
-	  abort();
+	  gcc_unreachable ();
 	}
       break;
 
@@ -13039,12 +13003,12 @@ thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
 	  return offsets->saved_regs - offsets->soft_frame;
 
 	default:
-	  abort();
+	  gcc_unreachable ();
 	}
       break;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 }
 
@@ -13262,10 +13226,9 @@ thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
     {
       const char * name;
 
-      if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
-	abort ();
-      if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
-	abort ();
+      gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
+      gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
+		  == SYMBOL_REF);
       name = XSTR  (XEXP (DECL_RTL (current_function_decl), 0), 0);
 
       /* Generate code sequence to switch us into Thumb mode.  */
@@ -13494,11 +13457,8 @@ thumb_load_double_from_address (rtx *operands)
   rtx arg1;
   rtx arg2;
 
-  if (GET_CODE (operands[0]) != REG)
-    abort ();
-
-  if (GET_CODE (operands[1]) != MEM)
-    abort ();
+  gcc_assert (GET_CODE (operands[0]) == REG);
+  gcc_assert (GET_CODE (operands[1]) == MEM);
 
   /* Get the memory address.  */
   addr = XEXP (operands[1], 0);
@@ -13540,8 +13500,7 @@ thumb_load_double_from_address (rtx *operands)
       else
 	base = arg1, offset = arg2;
 
-      if (GET_CODE (base) != REG)
-	abort ();
+      gcc_assert (GET_CODE (base) == REG);
 
       /* Catch the case of <address> = <reg> + <reg> */
       if (GET_CODE (offset) == REG)
@@ -13598,8 +13557,7 @@ thumb_load_double_from_address (rtx *operands)
       break;
 
     default:
-      abort ();
-      break;
+      gcc_unreachable ();
     }
 
   return "";
@@ -13648,7 +13606,7 @@ thumb_output_move_mem_multiple (int n, rtx *operands)
       break;
 
     default:
-      abort ();
+      gcc_unreachable ();
     }
 
   return "";
@@ -13746,7 +13704,7 @@ thumb_reload_out_hi (rtx *operands)
 void
 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
 {
-  abort ();
+  gcc_unreachable ();
 }
 
 /* Return the length of a function name prefix
@@ -14126,15 +14084,14 @@ arm_emit_vector_const (FILE *file, rtx x)
   int i;
   const char * pattern;
 
-  if (GET_CODE (x) != CONST_VECTOR)
-    abort ();
+  gcc_assert (GET_CODE (x) == CONST_VECTOR);
 
   switch (GET_MODE (x))
     {
     case V2SImode: pattern = "%08x"; break;
     case V4HImode: pattern = "%04x"; break;
     case V8QImode: pattern = "%02x"; break;
-    default:       abort ();
+    default:       gcc_unreachable ();
     }
 
   fprintf (file, "0x");
@@ -14590,6 +14547,6 @@ arm_dbx_register_number (unsigned int regno)
   if (IS_IWMMXT_REGNUM (regno))
     return 112 + regno - FIRST_IWMMXT_REGNUM;
 
-  abort ();
+  gcc_unreachable ();
 }
 

gcc/config/arm/arm.h

@@ -2565,7 +2565,7 @@ extern int making_const_table;
 	  }								\
 									\
 	  default:							\
-	    abort();							\
+	    gcc_unreachable ();						\
 	}								\
     }									\
   else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC		\
@@ -2573,8 +2573,7 @@ extern int making_const_table;
     {									\
       extern enum machine_mode output_memory_reference_mode;		\
 									\
-      if (GET_CODE (XEXP (X, 0)) != REG)				\
-	abort ();							\
+      gcc_assert (GET_CODE (XEXP (X, 0)) == REG);			\
 									\
       if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC)		\
 	asm_fprintf (STREAM, "[%r, #%s%d]!",				\
@@ -2618,8 +2617,7 @@ extern int making_const_table;
     asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0)));	\
   else if (GET_CODE (X) == PLUS)			\
     {							\
-      if (GET_CODE (XEXP (X, 0)) != REG)		\
-        abort ();					\
+      gcc_assert (GET_CODE (XEXP (X, 0)) == REG);	\
       if (GET_CODE (XEXP (X, 1)) == CONST_INT)		\
 	asm_fprintf (STREAM, "[%r, #%wd]", 		\
 		     REGNO (XEXP (X, 0)),		\

gcc/config/arm/arm.md

@@ -3614,12 +3614,8 @@
         ops[1] = mem;
         ops[2] = const0_rtx;
       }
-      
-    if (GET_CODE (ops[1]) != REG)
-      {
-        debug_rtx (ops[1]);
-        abort ();
-      }
+
+    gcc_assert (GET_CODE (ops[1]) == REG);
 
     ops[0] = operands[0];
     ops[3] = operands[2];
@@ -3634,7 +3630,7 @@
 ;; We used to have an early-clobber on the scratch register here.
 ;; However, there's a bug somewhere in reload which means that this
 ;; can be partially ignored during spill allocation if the memory
-;; address also needs reloading; this causes an abort later on when
+;; address also needs reloading; this causes us to die later on when
 ;; we try to verify the operands.  Fortunately, we don't really need
 ;; the early-clobber: we can always use operand 0 if operand 2
 ;; overlaps the address.
@@ -3685,11 +3681,7 @@
         ops[2] = const0_rtx;
       }
       
-    if (GET_CODE (ops[1]) != REG)
-      {
-        debug_rtx (ops[1]);
-        abort ();
-      }
+    gcc_assert (GET_CODE (ops[1]) == REG);
 
     ops[0] = operands[0];
     if (reg_mentioned_p (operands[2], ops[1]))
@@ -3949,10 +3941,9 @@
 	    else
               output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
 	  }
-        else if (GET_CODE (b) != REG)
-	  abort ();
 	else
           {
+	    gcc_assert (GET_CODE (b) == REG);
             if (REGNO (b) == REGNO (ops[0]))
 	      {
                 output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops);
@@ -4032,10 +4023,9 @@
 	    else
               output_asm_insn (\"mov\\t%0, %2\;ldrsb\\t%0, [%1, %0]\", ops);
 	  }
-        else if (GET_CODE (b) != REG)
-	  abort ();
 	else
           {
+	    gcc_assert (GET_CODE (b) == REG);
             if (REGNO (b) == REGNO (ops[0]))
 	      {
                 output_asm_insn (\"ldrb\\t%0, [%2, %1]\", ops);
@@ -4778,8 +4768,7 @@
         {
           /* Writing a constant to memory needs a scratch, which should
 	     be handled with SECONDARY_RELOADs.  */
-          if (GET_CODE (operands[0]) != REG)
-	    abort ();
+          gcc_assert (GET_CODE (operands[0]) == REG);
 
           operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
           emit_insn (gen_movsi (operands[0], operands[1]));
@@ -4821,8 +4810,7 @@
         {
           /* Writing a constant to memory needs a scratch, which should
 	     be handled with SECONDARY_RELOADs.  */
-          if (GET_CODE (operands[0]) != REG)
-	    abort ();
+          gcc_assert (GET_CODE (operands[0]) == REG);
 
           operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
           emit_insn (gen_movsi (operands[0], operands[1]));
@@ -4846,7 +4834,7 @@
     case 3: return \"mov	%0, %1\";
     case 4: return \"mov	%0, %1\";
     case 5: return \"mov	%0, %1\";
-    default: abort ();
+    default: gcc_unreachable ();
     case 1:
       /* The stack pointer can end up being taken as an index register.
           Catch this case here and deal with it.  */
@@ -4957,7 +4945,7 @@
    (clobber (match_operand:SI 2 "register_operand" "=&l"))]
   "TARGET_THUMB"
   "*
-  abort ();"
+  gcc_unreachable ();"
 )
 	
 ;; We use a DImode scratch because we may occasionally need an additional
@@ -5052,8 +5040,7 @@
         {
           /* Writing a constant to memory needs a scratch, which should
 	     be handled with SECONDARY_RELOADs.  */
-          if (GET_CODE (operands[0]) != REG)
-	    abort ();
+          gcc_assert (GET_CODE (operands[0]) == REG);
 
           operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
           emit_insn (gen_movsi (operands[0], operands[1]));
@@ -7059,8 +7046,7 @@
 		      (pc)))]
   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
   "*
-  if (arm_ccfsm_state != 0)
-    abort ();
+  gcc_assert (!arm_ccfsm_state);
 
   return \"bvs\\t%l0\;beq\\t%l0\";
   "
@@ -7076,8 +7062,7 @@
 		      (pc)))]
   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
   "*
-  if (arm_ccfsm_state != 0)
-    abort ();
+  gcc_assert (!arm_ccfsm_state);
 
   return \"bmi\\t%l0\;bgt\\t%l0\";
   "
@@ -7112,8 +7097,7 @@
 		      (label_ref (match_operand 0 "" ""))))]
   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
   "*
-  if (arm_ccfsm_state != 0)
-    abort ();
+  gcc_assert (!arm_ccfsm_state);
 
   return \"bmi\\t%l0\;bgt\\t%l0\";
   "
@@ -7129,8 +7113,7 @@
 		      (label_ref (match_operand 0 "" ""))))]
   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
   "*
-  if (arm_ccfsm_state != 0)
-    abort ();
+  gcc_assert (!arm_ccfsm_state);
 
   return \"bvs\\t%l0\;beq\\t%l0\";
   "
@@ -7286,14 +7269,14 @@
 ;   [(set (match_operand:SI 0 "s_register_operand" "")
 ; 	(uneq:SI (match_dup 1) (const_int 0)))]
 ;   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
-;   "abort ();"
+;   "gcc_unreachable ();"
 ; )
 ;
 ; (define_expand "sltgt"
 ;   [(set (match_operand:SI 0 "s_register_operand" "")
 ; 	(ltgt:SI (match_dup 1) (const_int 0)))]
 ;   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
-;   "abort ();"
+;   "gcc_unreachable ();"
 ; )
 
 (define_insn "*mov_scc"

gcc/config/arm/cirrus.md

@@ -391,7 +391,7 @@
     /* Shifting by 0 will just copy %1 into %0.  */
     case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
 
-    default: abort ();
+    default: gcc_unreachable ();
     }
   }"
   [(set_attr "length"         "  8,   8,     8,   8,     8,     4,     4,     4")
@@ -468,7 +468,7 @@
     case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
     case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
     case 9: return \"cfstrd%?\\t%V1, %0\";
-    default: abort ();
+    default: gcc_unreachable ();
     }
   }"
   [(set_attr "type"           "load1,store2,  *,store2,load1,     *,  load1,   *,     *,store2")

gcc/config/arm/pe.c

@@ -108,13 +108,11 @@ arm_mark_dllexport (decl)
   tree idp;
 
   rtlname = XEXP (DECL_RTL (decl), 0);
-  if (GET_CODE (rtlname) == SYMBOL_REF)
-    oldname = XSTR (rtlname, 0);
-  else if (GET_CODE (rtlname) == MEM
-	   && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
-    oldname = XSTR (XEXP (rtlname, 0), 0);
-  else
-    abort ();
+  if (GET_CODE (rtlname) == MEM)
+    rtlname = XEXP (rtlname, 0);
+  gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
+  oldname = XSTR (rtlname, 0);
+  
   if (arm_dllimport_name_p (oldname))
     oldname += 9;
   else if (arm_dllexport_name_p (oldname))
@@ -147,17 +145,13 @@ arm_mark_dllimport (decl)
 
   rtlname = XEXP (DECL_RTL (decl), 0);
   
-  if (GET_CODE (rtlname) == SYMBOL_REF)
-    oldname = XSTR (rtlname, 0);
-  else if (GET_CODE (rtlname) == MEM
-	   && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
-    oldname = XSTR (XEXP (rtlname, 0), 0);
-  else
-    abort ();
+  if (GET_CODE (rtlname) == MEM)
+    rtlname = XEXP (rtlname, 0);
+  gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
+  oldname = XSTR (rtlname, 0);
   
-  if (arm_dllexport_name_p (oldname))
-    abort (); /* this shouldn't happen */
-  else if (arm_dllimport_name_p (oldname))
+  gcc_assert (!arm_dllexport_name_p (oldname));
+  if (arm_dllimport_name_p (oldname))
     return; /* already done */
 
   /* ??? One can well ask why we're making these checks here,

gcc/config/arm/vfp.md

@@ -158,7 +158,7 @@
     case 7:
       return \"fstd%?\\t%P1, %0\\t%@ int\";
     default:
-      abort ();
+      gcc_unreachable ();
     }
   "
   [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarith,f_load,f_store")
@@ -217,7 +217,7 @@
       case 7:
         return \"#\";
       default:
-	abort ();
+	gcc_unreachable ();
       }
     }
   "