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riscv-gcc-1
Commit e35f75d3 by Segher Boessenkool Committed by Segher Boessenkool
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rs6000: Rename DFP iterator and attr to DDTD and q 

This is more in line with the other iterators we have, and a bit easier
to read and write.


	* config/rs6000/dfp.md (D64_D128): Rename to ...
	(DDTD): ... this, throughout.
	(dfp_suffix): Rename to ...
	(q): ... this, throughout.

From-SVN: r274218
parent b1bb8160
Showing with 59 additions and 56 deletions
gcc/ChangeLog
2019-08-08 Segher Boessenkool <segher@kernel.crashing.org> 2019-08-08 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/dfp.md (D64_D128): Rename to ...
(DDTD): ... this, throughout.
(dfp_suffix): Rename to ...
(q): ... this, throughout.
2019-08-08 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/dfp.md (D64_D128): Move earlier in the file. * config/rs6000/dfp.md (D64_D128): Move earlier in the file.
(dfp_suffix): Ditto. (dfp_suffix): Ditto.
(adddd3, addtd3): Merge to ... (adddd3, addtd3): Merge to ...
......
gcc/config/rs6000/dfp.md
...@@ -29,10 +29,9 @@ ...@@ -29,10 +29,9 @@
]) ])
; Either of the two decimal modes. ; Either of the two decimal modes.
(define_mode_iterator D64_D128 [DD TD]) (define_mode_iterator DDTD [DD TD])
(define_mode_attr dfp_suffix [(DD "") (define_mode_attr q [(DD "") (TD "q")])
(TD "q")])
(define_insn "movsd_store" (define_insn "movsd_store"
...@@ -157,43 +156,43 @@ ...@@ -157,43 +156,43 @@
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "add<mode>3" (define_insn "add<mode>3"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(plus:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "%d") (plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")))] (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dadd<dfp_suffix> %0,%1,%2" "dadd<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "sub<mode>3" (define_insn "sub<mode>3"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(minus:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d") (minus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")))] (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dsub<dfp_suffix> %0,%1,%2" "dsub<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "mul<mode>3" (define_insn "mul<mode>3"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(mult:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "%d") (mult:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")))] (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dmul<dfp_suffix> %0,%1,%2" "dmul<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "div<mode>3" (define_insn "div<mode>3"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(div:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d") (div:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")))] (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"ddiv<dfp_suffix> %0,%1,%2" "ddiv<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "*cmp<mode>_internal1" (define_insn "*cmp<mode>_internal1"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:D64_D128 1 "gpc_reg_operand" "d") (compare:CCFP (match_operand:DDTD 1 "gpc_reg_operand" "d")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")))] (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dcmpu<dfp_suffix> %0,%1,%2" "dcmpu<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "floatdidd2" (define_insn "floatdidd2"
...@@ -214,10 +213,10 @@ ...@@ -214,10 +213,10 @@
;; This is the first stage of converting it to an integer type. ;; This is the first stage of converting it to an integer type.
(define_insn "ftrunc<mode>2" (define_insn "ftrunc<mode>2"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(fix:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d")))] (fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"drintn<dfp_suffix>. 0,%0,%1,1" "drintn<q>. 0,%0,%1,1"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
;; Convert a decimal64/128 whose value is an integer to an actual integer. ;; Convert a decimal64/128 whose value is an integer to an actual integer.
...@@ -225,9 +224,9 @@ ...@@ -225,9 +224,9 @@
(define_insn "fix<mode>di2" (define_insn "fix<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d") [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(fix:DI (match_operand:D64_D128 1 "gpc_reg_operand" "d")))] (fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP" "TARGET_DFP"
"dctfix<dfp_suffix> %0,%1" "dctfix<q> %0,%1"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
;; Decimal builtin support ;; Decimal builtin support
...@@ -244,48 +243,46 @@ ...@@ -244,48 +243,46 @@
(define_code_iterator DFP_TEST [eq lt gt unordered]) (define_code_iterator DFP_TEST [eq lt gt unordered])
(define_insn "dfp_ddedpd_<mode>" (define_insn "dfp_ddedpd_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i") (unspec:DDTD [(match_operand:QI 1 "const_0_to_3_operand" "i")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")] (match_operand:DDTD 2 "gpc_reg_operand" "d")]
UNSPEC_DDEDPD))] UNSPEC_DDEDPD))]
"TARGET_DFP" "TARGET_DFP"
"ddedpd<dfp_suffix> %1,%0,%2" "ddedpd<q> %1,%0,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "dfp_denbcd_<mode>" (define_insn "dfp_denbcd_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i") (unspec:DDTD [(match_operand:QI 1 "const_0_to_1_operand" "i")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")] (match_operand:DDTD 2 "gpc_reg_operand" "d")]
UNSPEC_DENBCD))] UNSPEC_DENBCD))]
"TARGET_DFP" "TARGET_DFP"
"denbcd<dfp_suffix> %1,%0,%2" "denbcd<q> %1,%0,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "dfp_dxex_<mode>" (define_insn "dfp_dxex_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d") [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")] (unspec:DI [(match_operand:DDTD 1 "gpc_reg_operand" "d")]
UNSPEC_DXEX))] UNSPEC_DXEX))]
"TARGET_DFP" "TARGET_DFP"
"dxex<dfp_suffix> %0,%1" "dxex<q> %0,%1"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "dfp_diex_<mode>" (define_insn "dfp_diex_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d") (unspec:DDTD [(match_operand:DI 1 "gpc_reg_operand" "d")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")] (match_operand:DDTD 2 "gpc_reg_operand" "d")]
UNSPEC_DXEX))] UNSPEC_DXEX))]
"TARGET_DFP" "TARGET_DFP"
"diex<dfp_suffix> %0,%1,%2" "diex<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_expand "dfptstsfi_<code>_<mode>" (define_expand "dfptstsfi_<code>_<mode>"
[(set (match_dup 3) [(set (match_dup 3)
(compare:CCFP (compare:CCFP (unspec:DDTD [(match_operand:SI 1 "const_int_operand")
(unspec:D64_D128 (match_operand:DDTD 2 "gpc_reg_operand")]
[(match_operand:SI 1 "const_int_operand")
(match_operand:D64_D128 2 "gpc_reg_operand")]
UNSPEC_DTSTSFI) UNSPEC_DTSTSFI)
(match_dup 4))) (const_int 0)))
(set (match_operand:SI 0 "register_operand") (set (match_operand:SI 0 "register_operand")
(DFP_TEST:SI (match_dup 3) (DFP_TEST:SI (match_dup 3)
(const_int 0))) (const_int 0)))
...@@ -293,14 +290,13 @@ ...@@ -293,14 +290,13 @@
"TARGET_P9_MISC" "TARGET_P9_MISC"
{ {
operands[3] = gen_reg_rtx (CCFPmode); operands[3] = gen_reg_rtx (CCFPmode);
operands[4] = const0_rtx;
}) })
(define_insn "*dfp_sgnfcnc_<mode>" (define_insn "*dfp_sgnfcnc_<mode>"
[(set (match_operand:CCFP 0 "" "=y") [(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP (compare:CCFP
(unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n") (unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")] (match_operand:DDTD 2 "gpc_reg_operand" "d")]
UNSPEC_DTSTSFI) UNSPEC_DTSTSFI)
(match_operand:SI 3 "zero_constant" "j")))] (match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_MISC" "TARGET_P9_MISC"
...@@ -310,24 +306,24 @@ ...@@ -310,24 +306,24 @@
immediate operand values greater than 63. */ immediate operand values greater than 63. */
if (!(IN_RANGE (INTVAL (operands[1]), 0, 63))) if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
operands[1] = GEN_INT (63); operands[1] = GEN_INT (63);
return "dtstsfi<dfp_suffix> %0,%1,%2"; return "dtstsfi<q> %0,%1,%2";
} }
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "dfp_dscli_<mode>" (define_insn "dfp_dscli_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
(match_operand:QI 2 "immediate_operand" "i")] (match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_DSCLI))] UNSPEC_DSCLI))]
"TARGET_DFP" "TARGET_DFP"
"dscli<dfp_suffix> %0,%1,%2" "dscli<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
(define_insn "dfp_dscri_<mode>" (define_insn "dfp_dscri_<mode>"
[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
(match_operand:QI 2 "immediate_operand" "i")] (match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_DSCRI))] UNSPEC_DSCRI))]
"TARGET_DFP" "TARGET_DFP"
"dscri<dfp_suffix> %0,%1,%2" "dscri<q> %0,%1,%2"
[(set_attr "type" "dfp")]) [(set_attr "type" "dfp")])
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