Commit e2fd7ca7 by Sofiane Naci Committed by Sofiane Naci

types.md (define_attr "type"): Add "load_acq" and "store_rel".

	* config/arm/types.md (define_attr "type"): Add "load_acq" and "store_rel".
	* config/arm/cortex-a53.md (cortex_a53_load1): Update for attribute
	changes.
	(cortex_a53_store1): Likewise.

From-SVN: r201436
parent f43b3c4b
2013-08-02 Sofiane Naci <sofiane.naci@arm.com>
* config/arm/types.md (define_attr "type"): Add "load_acq" and "store_rel".
* config/arm/cortex-a53.md (cortex_a53_load1): Update for attribute
changes.
(cortex_a53_store1): Likewise.
2013-08-01 Jan Hubicka <jh@suse.cz> 2013-08-01 Jan Hubicka <jh@suse.cz>
* ipa.c (symtab_remove_unreachable_nodes): Nodes in other partitions are * ipa.c (symtab_remove_unreachable_nodes): Nodes in other partitions are
......
...@@ -130,12 +130,12 @@ ...@@ -130,12 +130,12 @@
(define_insn_reservation "cortex_a53_load1" 3 (define_insn_reservation "cortex_a53_load1" 3
(and (eq_attr "tune" "cortexa53") (and (eq_attr "tune" "cortexa53")
(eq_attr "type" "load_byte,load1")) (eq_attr "type" "load_byte,load1,load_acq"))
"cortex_a53_slot_any+cortex_a53_ls") "cortex_a53_slot_any+cortex_a53_ls")
(define_insn_reservation "cortex_a53_store1" 2 (define_insn_reservation "cortex_a53_store1" 2
(and (eq_attr "tune" "cortexa53") (and (eq_attr "tune" "cortexa53")
(eq_attr "type" "store1")) (eq_attr "type" "store1,store_rel"))
"cortex_a53_slot_any+cortex_a53_ls+cortex_a53_store") "cortex_a53_slot_any+cortex_a53_ls+cortex_a53_store")
(define_insn_reservation "cortex_a53_load2" 3 (define_insn_reservation "cortex_a53_load2" 3
......
...@@ -57,6 +57,7 @@ ...@@ -57,6 +57,7 @@
; float floating point arithmetic operation. ; float floating point arithmetic operation.
; fmac[d,s] double/single floating point multiply-accumulate. ; fmac[d,s] double/single floating point multiply-accumulate.
; fmul[d,s] double/single floating point multiply. ; fmul[d,s] double/single floating point multiply.
; load_acq load-acquire.
; load_byte load byte(s) from memory to arm registers. ; load_byte load byte(s) from memory to arm registers.
; load1 load 1 word from memory to arm registers. ; load1 load 1 word from memory to arm registers.
; load2 load 2 words from memory to arm registers. ; load2 load 2 words from memory to arm registers.
...@@ -105,6 +106,7 @@ ...@@ -105,6 +106,7 @@
; smulxy signed multiply, 16x16-bit, 32-bit accumulate. ; smulxy signed multiply, 16x16-bit, 32-bit accumulate.
; smusd signed dual multiply subtract. ; smusd signed dual multiply subtract.
; smusdx signed dual multiply subtract reverse. ; smusdx signed dual multiply subtract reverse.
; store_rel store-release.
; store1 store 1 word to memory from arm registers. ; store1 store 1 word to memory from arm registers.
; store2 store 2 words to memory from arm registers. ; store2 store 2 words to memory from arm registers.
; store3 store 3 words to memory from arm registers. ; store3 store 3 words to memory from arm registers.
...@@ -221,6 +223,7 @@ ...@@ -221,6 +223,7 @@
fmacs,\ fmacs,\
fmuld,\ fmuld,\
fmuls,\ fmuls,\
load_acq,\
load_byte,\ load_byte,\
load1,\ load1,\
load2,\ load2,\
...@@ -265,6 +268,7 @@ ...@@ -265,6 +268,7 @@
smulxy,\ smulxy,\
smusd,\ smusd,\
smusdx,\ smusdx,\
store_rel,\
store1,\ store1,\
store2,\ store2,\
store3,\ store3,\
......
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