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riscv-gcc-1
Commit deb9225a by Richard Kenner
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(addsi3): Prefer add without carry instructions and flag input operands as… 

(addsi3): Prefer add without carry instructions and flag input operands as commutative for condition register variant.

(addsi3): Prefer add without carry instructions and
flag input operands as commutative for condition register variant.
(subsi3): Define PowerPC patterns using subtract without carry.
(numerous): Flag input operands as commutative for condition register variant.
(mov* matchers): Use mr instruction in ! TARGET_POWERPC case as well and
mr. in condition register variant.

From-SVN: r7166
parent 40acaab8
Showing with 92 additions and 45 deletions
gcc/config/rs6000/rs6000.md
...@@ -332,34 +332,43 @@ ...@@ -332,34 +332,43 @@
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
;; Fixed-point arithmetic insns. ;; Fixed-point arithmetic insns.
;; Discourage ai/addic because of carry but provide it in an alternative
;; allowing register zero as source.
(define_insn "addsi3" (define_insn "addsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b") (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
(match_operand:SI 2 "add_operand" "rI,J")))] (match_operand:SI 2 "add_operand" "r,I,I,J")))]
"" ""
"@ "@
{a%I2|add%I2c} %0,%1,%2 {cax|add} %0,%1,%2
{cal %0,%2(%1)|addi %0,%1,%2}
{ai|addic} %0,%1,%2
{cau|addis} %0,%1,%u2") {cau|addis} %0,%1,%u2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "rI")) (match_operand:SI 2 "reg_or_short_operand" "r,I"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r,r"))]
"" ""
"{a%I2.|add%I2c.} %3,%1,%2" "@
{cax.|add.} %3,%1,%2
{ai.|addic.} %3,%1,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "rI")) (match_operand:SI 2 "reg_or_short_operand" "r,I"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"" ""
"{a%I2.|add%I2c.} %0,%1,%2" "@
{cax.|add.} %0,%1,%2
{ai.|addic.} %0,%1,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
;; Split an add that we can't do in one insn into two insns, each of which ;; Split an add that we can't do in one insn into two insns, each of which
...@@ -414,30 +423,60 @@ ...@@ -414,30 +423,60 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
(match_operand:SI 2 "gpc_reg_operand" "r")))] (match_operand:SI 2 "gpc_reg_operand" "r")))]
"" "! TARGET_POWERPC"
"{sf%I1|subf%I1c} %0,%2,%1") "{sf%I1|subf%I1c} %0,%2,%1")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
(match_operand:SI 2 "gpc_reg_operand" "r,r")))]
"TARGET_POWERPC"
"@
subf %0,%2,%1
subfic %0,%2,%1")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" "! TARGET_POWERPC"
"{sf.|subfc.} %3,%2,%1" "{sf.|subfc.} %3,%2,%1"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"TARGET_POWERPC"
"subf. %3,%2,%1"
[(set_attr "type" "compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))] (minus:SI (match_dup 1) (match_dup 2)))]
"" "! TARGET_POWERPC"
"{sf.|subfc.} %0,%2,%1" "{sf.|subfc.} %0,%2,%1"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC"
"subf. %0,%2,%1"
[(set_attr "type" "compare")])
(define_expand "subsi3" (define_expand "subsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "") [(set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "") (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
...@@ -657,7 +696,7 @@ ...@@ -657,7 +696,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r")) (clobber (match_scratch:SI 3 "=r"))
...@@ -668,7 +707,7 @@ ...@@ -668,7 +707,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
...@@ -678,7 +717,7 @@ ...@@ -678,7 +717,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -690,7 +729,7 @@ ...@@ -690,7 +729,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -722,6 +761,7 @@ ...@@ -722,6 +761,7 @@
DONE; DONE;
} }
}") }")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
...@@ -756,6 +796,7 @@ ...@@ -756,6 +796,7 @@
DONE; DONE;
} }
}") }")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
...@@ -1096,7 +1137,7 @@ ...@@ -1096,7 +1137,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
...@@ -1106,7 +1147,7 @@ ...@@ -1106,7 +1147,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -1144,7 +1185,7 @@ ...@@ -1144,7 +1185,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
...@@ -1154,7 +1195,7 @@ ...@@ -1154,7 +1195,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -1266,14 +1307,14 @@ ...@@ -1266,14 +1307,14 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
"" ""
"nand %0,%1,%2") "nand %0,%1,%2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
...@@ -1283,7 +1324,7 @@ ...@@ -1283,7 +1324,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -1294,14 +1335,14 @@ ...@@ -1294,14 +1335,14 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
"" ""
"nor %0,%1,%2") "nor %0,%1,%2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
...@@ -1311,7 +1352,7 @@ ...@@ -1311,7 +1352,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x") [(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
...@@ -2767,6 +2808,7 @@ ...@@ -2767,6 +2808,7 @@
"TARGET_POWER2 || TARGET_POWERPC" "TARGET_POWER2 || TARGET_POWERPC"
"{fcirz|fctiwz} %0,%1" "{fcirz|fctiwz} %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "fixuns_truncdfsi2" (define_expand "fixuns_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "") [(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
...@@ -2778,7 +2820,6 @@ ...@@ -2778,7 +2820,6 @@
DONE; DONE;
}") }")
(define_expand "trunc_call" (define_expand "trunc_call"
[(parallel [(set (match_operand:SI 0 "" "") [(parallel [(set (match_operand:SI 0 "" "")
(fix:SI (match_operand:DF 1 "" ""))) (fix:SI (match_operand:DF 1 "" "")))
...@@ -2911,6 +2952,7 @@ ...@@ -2911,6 +2952,7 @@
DONE; DONE;
} }
}") }")
(define_insn "mulsidi3_mq" (define_insn "mulsidi3_mq"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
...@@ -2920,6 +2962,7 @@ ...@@ -2920,6 +2962,7 @@
"mul %0,%1,%2\;mfmq %L0" "mul %0,%1,%2\;mfmq %L0"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "" (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
...@@ -2928,6 +2971,7 @@ ...@@ -2928,6 +2971,7 @@
"mulhw %0,%1,%2\;mullw %L0,%1,%2" "mulhw %0,%1,%2\;mullw %L0,%1,%2"
[(set_attr "type" "imul") [(set_attr "type" "imul")
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_expand "smulsi3_highpart" (define_expand "smulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "") [(set (match_operand:SI 0 "gpc_reg_operand" "")
(truncate:SI (truncate:SI
...@@ -2953,6 +2997,7 @@ ...@@ -2953,6 +2997,7 @@
DONE; DONE;
} }
}") }")
(define_insn "smulsi3_highpart_mq" (define_insn "smulsi3_highpart_mq"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(truncate:SI (truncate:SI
...@@ -2965,6 +3010,7 @@ ...@@ -2965,6 +3010,7 @@
"TARGET_POWER" "TARGET_POWER"
"mul %0,%1,%2" "mul %0,%1,%2"
[(set_attr "type" "imul")]) [(set_attr "type" "imul")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(truncate:SI (truncate:SI
...@@ -2976,6 +3022,7 @@ ...@@ -2976,6 +3022,7 @@
"TARGET_POWERPC" "TARGET_POWERPC"
"mulhw %0,%1,%2" "mulhw %0,%1,%2"
[(set_attr "type" "imul")]) [(set_attr "type" "imul")])
(define_insn "umulsi3_highpart" (define_insn "umulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(truncate:SI (truncate:SI
...@@ -3106,7 +3153,7 @@ ...@@ -3106,7 +3153,7 @@
"TARGET_POWER && (gpc_reg_operand (operands[0], SImode) "TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode))" || gpc_reg_operand (operands[1], SImode))"
"@ "@
{ai|addic} %0,%1,0 mr %0,%1
{l%U1%X1|lwz%U1%X1} %0,%1 {l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%X0|stw%U0%X0} %1,%0 {st%U0%X0|stw%U0%X0} %1,%0
{cal %0,%1(0)|li %0,%1} {cal %0,%1(0)|li %0,%1}
...@@ -3158,7 +3205,7 @@ ...@@ -3158,7 +3205,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"" ""
"{ai.|addic.} %0,%1,0" "mr. %0,%1"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_expand "movhi" (define_expand "movhi"
...@@ -3186,7 +3233,7 @@ ...@@ -3186,7 +3233,7 @@
"TARGET_POWER && (gpc_reg_operand (operands[0], HImode) "TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
|| gpc_reg_operand (operands[1], HImode))" || gpc_reg_operand (operands[1], HImode))"
"@ "@
{oril|ori} %0,%1,0 mr %0,%1
lhz%U1%X1 %0,%1 lhz%U1%X1 %0,%1
sth%U0%X0 %1,%0 sth%U0%X0 %1,%0
{cal %0,%w1(0)|li %0,%w1} {cal %0,%w1(0)|li %0,%w1}
...@@ -3201,7 +3248,7 @@ ...@@ -3201,7 +3248,7 @@
"! TARGET_POWER && (gpc_reg_operand (operands[0], HImode) "! TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
|| gpc_reg_operand (operands[1], HImode))" || gpc_reg_operand (operands[1], HImode))"
"@ "@
ori %0,%1,0 mr %0,%1
lhz%U1%X1 %0,%1 lhz%U1%X1 %0,%1
sth%U0%X0 %1,%0 sth%U0%X0 %1,%0
li %0,%w1 li %0,%w1
...@@ -3234,7 +3281,7 @@ ...@@ -3234,7 +3281,7 @@
"TARGET_POWER && (gpc_reg_operand (operands[0], QImode) "TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
|| gpc_reg_operand (operands[1], QImode))" || gpc_reg_operand (operands[1], QImode))"
"@ "@
{oril|ori} %0,%1,0 mr %0,%1
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
stb%U0%X0 %1,%0 stb%U0%X0 %1,%0
{cal %0,%1(0)|li %0,%1} {cal %0,%1(0)|li %0,%1}
...@@ -3277,7 +3324,7 @@ ...@@ -3277,7 +3324,7 @@
{rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
mfcr %0 mfcr %0
mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
{ai %0,%1,0|mr %0,%1} mr %0,%1
{l%U1%X1|lwz%U1%X1} %0,%1 {l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%U1|stw%U0%U1} %1,%0" {st%U0%U1|stw%U0%U1} %1,%0"
[(set_attr "type" "*,*,*,compare,*,*,load,*") [(set_attr "type" "*,*,*,compare,*,*,load,*")
...@@ -3452,9 +3499,9 @@ ...@@ -3452,9 +3499,9 @@
the first register operand 0 is the same as the second register of the first register operand 0 is the same as the second register of
operand 1, we must copy in the opposite order. */ operand 1, we must copy in the opposite order. */
if (REGNO (operands[0]) == REGNO (operands[1]) + 1) if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\"; return \"mr %L0,%L1\;mr %0,%1\";
else else
return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\"; return \"mr %0,%1\;mr %L0,%L1\";
case 1: case 1:
/* If the low-address word is used in the address, we must load it /* If the low-address word is used in the address, we must load it
last. Otherwise, load it first. Note that we cannot have last. Otherwise, load it first. Note that we cannot have
...@@ -3516,9 +3563,9 @@ ...@@ -3516,9 +3563,9 @@
the first register operand 0 is the same as the second register of the first register operand 0 is the same as the second register of
operand 1, we must copy in the opposite order. */ operand 1, we must copy in the opposite order. */
if (REGNO (operands[0]) == REGNO (operands[1]) + 1) if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\"; return \"mr %L0,%L1\;mr %0,%1\";
else else
return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\"; return \"mr %0,%1\;mr %L0,%L1\";
case 1: case 1:
/* If the low-address word is used in the address, we must load it /* If the low-address word is used in the address, we must load it
last. Otherwise, load it first. Note that we cannot have last. Otherwise, load it first. Note that we cannot have
...@@ -3595,9 +3642,9 @@ ...@@ -3595,9 +3642,9 @@
is the second, third, or fourth register in the input. */ is the second, third, or fourth register in the input. */
if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
&& REGNO (operands[0]) <= REGNO (operands[1]) + 3) && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
return \"{oril %Z0,%Z1,0|mr %Z0,%Z1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\"; return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
else else
return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %Z0,%Z1,0|mr %Z0,%Z1}\"; return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
case 3: case 3:
/* If the address is not used in the output, we can use lsi. Otherwise, /* If the address is not used in the output, we can use lsi. Otherwise,
fall through to generating four loads. */ fall through to generating four loads. */
...@@ -4817,7 +4864,7 @@ ...@@ -4817,7 +4864,7 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r") (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
"" ""
"@ "@
......
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