mips.md (*baddu_si_eb, [...]): Merge into...

gcc/
	* config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...
	(*baddu_si): ...this new pattern.

From-SVN: r191997

gcc/ChangeLog

 2012-10-02  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...
+	(*baddu_si): ...this new pattern.
+
+2012-10-02  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* ira-int.h (target_ira_int): Add x_ira_useful_class_mode_regs.
 	(ira_useful_class_mode_regs): New macro.
 	* ira.c (clarify_prohibited_class_mode_regs): Set up

gcc/config/mips/mips.md

@@ -1293,23 +1293,12 @@
 
 ;; Combiner patterns for unsigned byte-add.
 
-(define_insn "*baddu_si_eb"
+(define_insn "*baddu_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (zero_extend:SI
-	 (subreg:QI
-	  (plus:SI (match_operand:SI 1 "register_operand" "d")
-		   (match_operand:SI 2 "register_operand" "d")) 3)))]
-  "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
-  "baddu\\t%0,%1,%2"
-  [(set_attr "alu_type" "add")])
-
-(define_insn "*baddu_si_el"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (zero_extend:SI
-	 (subreg:QI
-	  (plus:SI (match_operand:SI 1 "register_operand" "d")
-		   (match_operand:SI 2 "register_operand" "d")) 0)))]
-  "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
+	 (plus:QI (match_operand:QI 1 "register_operand" "d")
+		  (match_operand:QI 2 "register_operand" "d"))))]
+  "ISA_HAS_BADDU"
   "baddu\\t%0,%1,%2"
   [(set_attr "alu_type" "add")])