Skip to content

R
riscv-gcc-1
Commit d9030ea4 by Naveen H.S
Options

Use braced string notation where applicable for v850.md 

From-SVN: r186747
parent b8ed5fd0
Showing with 284 additions and 304 deletions
gcc/config/v850/v850.md
...@@ -180,26 +180,28 @@ ...@@ -180,26 +180,28 @@
"st.w %2,%1[%0]" "st.w %2,%1[%0]"
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "none_0hit")]) (set_attr "cc" "none_0hit")])
;; movqi ;; movqi
(define_expand "movqi" (define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "") [(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "general_operand" ""))] (match_operand:QI 1 "general_operand" ""))]
"" ""
" {
{
/* One of the ops has to be in a register or 0 */ /* One of the ops has to be in a register or 0 */
if (!register_operand (operand0, QImode) if (!register_operand (operand0, QImode)
&& !reg_or_0_operand (operand1, QImode)) && !reg_or_0_operand (operand1, QImode))
operands[1] = copy_to_mode_reg (QImode, operand1); operands[1] = copy_to_mode_reg (QImode, operand1);
}") })
(define_insn "*movqi_internal" (define_insn "*movqi_internal"
[(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m") [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
(match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
"register_operand (operands[0], QImode) "register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode)" || reg_or_0_operand (operands[1], QImode)"
"* return output_move_single (operands);" {
return output_move_single (operands);
}
[(set_attr "length" "2,4,2,2,4,4,4") [(set_attr "length" "2,4,2,2,4,4,4")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,load,other,load,store,store")]) (set_attr "type" "other,other,load,other,load,store,store")])
...@@ -210,20 +212,21 @@ ...@@ -210,20 +212,21 @@
[(set (match_operand:HI 0 "general_operand" "") [(set (match_operand:HI 0 "general_operand" "")
(match_operand:HI 1 "general_operand" ""))] (match_operand:HI 1 "general_operand" ""))]
"" ""
"
{ {
/* One of the ops has to be in a register or 0 */ /* One of the ops has to be in a register or 0 */
if (!register_operand (operand0, HImode) if (!register_operand (operand0, HImode)
&& !reg_or_0_operand (operand1, HImode)) && !reg_or_0_operand (operand1, HImode))
operands[1] = copy_to_mode_reg (HImode, operand1); operands[1] = copy_to_mode_reg (HImode, operand1);
}") })
(define_insn "*movhi_internal" (define_insn "*movhi_internal"
[(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m") [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
(match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
"register_operand (operands[0], HImode) "register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode)" || reg_or_0_operand (operands[1], HImode)"
"* return output_move_single (operands);" {
return output_move_single (operands);
}
[(set_attr "length" "2,4,2,2,4,4,4") [(set_attr "length" "2,4,2,2,4,4,4")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,load,other,load,store,store")]) (set_attr "type" "other,other,load,other,load,store,store")])
...@@ -253,8 +256,7 @@ ...@@ -253,8 +256,7 @@
[(set (match_operand:SI 0 "general_operand" "") [(set (match_operand:SI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))] (match_operand:SI 1 "general_operand" ""))]
"" ""
" {
{
/* One of the ops has to be in a register or 0 */ /* One of the ops has to be in a register or 0 */
if (!register_operand (operand0, SImode) if (!register_operand (operand0, SImode)
&& !reg_or_0_operand (operand1, SImode)) && !reg_or_0_operand (operand1, SImode))
...@@ -284,7 +286,7 @@ ...@@ -284,7 +286,7 @@
gen_rtx_LO_SUM (SImode, temp, operand1))); gen_rtx_LO_SUM (SImode, temp, operand1)));
DONE; DONE;
} }
}") })
;; This is the same as the following pattern, except that it includes ;; This is the same as the following pattern, except that it includes
;; support for arbitrary 32-bit immediates. ;; support for arbitrary 32-bit immediates.
...@@ -299,7 +301,9 @@ ...@@ -299,7 +301,9 @@
"(TARGET_V850E || TARGET_V850E2_ALL) "(TARGET_V850E || TARGET_V850E2_ALL)
&& (register_operand (operands[0], SImode) && (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))" || reg_or_0_operand (operands[1], SImode))"
"* return output_move_single (operands);" {
return output_move_single (operands);
}
[(set_attr "length" "2,4,4,2,2,4,4,4,4,6") [(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,load,other,load,other,store,store,other")]) (set_attr "type" "other,other,other,load,other,load,other,store,store,other")])
...@@ -309,7 +313,9 @@ ...@@ -309,7 +313,9 @@
(match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))] (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
"register_operand (operands[0], SImode) "register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode)" || reg_or_0_operand (operands[1], SImode)"
"* return output_move_single (operands);" {
return output_move_single (operands);
}
[(set_attr "length" "2,4,4,2,2,4,4,4,4") [(set_attr "length" "2,4,4,2,2,4,4,4,4")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,load,other,load,store,store,other")]) (set_attr "type" "other,other,other,load,other,load,store,store,other")])
...@@ -319,7 +325,9 @@ ...@@ -319,7 +325,9 @@
(match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))] (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
"register_operand (operands[0], SFmode) "register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode)" || reg_or_0_operand (operands[1], SFmode)"
"* return output_move_single (operands);" {
return output_move_single (operands);
}
[(set_attr "length" "2,4,4,8,2,2,4,4,4,8") [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
(set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
(set_attr "type" "other,other,other,other,load,other,load,store,store,other")]) (set_attr "type" "other,other,other,other,load,other,load,store,store,other")])
...@@ -380,12 +388,11 @@ ...@@ -380,12 +388,11 @@
(compare (match_operand:SI 0 "register_operand" "r,r") (compare (match_operand:SI 0 "register_operand" "r,r")
(match_operand:SI 1 "reg_or_int5_operand" "r,J")))] (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
"" ""
" {
{
v850_compare_op0 = operands[0]; v850_compare_op0 = operands[0];
v850_compare_op1 = operands[1]; v850_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_insn "cmpsi_insn" (define_insn "cmpsi_insn"
[(set (cc0) [(set (cc0)
...@@ -403,24 +410,22 @@ ...@@ -403,24 +410,22 @@
(compare (match_operand:SF 0 "register_operand" "r") (compare (match_operand:SF 0 "register_operand" "r")
(match_operand:SF 1 "register_operand" "r")))] (match_operand:SF 1 "register_operand" "r")))]
"TARGET_V850E2V3" "TARGET_V850E2V3"
" {
{
v850_compare_op0 = operands[0]; v850_compare_op0 = operands[0];
v850_compare_op1 = operands[1]; v850_compare_op1 = operands[1];
DONE; DONE;
}") })
(define_expand "cmpdf" (define_expand "cmpdf"
[(set (reg:CC CC_REGNUM) [(set (reg:CC CC_REGNUM)
(compare (match_operand:DF 0 "even_reg_operand" "r") (compare (match_operand:DF 0 "even_reg_operand" "r")
(match_operand:DF 1 "even_reg_operand" "r")))] (match_operand:DF 1 "even_reg_operand" "r")))]
"TARGET_V850E2V3" "TARGET_V850E2V3"
" {
{
v850_compare_op0 = operands[0]; v850_compare_op0 = operands[0];
v850_compare_op1 = operands[1]; v850_compare_op1 = operands[1];
DONE; DONE;
}") })
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; ADD INSTRUCTIONS ;; ADD INSTRUCTIONS
...@@ -475,11 +480,13 @@ ...@@ -475,11 +480,13 @@
(sign_extend:SI (match_operand:HI 1 "register_operand" "")) (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
(sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))] (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
"" ""
"if (GET_CODE (operands[2]) == CONST_INT) {
if (GET_CODE (operands[2]) == CONST_INT)
{ {
emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2])); emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
DONE; DONE;
}") }
})
(define_insn "*mulhisi3_internal1" (define_insn "*mulhisi3_internal1"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -544,12 +551,12 @@ ...@@ -544,12 +551,12 @@
(match_dup 2))) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_V850E || TARGET_V850E2_ALL" "TARGET_V850E || TARGET_V850E2_ALL"
{ {
if (TARGET_V850E2_ALL) if (TARGET_V850E2_ALL)
return "divq %2,%0,%3"; return "divq %2,%0,%3";
else else
return "div %2,%0,%3"; return "div %2,%0,%3";
} }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "div")]) (set_attr "type" "div")])
...@@ -563,12 +570,12 @@ ...@@ -563,12 +570,12 @@
(match_dup 2))) (match_dup 2)))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_V850E || TARGET_V850E2_ALL" "TARGET_V850E || TARGET_V850E2_ALL"
{ {
if (TARGET_V850E2_ALL) if (TARGET_V850E2_ALL)
return "divqu %2,%0,%3"; return "divqu %2,%0,%3";
else else
return "divu %2,%0,%3"; return "divu %2,%0,%3";
} }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "div")]) (set_attr "type" "div")])
...@@ -618,14 +625,13 @@ ...@@ -618,14 +625,13 @@
(match_operand:QI 1 "not_power_of_two_operand" "")) 0)) (match_operand:QI 1 "not_power_of_two_operand" "")) 0))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"*
{ {
rtx xoperands[2]; rtx xoperands[2];
xoperands[0] = operands[0]; xoperands[0] = operands[0];
xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff); xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
output_asm_insn (\"clr1 %M1,%0\", xoperands); output_asm_insn ("clr1 %M1,%0", xoperands);
return \"\"; return "";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "bit1")]) (set_attr "type" "bit1")])
...@@ -637,7 +643,6 @@ ...@@ -637,7 +643,6 @@
(match_operand:HI 1 "not_power_of_two_operand" "")) 0)) (match_operand:HI 1 "not_power_of_two_operand" "")) 0))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"*
{ {
int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff); int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
...@@ -645,9 +650,9 @@ ...@@ -645,9 +650,9 @@
xoperands[0] = gen_rtx_MEM (QImode, xoperands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), log2 / 8)); plus_constant (XEXP (operands[0], 0), log2 / 8));
xoperands[1] = GEN_INT (log2 % 8); xoperands[1] = GEN_INT (log2 % 8);
output_asm_insn (\"clr1 %1,%0\", xoperands); output_asm_insn ("clr1 %1,%0", xoperands);
return \"\"; return "";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "bit1")]) (set_attr "type" "bit1")])
...@@ -658,7 +663,6 @@ ...@@ -658,7 +663,6 @@
(match_operand:SI 1 "not_power_of_two_operand" ""))) (match_operand:SI 1 "not_power_of_two_operand" "")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"*
{ {
int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff); int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
...@@ -666,9 +670,9 @@ ...@@ -666,9 +670,9 @@
xoperands[0] = gen_rtx_MEM (QImode, xoperands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), log2 / 8)); plus_constant (XEXP (operands[0], 0), log2 / 8));
xoperands[1] = GEN_INT (log2 % 8); xoperands[1] = GEN_INT (log2 % 8);
output_asm_insn (\"clr1 %1,%0\", xoperands); output_asm_insn ("clr1 %1,%0", xoperands);
return \"\"; return "";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "bit1")]) (set_attr "type" "bit1")])
...@@ -706,12 +710,11 @@ ...@@ -706,12 +710,11 @@
(subreg:HI (ior:SI (subreg:SI (match_dup 0) 0) (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
(match_operand 1 "power_of_two_operand" "")) 0))] (match_operand 1 "power_of_two_operand" "")) 0))]
"" ""
"*
{ {
int log2 = exact_log2 (INTVAL (operands[1])); int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8) if (log2 < 8)
return \"set1 %M1,%0\"; return "set1 %M1,%0";
else else
{ {
rtx xoperands[2]; rtx xoperands[2];
...@@ -719,10 +722,10 @@ ...@@ -719,10 +722,10 @@
plus_constant (XEXP (operands[0], 0), plus_constant (XEXP (operands[0], 0),
log2 / 8)); log2 / 8));
xoperands[1] = GEN_INT (log2 % 8); xoperands[1] = GEN_INT (log2 % 8);
output_asm_insn (\"set1 %1,%0\", xoperands); output_asm_insn ("set1 %1,%0", xoperands);
} }
return \"\"; return "";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "bit1")]) (set_attr "type" "bit1")])
...@@ -733,12 +736,11 @@ ...@@ -733,12 +736,11 @@
(match_operand 1 "power_of_two_operand" ""))) (match_operand 1 "power_of_two_operand" "")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"*
{ {
int log2 = exact_log2 (INTVAL (operands[1])); int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8) if (log2 < 8)
return \"set1 %M1,%0\"; return "set1 %M1,%0";
else else
{ {
rtx xoperands[2]; rtx xoperands[2];
...@@ -746,10 +748,10 @@ ...@@ -746,10 +748,10 @@
plus_constant (XEXP (operands[0], 0), plus_constant (XEXP (operands[0], 0),
log2 / 8)); log2 / 8));
xoperands[1] = GEN_INT (log2 % 8); xoperands[1] = GEN_INT (log2 % 8);
output_asm_insn (\"set1 %1,%0\", xoperands); output_asm_insn ("set1 %1,%0", xoperands);
} }
return \"\"; return "";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "bit1")]) (set_attr "type" "bit1")])
...@@ -787,12 +789,11 @@ ...@@ -787,12 +789,11 @@
(subreg:HI (xor:SI (subreg:SI (match_dup 0) 0) (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
(match_operand 1 "power_of_two_operand" "")) 0))] (match_operand 1 "power_of_two_operand" "")) 0))]
"" ""
"*
{ {
int log2 = exact_log2 (INTVAL (operands[1])); int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8) if (log2 < 8)
return \"not1 %M1,%0\"; return "not1 %M1,%0";
else else
{ {
rtx xoperands[2]; rtx xoperands[2];
...@@ -800,10 +801,10 @@ ...@@ -800,10 +801,10 @@
plus_constant (XEXP (operands[0], 0), plus_constant (XEXP (operands[0], 0),
log2 / 8)); log2 / 8));
xoperands[1] = GEN_INT (log2 % 8); xoperands[1] = GEN_INT (log2 % 8);
output_asm_insn (\"not1 %1,%0\", xoperands); output_asm_insn ("not1 %1,%0", xoperands);
} }
return \"\"; return "";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "bit1")]) (set_attr "type" "bit1")])
...@@ -814,12 +815,11 @@ ...@@ -814,12 +815,11 @@
(match_operand 1 "power_of_two_operand" ""))) (match_operand 1 "power_of_two_operand" "")))
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"" ""
"*
{ {
int log2 = exact_log2 (INTVAL (operands[1])); int log2 = exact_log2 (INTVAL (operands[1]));
if (log2 < 8) if (log2 < 8)
return \"not1 %M1,%0\"; return "not1 %M1,%0";
else else
{ {
rtx xoperands[2]; rtx xoperands[2];
...@@ -827,10 +827,10 @@ ...@@ -827,10 +827,10 @@
plus_constant (XEXP (operands[0], 0), plus_constant (XEXP (operands[0], 0),
log2 / 8)); log2 / 8));
xoperands[1] = GEN_INT (log2 % 8); xoperands[1] = GEN_INT (log2 % 8);
output_asm_insn (\"not1 %1,%0\", xoperands); output_asm_insn ("not1 %1,%0", xoperands);
} }
return \"\"; return "";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber") (set_attr "cc" "clobber")
(set_attr "type" "bit1")]) (set_attr "type" "bit1")])
...@@ -884,7 +884,6 @@ ...@@ -884,7 +884,6 @@
(match_operator:SI 1 "comparison_operator" (match_operator:SI 1 "comparison_operator"
[(cc0) (const_int 0)]))] [(cc0) (const_int 0)]))]
"" ""
"*
{ {
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT && (GET_CODE (operands[1]) == GT
...@@ -893,8 +892,8 @@ ...@@ -893,8 +892,8 @@
|| GET_CODE (operands[1]) == LT)) || GET_CODE (operands[1]) == LT))
return 0; return 0;
return \"setf %c1,%0\"; return "setf %c1,%0";
}" }
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "none_0hit")]) (set_attr "cc" "none_0hit")])
...@@ -938,9 +937,8 @@ ...@@ -938,9 +937,8 @@
(match_operand:SI 2 "reg_or_const_operand" "rJ") (match_operand:SI 2 "reg_or_const_operand" "rJ")
(match_operand:SI 3 "reg_or_const_operand" "rI")))] (match_operand:SI 3 "reg_or_const_operand" "rI")))]
"(TARGET_V850E || TARGET_V850E2_ALL)" "(TARGET_V850E || TARGET_V850E2_ALL)"
" {
{ if ((GET_CODE (operands[2]) == CONST_INT
if ( (GET_CODE (operands[2]) == CONST_INT
&& GET_CODE (operands[3]) == CONST_INT)) && GET_CODE (operands[3]) == CONST_INT))
{ {
int o2 = INTVAL (operands[2]); int o2 = INTVAL (operands[2]);
...@@ -966,7 +964,7 @@ ...@@ -966,7 +964,7 @@
if (GET_CODE (operands[3]) != REG) if (GET_CODE (operands[3]) != REG)
operands[3] = copy_to_mode_reg (SImode, operands[3]); operands[3] = copy_to_mode_reg (SImode, operands[3]);
} }
}") })
;; ??? Clobbering the condition codes is overkill. ;; ??? Clobbering the condition codes is overkill.
...@@ -1095,8 +1093,7 @@ ...@@ -1095,8 +1093,7 @@
(ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)]) (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
(ashift:SI (match_dup 0) (const_int 1)))) (ashift:SI (match_dup 0) (const_int 1))))
(clobber (reg:CC CC_REGNUM))])] (clobber (reg:CC CC_REGNUM))])]
" {
{
operands[6] = GEN_INT (INTVAL (operands[2]) >> 1); operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
if (INTVAL (operands[2]) & 0x1) if (INTVAL (operands[2]) & 0x1)
operands[7] = operands[1]; operands[7] = operands[1];
...@@ -1104,7 +1101,7 @@ ...@@ -1104,7 +1101,7 @@
operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
GET_MODE (operands[1]), GET_MODE (operands[1]),
XEXP (operands[1], 0), XEXP (operands[1], 1)); XEXP (operands[1], 0), XEXP (operands[1], 1));
}") })
;; --------------------------------------------------------------------- ;; ---------------------------------------------------------------------
;; BYTE SWAP INSTRUCTIONS ;; BYTE SWAP INSTRUCTIONS
...@@ -1115,11 +1112,10 @@ ...@@ -1115,11 +1112,10 @@
(match_operand:HI 2 "const_int_operand" ""))) (match_operand:HI 2 "const_int_operand" "")))
(clobber (reg:CC CC_REGNUM))])] (clobber (reg:CC CC_REGNUM))])]
"(TARGET_V850E || TARGET_V850E2_ALL)" "(TARGET_V850E || TARGET_V850E2_ALL)"
" {
{
if (INTVAL (operands[2]) != 8) if (INTVAL (operands[2]) != 8)
FAIL; FAIL;
}") })
(define_insn "*rotlhi3_8" (define_insn "*rotlhi3_8"
[(set (match_operand:HI 0 "register_operand" "=r") [(set (match_operand:HI 0 "register_operand" "=r")
...@@ -1137,11 +1133,10 @@ ...@@ -1137,11 +1133,10 @@
(match_operand:SI 2 "const_int_operand" ""))) (match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC CC_REGNUM))])] (clobber (reg:CC CC_REGNUM))])]
"(TARGET_V850E || TARGET_V850E2_ALL)" "(TARGET_V850E || TARGET_V850E2_ALL)"
" {
{
if (INTVAL (operands[2]) != 16) if (INTVAL (operands[2]) != 16)
FAIL; FAIL;
}") })
(define_insn "*rotlsi3_16" (define_insn "*rotlsi3_16"
[(set (match_operand:SI 0 "register_operand" "=r") [(set (match_operand:SI 0 "register_operand" "=r")
...@@ -1166,7 +1161,6 @@ ...@@ -1166,7 +1161,6 @@
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))]
"" ""
"*
{ {
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT && (GET_CODE (operands[1]) == GT
...@@ -1176,10 +1170,10 @@ ...@@ -1176,10 +1170,10 @@
return 0; return 0;
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"b%b1 %l0\"; return "b%b1 %l0";
else else
return \"b%B1 .+6 ; jr %l0\"; return "b%B1 .+6 ; jr %l0";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc))) (if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256)) (const_int 256))
...@@ -1194,7 +1188,6 @@ ...@@ -1194,7 +1188,6 @@
(pc) (pc)
(label_ref (match_operand 0 "" ""))))] (label_ref (match_operand 0 "" ""))))]
"" ""
"*
{ {
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
&& (GET_CODE (operands[1]) == GT && (GET_CODE (operands[1]) == GT
...@@ -1203,10 +1196,10 @@ ...@@ -1203,10 +1196,10 @@
|| GET_CODE (operands[1]) == LT)) || GET_CODE (operands[1]) == LT))
return 0; return 0;
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"b%B1 %l0\"; return "b%B1 %l0";
else else
return \"b%b1 .+6 ; jr %l0\"; return "b%b1 .+6 ; jr %l0";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc))) (if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256)) (const_int 256))
...@@ -1220,13 +1213,12 @@ ...@@ -1220,13 +1213,12 @@
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))]
"TARGET_V850E2V3" "TARGET_V850E2V3"
"*
{ {
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"bz %l0\"; return "bz %l0";
else else
return \"bnz 1f ; jr %l0 ; 1:\"; return "bnz 1f ; jr %l0 ; 1:";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc))) (if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256)) (const_int 256))
...@@ -1240,13 +1232,12 @@ ...@@ -1240,13 +1232,12 @@
(pc) (pc)
(label_ref (match_operand 0 "" ""))))] (label_ref (match_operand 0 "" ""))))]
"TARGET_V850E2V3" "TARGET_V850E2V3"
"*
{ {
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"bnz %l0\"; return "bnz %l0";
else else
return \"bz 1f ; jr %l0 ; 1:\"; return "bz 1f ; jr %l0 ; 1:";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc))) (if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256)) (const_int 256))
...@@ -1260,13 +1251,12 @@ ...@@ -1260,13 +1251,12 @@
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))]
"TARGET_V850E2V3" "TARGET_V850E2V3"
"*
{ {
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"bnz %l0\"; return "bnz %l0";
else else
return \"bz 1f ; jr %l0 ; 1:\"; return "bz 1f ; jr %l0 ; 1:";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc))) (if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256)) (const_int 256))
...@@ -1280,13 +1270,12 @@ ...@@ -1280,13 +1270,12 @@
(pc) (pc)
(label_ref (match_operand 0 "" ""))))] (label_ref (match_operand 0 "" ""))))]
"TARGET_V850E2V3" "TARGET_V850E2V3"
"*
{ {
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"bz %l0\"; return "bz %l0";
else else
return \"bnz 1f ; jr %l0 ; 1:\"; return "bnz 1f ; jr %l0 ; 1:";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc))) (if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256)) (const_int 256))
...@@ -1300,13 +1289,12 @@ ...@@ -1300,13 +1289,12 @@
[(set (pc) [(set (pc)
(label_ref (match_operand 0 "" "")))] (label_ref (match_operand 0 "" "")))]
"" ""
"*
{ {
if (get_attr_length (insn) == 2) if (get_attr_length (insn) == 2)
return \"br %0\"; return "br %0";
else else
return \"jr %0\"; return "jr %0";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (lt (abs (minus (match_dup 0) (pc))) (if_then_else (lt (abs (minus (match_dup 0) (pc)))
(const_int 256)) (const_int 256))
...@@ -1349,8 +1337,7 @@ ...@@ -1349,8 +1337,7 @@
(match_operand:SI 2 "register_operand" "") (match_operand:SI 2 "register_operand" "")
(match_operand 3 "" "") (match_operand 4 "" "")] (match_operand 3 "" "") (match_operand 4 "" "")]
"" ""
" {
{
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
rtx tableaddress = gen_reg_rtx (SImode); rtx tableaddress = gen_reg_rtx (SImode);
rtx test; rtx test;
...@@ -1386,7 +1373,7 @@ ...@@ -1386,7 +1373,7 @@
/* Branch to the switch label. */ /* Branch to the switch label. */
emit_jump_insn (gen_tablejump (reg, operands[3])); emit_jump_insn (gen_tablejump (reg, operands[3]));
DONE; DONE;
}") })
;; Call subroutine with no return value. ;; Call subroutine with no return value.
...@@ -1394,8 +1381,7 @@ ...@@ -1394,8 +1381,7 @@
[(call (match_operand:QI 0 "general_operand" "") [(call (match_operand:QI 0 "general_operand" "")
(match_operand:SI 1 "general_operand" ""))] (match_operand:SI 1 "general_operand" ""))]
"" ""
" {
{
if (! call_address_operand (XEXP (operands[0], 0), QImode) if (! call_address_operand (XEXP (operands[0], 0), QImode)
|| TARGET_LONG_CALLS) || TARGET_LONG_CALLS)
XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
...@@ -1405,7 +1391,7 @@ ...@@ -1405,7 +1391,7 @@
emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1])); emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
DONE; DONE;
}") })
(define_insn "call_internal_short" (define_insn "call_internal_short"
[(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
...@@ -1424,18 +1410,17 @@ ...@@ -1424,18 +1410,17 @@
(match_operand:SI 1 "general_operand" "g,g")) (match_operand:SI 1 "general_operand" "g,g"))
(clobber (reg:SI 31))] (clobber (reg:SI 31))]
"TARGET_LONG_CALLS" "TARGET_LONG_CALLS"
"* {
{
if (which_alternative == 0) if (which_alternative == 0)
{ {
if (GET_CODE (operands[0]) == REG) if (GET_CODE (operands[0]) == REG)
return \"jarl %0,r31\"; return "jarl %0,r31";
else else
return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\"; return "movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11";
} }
else else
return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\"; return "jarl .+4,r31 ; add 4,r31 ; jmp %0";
}" }
[(set_attr "length" "16,8") [(set_attr "length" "16,8")
(set_attr "cc" "clobber,clobber")] (set_attr "cc" "clobber,clobber")]
) )
...@@ -1448,8 +1433,7 @@ ...@@ -1448,8 +1433,7 @@
(call (match_operand:QI 1 "general_operand" "") (call (match_operand:QI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))] (match_operand:SI 2 "general_operand" "")))]
"" ""
" {
{
if (! call_address_operand (XEXP (operands[1], 0), QImode) if (! call_address_operand (XEXP (operands[1], 0), QImode)
|| TARGET_LONG_CALLS) || TARGET_LONG_CALLS)
XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
...@@ -1462,7 +1446,7 @@ ...@@ -1462,7 +1446,7 @@
XEXP (operands[1], 0), XEXP (operands[1], 0),
operands[2])); operands[2]));
DONE; DONE;
}") })
(define_insn "call_value_internal_short" (define_insn "call_value_internal_short"
[(set (match_operand 0 "" "=r,r") [(set (match_operand 0 "" "=r,r")
...@@ -1483,19 +1467,18 @@ ...@@ -1483,19 +1467,18 @@
(match_operand:SI 2 "general_operand" "g,g"))) (match_operand:SI 2 "general_operand" "g,g")))
(clobber (reg:SI 31))] (clobber (reg:SI 31))]
"TARGET_LONG_CALLS" "TARGET_LONG_CALLS"
"* {
{
if (which_alternative == 0) if (which_alternative == 0)
{ {
if (GET_CODE (operands[1]) == REG) if (GET_CODE (operands[1]) == REG)
return \"jarl %1, r31\"; return "jarl %1, r31";
else else
/* Reload can generate this pattern.... */ /* Reload can generate this pattern.... */
return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\"; return "movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11";
} }
else else
return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\"; return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
}" }
[(set_attr "length" "16,8") [(set_attr "length" "16,8")
(set_attr "cc" "clobber,clobber")] (set_attr "cc" "clobber,clobber")]
) )
...@@ -1544,8 +1527,7 @@ ...@@ -1544,8 +1527,7 @@
{ {
if (! (TARGET_V850E || TARGET_V850E2_ALL)) if (! (TARGET_V850E || TARGET_V850E2_ALL))
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
} })
)
(define_insn "*zero_extendqisi2_v850e" (define_insn "*zero_extendqisi2_v850e"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r") [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
...@@ -1580,8 +1562,7 @@ ...@@ -1580,8 +1562,7 @@
{ {
if (! (TARGET_V850E || TARGET_V850E2_ALL)) if (! (TARGET_V850E || TARGET_V850E2_ALL))
operands[1] = force_reg (QImode, operands[1]); operands[1] = force_reg (QImode, operands[1]);
} })
)
;;- sign extension instructions ;;- sign extension instructions
...@@ -1612,11 +1593,10 @@ ...@@ -1612,11 +1593,10 @@
(const_int 16))) (const_int 16)))
(clobber (reg:CC CC_REGNUM))])] (clobber (reg:CC CC_REGNUM))])]
"" ""
" {
{
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_reg_rtx (SImode); operands[2] = gen_reg_rtx (SImode);
}") })
;; ??? The extendqisi2 pattern should not emit shifts for v850e? ;; ??? The extendqisi2 pattern should not emit shifts for v850e?
...@@ -1645,11 +1625,10 @@ ...@@ -1645,11 +1625,10 @@
(const_int 24))) (const_int 24)))
(clobber (reg:CC CC_REGNUM))])] (clobber (reg:CC CC_REGNUM))])]
"" ""
" {
{
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_reg_rtx (SImode); operands[2] = gen_reg_rtx (SImode);
}") })
;; ---------------------------------------------------------------------- ;; ----------------------------------------------------------------------
;; SHIFTS ;; SHIFTS
...@@ -1746,16 +1725,18 @@ ...@@ -1746,16 +1725,18 @@
(define_expand "prologue" (define_expand "prologue"
[(const_int 0)] [(const_int 0)]
"" ""
"expand_prologue (); DONE;") {
expand_prologue ();
DONE;
})
(define_expand "epilogue" (define_expand "epilogue"
[(return)] [(return)]
"" ""
" {
{
expand_epilogue (); expand_epilogue ();
DONE; DONE;
}") })
(define_insn "return_simple" (define_insn "return_simple"
[(return)] [(return)]
...@@ -2344,8 +2325,9 @@ ...@@ -2344,8 +2325,9 @@
(match_operand:SI 2 "immediate_operand" "i"))) (match_operand:SI 2 "immediate_operand" "i")))
(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
"TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
"* return construct_prepare_instruction (operands[0]); {
" return construct_prepare_instruction (operands[0]);
}
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber")]) (set_attr "cc" "clobber")])
...@@ -2357,8 +2339,9 @@ ...@@ -2357,8 +2339,9 @@
(match_operand:SI 2 "immediate_operand" "i"))) (match_operand:SI 2 "immediate_operand" "i")))
(match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
"TARGET_PROLOG_FUNCTION" "TARGET_PROLOG_FUNCTION"
"* return construct_save_jarl (operands[0]); {
" return construct_save_jarl (operands[0]);
}
[(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
(const_string "16") (const_string "16")
(const_string "4"))) (const_string "4")))
...@@ -2376,8 +2359,9 @@ ...@@ -2376,8 +2359,9 @@
(mem:SI (plus:SI (reg:SI 3) (mem:SI (plus:SI (reg:SI 3)
(match_operand:SI 3 "immediate_operand" "i"))))])] (match_operand:SI 3 "immediate_operand" "i"))))])]
"TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
"* return construct_dispose_instruction (operands[0]); {
" return construct_dispose_instruction (operands[0]);
}
[(set_attr "length" "4") [(set_attr "length" "4")
(set_attr "cc" "clobber")]) (set_attr "cc" "clobber")])
...@@ -2394,8 +2378,9 @@ ...@@ -2394,8 +2378,9 @@
(mem:SI (plus:SI (reg:SI 3) (mem:SI (plus:SI (reg:SI 3)
(match_operand:SI 3 "immediate_operand" "i"))))])] (match_operand:SI 3 "immediate_operand" "i"))))])]
"TARGET_PROLOG_FUNCTION" "TARGET_PROLOG_FUNCTION"
"* return construct_restore_jr (operands[0]); {
" return construct_restore_jr (operands[0]);
}
[(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
(const_string "12") (const_string "12")
(const_string "4"))) (const_string "4")))
...@@ -2409,19 +2394,18 @@ ...@@ -2409,19 +2394,18 @@
;; without saving its previous value. So if the interrupt handler ;; without saving its previous value. So if the interrupt handler
;; or its caller could possibly execute the CALLT insn, save_interrupt ;; or its caller could possibly execute the CALLT insn, save_interrupt
;; MUST NOT be called via CALLT. ;; MUST NOT be called via CALLT.
"*
{ {
output_asm_insn (\"addi -28, sp, sp\", operands); output_asm_insn ("addi -28, sp, sp", operands);
output_asm_insn (\"st.w r1, 24[sp]\", operands); output_asm_insn ("st.w r1, 24[sp]", operands);
output_asm_insn (\"st.w r10, 12[sp]\", operands); output_asm_insn ("st.w r10, 12[sp]", operands);
output_asm_insn (\"st.w r11, 16[sp]\", operands); output_asm_insn ("st.w r11, 16[sp]", operands);
output_asm_insn (\"stsr ctpc, r10\", operands); output_asm_insn ("stsr ctpc, r10", operands);
output_asm_insn (\"st.w r10, 20[sp]\", operands); output_asm_insn ("st.w r10, 20[sp]", operands);
output_asm_insn (\"stsr ctpsw, r10\", operands); output_asm_insn ("stsr ctpsw, r10", operands);
output_asm_insn (\"st.w r10, 24[sp]\", operands); output_asm_insn ("st.w r10, 24[sp]", operands);
output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands); output_asm_insn ("callt ctoff(__callt_save_interrupt)", operands);
return \"\"; return "";
}" }
[(set_attr "length" "26") [(set_attr "length" "26")
(set_attr "cc" "clobber")]) (set_attr "cc" "clobber")])
...@@ -2440,25 +2424,24 @@ ...@@ -2440,25 +2424,24 @@
(set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10)) (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10))
(set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))] (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))]
"" ""
"*
{ {
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
return \"addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10\"; return "addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10";
else else
{ {
output_asm_insn (\"addi -20, sp, sp\", operands); output_asm_insn ("addi -20, sp, sp", operands);
output_asm_insn (\"st.w r11, 16[sp]\", operands); output_asm_insn ("st.w r11, 16[sp]", operands);
output_asm_insn (\"st.w r10, 12[sp]\", operands); output_asm_insn ("st.w r10, 12[sp]", operands);
output_asm_insn (\"st.w ep, 0[sp]\", operands); output_asm_insn ("st.w ep, 0[sp]", operands);
output_asm_insn (\"st.w gp, 4[sp]\", operands); output_asm_insn ("st.w gp, 4[sp]", operands);
output_asm_insn (\"st.w r1, 8[sp]\", operands); output_asm_insn ("st.w r1, 8[sp]", operands);
output_asm_insn (\"movhi hi(__ep), r0, ep\", operands); output_asm_insn ("movhi hi(__ep), r0, ep", operands);
output_asm_insn (\"movea lo(__ep), ep, ep\", operands); output_asm_insn ("movea lo(__ep), ep, ep", operands);
output_asm_insn (\"movhi hi(__gp), r0, gp\", operands); output_asm_insn ("movhi hi(__gp), r0, gp", operands);
output_asm_insn (\"movea lo(__gp), gp, gp\", operands); output_asm_insn ("movea lo(__gp), gp, gp", operands);
return \"\"; return "";
} }
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS") (if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 10) (const_int 10)
...@@ -2475,22 +2458,21 @@ ...@@ -2475,22 +2458,21 @@
(set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4)))) (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
(set (reg:SI 30) (mem:SI (reg:SI 3)))] (set (reg:SI 30) (mem:SI (reg:SI 3)))]
"" ""
"*
{ {
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
return \"jr __return_interrupt\"; return "jr __return_interrupt";
else else
{ {
output_asm_insn (\"ld.w 0[sp], ep\", operands); output_asm_insn ("ld.w 0[sp], ep", operands);
output_asm_insn (\"ld.w 4[sp], gp\", operands); output_asm_insn ("ld.w 4[sp], gp", operands);
output_asm_insn (\"ld.w 8[sp], r1\", operands); output_asm_insn ("ld.w 8[sp], r1", operands);
output_asm_insn (\"ld.w 12[sp], r10\", operands); output_asm_insn ("ld.w 12[sp], r10", operands);
output_asm_insn (\"ld.w 16[sp], r11\", operands); output_asm_insn ("ld.w 16[sp], r11", operands);
output_asm_insn (\"addi 20, sp, sp\", operands); output_asm_insn ("addi 20, sp, sp", operands);
output_asm_insn (\"reti\", operands); output_asm_insn ("reti", operands);
return \"\"; return "";
} }
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS") (if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4) (const_int 4)
...@@ -2514,77 +2496,76 @@ ...@@ -2514,77 +2496,76 @@
(define_insn "save_all_interrupt" (define_insn "save_all_interrupt"
[(unspec_volatile [(const_int 0)] 0)] [(unspec_volatile [(const_int 0)] 0)]
"" ""
"*
{ {
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
return \"jarl __save_all_interrupt,r10\"; return "jarl __save_all_interrupt,r10";
output_asm_insn (\"addi -120, sp, sp\", operands); output_asm_insn ("addi -120, sp, sp", operands);
if (TARGET_EP) if (TARGET_EP)
{ {
output_asm_insn (\"mov ep, r1\", operands); output_asm_insn ("mov ep, r1", operands);
output_asm_insn (\"mov sp, ep\", operands); output_asm_insn ("mov sp, ep", operands);
output_asm_insn (\"sst.w r31, 116[ep]\", operands); output_asm_insn ("sst.w r31, 116[ep]", operands);
output_asm_insn (\"sst.w r2, 112[ep]\", operands); output_asm_insn ("sst.w r2, 112[ep]", operands);
output_asm_insn (\"sst.w gp, 108[ep]\", operands); output_asm_insn ("sst.w gp, 108[ep]", operands);
output_asm_insn (\"sst.w r6, 104[ep]\", operands); output_asm_insn ("sst.w r6, 104[ep]", operands);
output_asm_insn (\"sst.w r7, 100[ep]\", operands); output_asm_insn ("sst.w r7, 100[ep]", operands);
output_asm_insn (\"sst.w r8, 96[ep]\", operands); output_asm_insn ("sst.w r8, 96[ep]", operands);
output_asm_insn (\"sst.w r9, 92[ep]\", operands); output_asm_insn ("sst.w r9, 92[ep]", operands);
output_asm_insn (\"sst.w r11, 88[ep]\", operands); output_asm_insn ("sst.w r11, 88[ep]", operands);
output_asm_insn (\"sst.w r12, 84[ep]\", operands); output_asm_insn ("sst.w r12, 84[ep]", operands);
output_asm_insn (\"sst.w r13, 80[ep]\", operands); output_asm_insn ("sst.w r13, 80[ep]", operands);
output_asm_insn (\"sst.w r14, 76[ep]\", operands); output_asm_insn ("sst.w r14, 76[ep]", operands);
output_asm_insn (\"sst.w r15, 72[ep]\", operands); output_asm_insn ("sst.w r15, 72[ep]", operands);
output_asm_insn (\"sst.w r16, 68[ep]\", operands); output_asm_insn ("sst.w r16, 68[ep]", operands);
output_asm_insn (\"sst.w r17, 64[ep]\", operands); output_asm_insn ("sst.w r17, 64[ep]", operands);
output_asm_insn (\"sst.w r18, 60[ep]\", operands); output_asm_insn ("sst.w r18, 60[ep]", operands);
output_asm_insn (\"sst.w r19, 56[ep]\", operands); output_asm_insn ("sst.w r19, 56[ep]", operands);
output_asm_insn (\"sst.w r20, 52[ep]\", operands); output_asm_insn ("sst.w r20, 52[ep]", operands);
output_asm_insn (\"sst.w r21, 48[ep]\", operands); output_asm_insn ("sst.w r21, 48[ep]", operands);
output_asm_insn (\"sst.w r22, 44[ep]\", operands); output_asm_insn ("sst.w r22, 44[ep]", operands);
output_asm_insn (\"sst.w r23, 40[ep]\", operands); output_asm_insn ("sst.w r23, 40[ep]", operands);
output_asm_insn (\"sst.w r24, 36[ep]\", operands); output_asm_insn ("sst.w r24, 36[ep]", operands);
output_asm_insn (\"sst.w r25, 32[ep]\", operands); output_asm_insn ("sst.w r25, 32[ep]", operands);
output_asm_insn (\"sst.w r26, 28[ep]\", operands); output_asm_insn ("sst.w r26, 28[ep]", operands);
output_asm_insn (\"sst.w r27, 24[ep]\", operands); output_asm_insn ("sst.w r27, 24[ep]", operands);
output_asm_insn (\"sst.w r28, 20[ep]\", operands); output_asm_insn ("sst.w r28, 20[ep]", operands);
output_asm_insn (\"sst.w r29, 16[ep]\", operands); output_asm_insn ("sst.w r29, 16[ep]", operands);
output_asm_insn (\"mov r1, ep\", operands); output_asm_insn ("mov r1, ep", operands);
} }
else else
{ {
output_asm_insn (\"st.w r31, 116[sp]\", operands); output_asm_insn ("st.w r31, 116[sp]", operands);
output_asm_insn (\"st.w r2, 112[sp]\", operands); output_asm_insn ("st.w r2, 112[sp]", operands);
output_asm_insn (\"st.w gp, 108[sp]\", operands); output_asm_insn ("st.w gp, 108[sp]", operands);
output_asm_insn (\"st.w r6, 104[sp]\", operands); output_asm_insn ("st.w r6, 104[sp]", operands);
output_asm_insn (\"st.w r7, 100[sp]\", operands); output_asm_insn ("st.w r7, 100[sp]", operands);
output_asm_insn (\"st.w r8, 96[sp]\", operands); output_asm_insn ("st.w r8, 96[sp]", operands);
output_asm_insn (\"st.w r9, 92[sp]\", operands); output_asm_insn ("st.w r9, 92[sp]", operands);
output_asm_insn (\"st.w r11, 88[sp]\", operands); output_asm_insn ("st.w r11, 88[sp]", operands);
output_asm_insn (\"st.w r12, 84[sp]\", operands); output_asm_insn ("st.w r12, 84[sp]", operands);
output_asm_insn (\"st.w r13, 80[sp]\", operands); output_asm_insn ("st.w r13, 80[sp]", operands);
output_asm_insn (\"st.w r14, 76[sp]\", operands); output_asm_insn ("st.w r14, 76[sp]", operands);
output_asm_insn (\"st.w r15, 72[sp]\", operands); output_asm_insn ("st.w r15, 72[sp]", operands);
output_asm_insn (\"st.w r16, 68[sp]\", operands); output_asm_insn ("st.w r16, 68[sp]", operands);
output_asm_insn (\"st.w r17, 64[sp]\", operands); output_asm_insn ("st.w r17, 64[sp]", operands);
output_asm_insn (\"st.w r18, 60[sp]\", operands); output_asm_insn ("st.w r18, 60[sp]", operands);
output_asm_insn (\"st.w r19, 56[sp]\", operands); output_asm_insn ("st.w r19, 56[sp]", operands);
output_asm_insn (\"st.w r20, 52[sp]\", operands); output_asm_insn ("st.w r20, 52[sp]", operands);
output_asm_insn (\"st.w r21, 48[sp]\", operands); output_asm_insn ("st.w r21, 48[sp]", operands);
output_asm_insn (\"st.w r22, 44[sp]\", operands); output_asm_insn ("st.w r22, 44[sp]", operands);
output_asm_insn (\"st.w r23, 40[sp]\", operands); output_asm_insn ("st.w r23, 40[sp]", operands);
output_asm_insn (\"st.w r24, 36[sp]\", operands); output_asm_insn ("st.w r24, 36[sp]", operands);
output_asm_insn (\"st.w r25, 32[sp]\", operands); output_asm_insn ("st.w r25, 32[sp]", operands);
output_asm_insn (\"st.w r26, 28[sp]\", operands); output_asm_insn ("st.w r26, 28[sp]", operands);
output_asm_insn (\"st.w r27, 24[sp]\", operands); output_asm_insn ("st.w r27, 24[sp]", operands);
output_asm_insn (\"st.w r28, 20[sp]\", operands); output_asm_insn ("st.w r28, 20[sp]", operands);
output_asm_insn (\"st.w r29, 16[sp]\", operands); output_asm_insn ("st.w r29, 16[sp]", operands);
} }
return \"\"; return "";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS") (if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4) (const_int 4)
...@@ -2615,75 +2596,74 @@ ...@@ -2615,75 +2596,74 @@
(define_insn "restore_all_interrupt" (define_insn "restore_all_interrupt"
[(unspec_volatile [(const_int 0)] 1)] [(unspec_volatile [(const_int 0)] 1)]
"" ""
"*
{ {
if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
return \"jarl __restore_all_interrupt,r10\"; return "jarl __restore_all_interrupt,r10";
if (TARGET_EP) if (TARGET_EP)
{ {
output_asm_insn (\"mov ep, r1\", operands); output_asm_insn ("mov ep, r1", operands);
output_asm_insn (\"mov sp, ep\", operands); output_asm_insn ("mov sp, ep", operands);
output_asm_insn (\"sld.w 116[ep], r31\", operands); output_asm_insn ("sld.w 116[ep], r31", operands);
output_asm_insn (\"sld.w 112[ep], r2\", operands); output_asm_insn ("sld.w 112[ep], r2", operands);
output_asm_insn (\"sld.w 108[ep], gp\", operands); output_asm_insn ("sld.w 108[ep], gp", operands);
output_asm_insn (\"sld.w 104[ep], r6\", operands); output_asm_insn ("sld.w 104[ep], r6", operands);
output_asm_insn (\"sld.w 100[ep], r7\", operands); output_asm_insn ("sld.w 100[ep], r7", operands);
output_asm_insn (\"sld.w 96[ep], r8\", operands); output_asm_insn ("sld.w 96[ep], r8", operands);
output_asm_insn (\"sld.w 92[ep], r9\", operands); output_asm_insn ("sld.w 92[ep], r9", operands);
output_asm_insn (\"sld.w 88[ep], r11\", operands); output_asm_insn ("sld.w 88[ep], r11", operands);
output_asm_insn (\"sld.w 84[ep], r12\", operands); output_asm_insn ("sld.w 84[ep], r12", operands);
output_asm_insn (\"sld.w 80[ep], r13\", operands); output_asm_insn ("sld.w 80[ep], r13", operands);
output_asm_insn (\"sld.w 76[ep], r14\", operands); output_asm_insn ("sld.w 76[ep], r14", operands);
output_asm_insn (\"sld.w 72[ep], r15\", operands); output_asm_insn ("sld.w 72[ep], r15", operands);
output_asm_insn (\"sld.w 68[ep], r16\", operands); output_asm_insn ("sld.w 68[ep], r16", operands);
output_asm_insn (\"sld.w 64[ep], r17\", operands); output_asm_insn ("sld.w 64[ep], r17", operands);
output_asm_insn (\"sld.w 60[ep], r18\", operands); output_asm_insn ("sld.w 60[ep], r18", operands);
output_asm_insn (\"sld.w 56[ep], r19\", operands); output_asm_insn ("sld.w 56[ep], r19", operands);
output_asm_insn (\"sld.w 52[ep], r20\", operands); output_asm_insn ("sld.w 52[ep], r20", operands);
output_asm_insn (\"sld.w 48[ep], r21\", operands); output_asm_insn ("sld.w 48[ep], r21", operands);
output_asm_insn (\"sld.w 44[ep], r22\", operands); output_asm_insn ("sld.w 44[ep], r22", operands);
output_asm_insn (\"sld.w 40[ep], r23\", operands); output_asm_insn ("sld.w 40[ep], r23", operands);
output_asm_insn (\"sld.w 36[ep], r24\", operands); output_asm_insn ("sld.w 36[ep], r24", operands);
output_asm_insn (\"sld.w 32[ep], r25\", operands); output_asm_insn ("sld.w 32[ep], r25", operands);
output_asm_insn (\"sld.w 28[ep], r26\", operands); output_asm_insn ("sld.w 28[ep], r26", operands);
output_asm_insn (\"sld.w 24[ep], r27\", operands); output_asm_insn ("sld.w 24[ep], r27", operands);
output_asm_insn (\"sld.w 20[ep], r28\", operands); output_asm_insn ("sld.w 20[ep], r28", operands);
output_asm_insn (\"sld.w 16[ep], r29\", operands); output_asm_insn ("sld.w 16[ep], r29", operands);
output_asm_insn (\"mov r1, ep\", operands); output_asm_insn ("mov r1, ep", operands);
} }
else else
{ {
output_asm_insn (\"ld.w 116[sp], r31\", operands); output_asm_insn ("ld.w 116[sp], r31", operands);
output_asm_insn (\"ld.w 112[sp], r2\", operands); output_asm_insn ("ld.w 112[sp], r2", operands);
output_asm_insn (\"ld.w 108[sp], gp\", operands); output_asm_insn ("ld.w 108[sp], gp", operands);
output_asm_insn (\"ld.w 104[sp], r6\", operands); output_asm_insn ("ld.w 104[sp], r6", operands);
output_asm_insn (\"ld.w 100[sp], r7\", operands); output_asm_insn ("ld.w 100[sp], r7", operands);
output_asm_insn (\"ld.w 96[sp], r8\", operands); output_asm_insn ("ld.w 96[sp], r8", operands);
output_asm_insn (\"ld.w 92[sp], r9\", operands); output_asm_insn ("ld.w 92[sp], r9", operands);
output_asm_insn (\"ld.w 88[sp], r11\", operands); output_asm_insn ("ld.w 88[sp], r11", operands);
output_asm_insn (\"ld.w 84[sp], r12\", operands); output_asm_insn ("ld.w 84[sp], r12", operands);
output_asm_insn (\"ld.w 80[sp], r13\", operands); output_asm_insn ("ld.w 80[sp], r13", operands);
output_asm_insn (\"ld.w 76[sp], r14\", operands); output_asm_insn ("ld.w 76[sp], r14", operands);
output_asm_insn (\"ld.w 72[sp], r15\", operands); output_asm_insn ("ld.w 72[sp], r15", operands);
output_asm_insn (\"ld.w 68[sp], r16\", operands); output_asm_insn ("ld.w 68[sp], r16", operands);
output_asm_insn (\"ld.w 64[sp], r17\", operands); output_asm_insn ("ld.w 64[sp], r17", operands);
output_asm_insn (\"ld.w 60[sp], r18\", operands); output_asm_insn ("ld.w 60[sp], r18", operands);
output_asm_insn (\"ld.w 56[sp], r19\", operands); output_asm_insn ("ld.w 56[sp], r19", operands);
output_asm_insn (\"ld.w 52[sp], r20\", operands); output_asm_insn ("ld.w 52[sp], r20", operands);
output_asm_insn (\"ld.w 48[sp], r21\", operands); output_asm_insn ("ld.w 48[sp], r21", operands);
output_asm_insn (\"ld.w 44[sp], r22\", operands); output_asm_insn ("ld.w 44[sp], r22", operands);
output_asm_insn (\"ld.w 40[sp], r23\", operands); output_asm_insn ("ld.w 40[sp], r23", operands);
output_asm_insn (\"ld.w 36[sp], r24\", operands); output_asm_insn ("ld.w 36[sp], r24", operands);
output_asm_insn (\"ld.w 32[sp], r25\", operands); output_asm_insn ("ld.w 32[sp], r25", operands);
output_asm_insn (\"ld.w 28[sp], r26\", operands); output_asm_insn ("ld.w 28[sp], r26", operands);
output_asm_insn (\"ld.w 24[sp], r27\", operands); output_asm_insn ("ld.w 24[sp], r27", operands);
output_asm_insn (\"ld.w 20[sp], r28\", operands); output_asm_insn ("ld.w 20[sp], r28", operands);
output_asm_insn (\"ld.w 16[sp], r29\", operands); output_asm_insn ("ld.w 16[sp], r29", operands);
} }
output_asm_insn (\"addi 120, sp, sp\", operands); output_asm_insn ("addi 120, sp, sp", operands);
return \"\"; return "";
}" }
[(set (attr "length") [(set (attr "length")
(if_then_else (match_test "TARGET_LONG_CALLS") (if_then_else (match_test "TARGET_LONG_CALLS")
(const_int 4) (const_int 4)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment