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riscv-gcc-1
Commit d8700b1c by Uros Bizjak
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sse.md (VI): New mode iterator. 

	* config/i386/sse.md (VI): New mode iterator.
	(SSEMODEI): Remove.
	(AVX256MODEI): Ditto.
	(AVXMODEF4P): Ditto.
	(avxvecpsmode): Ditto.
	(one_cmpl<mode>2): Enable for TARGET_SSE.  Use VI mode iterator.
	(sse2_andnot<mode>3): New expander.
	(*andnot<mode>3): Merge with *sse2_andnot<mode>3 and
	*avx_andnot<mode>3.  Enable for TARGET_SSE.  Use VI mode iterator.
	(<any_logic:code><mode>3): Use VI mode iterator.
	(*<any_logic:code><mode>3): Merge with *sse2_<any_logic:code><mode>3
	and *avx_<any_logic:code><mode>3.  Use VI mode iterator.
	(*andnottf3): Handle AVX three-operand constraints.
	(*<any_logic:code>tf3): Handle AVX three-operand constraints.

From-SVN: r172280
parent b1372d5d
Showing with 151 additions and 125 deletions
gcc/ChangeLog
2011-04-12 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (VI): New mode iterator.
(SSEMODEI): Remove.
(AVX256MODEI): Ditto.
(AVXMODEF4P): Ditto.
(avxvecpsmode): Ditto.
(one_cmpl<mode>2): Enable for TARGET_SSE. Use VI mode iterator.
(sse2_andnot<mode>3): New expander.
(*andnot<mode>3): Merge with *sse2_andnot<mode>3 and
*avx_andnot<mode>3. Enable for TARGET_SSE. Use VI mode iterator.
(<any_logic:code><mode>3): Use VI mode iterator.
(*<any_logic:code><mode>3): Merge with *sse2_<any_logic:code><mode>3
and *avx_<any_logic:code><mode>3. Use VI mode iterator.
(*andnottf3): Handle AVX three-operand constraints.
(*<any_logic:code>tf3): Handle AVX three-operand constraints.
2011-04-11 Joseph Myers <joseph@codesourcery.com> 2011-04-11 Joseph Myers <joseph@codesourcery.com>
Robert Millan <rmh@gnu.org> Robert Millan <rmh@gnu.org>
* config.gcc (x86_64-*-kfreebsd*-gnu): Use i386/kfreebsd-gnu.h. * config.gcc (x86_64-*-kfreebsd*-gnu): Use i386/kfreebsd-gnu.h.
* config/i386/kfreebsd-gnu.h (GNU_USER_DYNAMIC_LINKER32, * config/i386/kfreebsd-gnu.h (GNU_USER_DYNAMIC_LINKER32,
...@@ -9,8 +26,7 @@ ...@@ -9,8 +26,7 @@
* config/i386/knetbsd-gnu.h (GNU_USER_LINK_EMULATION): Define. * config/i386/knetbsd-gnu.h (GNU_USER_LINK_EMULATION): Define.
(REG_NAME): Don't undefine. (REG_NAME): Don't undefine.
(MD_UNWIND_SUPPORT): Undefine. (MD_UNWIND_SUPPORT): Undefine.
* config/i386/kopensolaris-gnu.h (GNU_USER_LINK_EMULATION): * config/i386/kopensolaris-gnu.h (GNU_USER_LINK_EMULATION): Define.
Define.
2011-04-11 Joseph Myers <joseph@codesourcery.com> 2011-04-11 Joseph Myers <joseph@codesourcery.com>
...@@ -110,8 +126,7 @@ ...@@ -110,8 +126,7 @@
LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS. LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS.
* config/pa/pa-linux.h (TARGET_OS_CPP_BUILTINS): Change * config/pa/pa-linux.h (TARGET_OS_CPP_BUILTINS): Change
LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS. LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS.
(LINK_SPEC): Change LINUX_DYNAMIC_LINKER to (LINK_SPEC): Change LINUX_DYNAMIC_LINKER to GNU_USER_DYNAMIC_LINKER.
GNU_USER_DYNAMIC_LINKER.
* config/rs6000/linux64.h (LINUX_DYNAMIC_LINKER32): Rename to * config/rs6000/linux64.h (LINUX_DYNAMIC_LINKER32): Rename to
GNU_USER_DYNAMIC_LINKER32. GNU_USER_DYNAMIC_LINKER32.
(LINUX_DYNAMIC_LINKER64): Rename to GNU_USER_DYNAMIC_LINKER64. (LINUX_DYNAMIC_LINKER64): Rename to GNU_USER_DYNAMIC_LINKER64.
...@@ -142,8 +157,7 @@ ...@@ -142,8 +157,7 @@
LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS. LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS.
* config/xtensa/linux.h (TARGET_OS_CPP_BUILTINS): Change * config/xtensa/linux.h (TARGET_OS_CPP_BUILTINS): Change
LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS. LINUX_TARGET_OS_CPP_BUILTINS to GNU_USER_TARGET_OS_CPP_BUILTINS.
(LINK_SPEC): Change LINUX_DYNAMIC_LINKER to (LINK_SPEC): Change LINUX_DYNAMIC_LINKER to GNU_USER_DYNAMIC_LINKER.
GNU_USER_DYNAMIC_LINKER.
2011-04-11 Joseph Myers <joseph@codesourcery.com> 2011-04-11 Joseph Myers <joseph@codesourcery.com>
...@@ -194,8 +208,7 @@ ...@@ -194,8 +208,7 @@
* config.gcc (i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | * config.gcc (i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu |
i[34567]86-*-knetbsd*-gnu | i[34567]86-*-gnu* | i[34567]86-*-knetbsd*-gnu | i[34567]86-*-gnu* |
i[34567]86-*-kopensolaris*-gnu, x86_64-*-linux* | i[34567]86-*-kopensolaris*-gnu, x86_64-*-linux* |
x86_64-*-kfreebsd*-gnu | x86_64-*-knetbsd*-gnu): Use the new x86_64-*-kfreebsd*-gnu | x86_64-*-knetbsd*-gnu): Use the new headers.
headers.
2011-04-11 Kai Tietz <ktietz@redhat.com> 2011-04-11 Kai Tietz <ktietz@redhat.com>
......
gcc/config/i386/sse.md
...@@ -36,6 +36,13 @@ ...@@ -36,6 +36,13 @@
(define_mode_iterator VF_128 (define_mode_iterator VF_128
[(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")]) [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE2")])
;; All vector integer modes
(define_mode_iterator VI
[(V32QI "TARGET_AVX") V16QI
(V16HI "TARGET_AVX") V8HI
(V8SI "TARGET_AVX") V4SI
(V4DI "TARGET_AVX") V2DI])
;; All 128bit vector integer modes ;; All 128bit vector integer modes
(define_mode_iterator VI_128 [V16QI V8HI V4SI V2DI]) (define_mode_iterator VI_128 [V16QI V8HI V4SI V2DI])
...@@ -50,16 +57,10 @@ ...@@ -50,16 +57,10 @@
;; Instruction suffix for sign and zero extensions. ;; Instruction suffix for sign and zero extensions.
(define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")]) (define_code_attr extsuffix [(sign_extend "sx") (zero_extend "zx")])
;; 16 byte integral modes handled by SSE
(define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
;; All 16-byte vector modes handled by SSE ;; All 16-byte vector modes handled by SSE
(define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF]) (define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
(define_mode_iterator SSEMODE16 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF]) (define_mode_iterator SSEMODE16 [V16QI V8HI V4SI V2DI V1TI V4SF V2DF])
;; 32 byte integral vector modes handled by AVX
(define_mode_iterator AVX256MODEI [V32QI V16HI V8SI V4DI])
;; All 32-byte vector modes handled by AVX ;; All 32-byte vector modes handled by AVX
(define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF]) (define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF])
...@@ -86,7 +87,6 @@ ...@@ -86,7 +87,6 @@
(define_mode_iterator AVX256MODE4P [V4DI V4DF]) (define_mode_iterator AVX256MODE4P [V4DI V4DF])
(define_mode_iterator AVX256MODE8P [V8SI V8SF]) (define_mode_iterator AVX256MODE8P [V8SI V8SF])
(define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF]) (define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF])
(define_mode_iterator AVXMODEF4P [V4SF V4DF])
(define_mode_iterator AVXMODEFDP [V2DF V4DF]) (define_mode_iterator AVXMODEFDP [V2DF V4DF])
(define_mode_iterator AVXMODEFSP [V4SF V8SF]) (define_mode_iterator AVXMODEFSP [V4SF V8SF])
...@@ -160,9 +160,6 @@ ...@@ -160,9 +160,6 @@
[(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI") [(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI")
(V4SF "V4SF") (V8SF "V8SF") (V2DF "V2DF") (V4DF "V4DF") (V4SF "V4SF") (V8SF "V8SF") (V2DF "V2DF") (V4DF "V4DF")
(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")]) (V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")])
(define_mode_attr avxvecpsmode
[(V16QI "V4SF") (V8HI "V4SF") (V4SI "V4SF") (V2DI "V4SF")
(V32QI "V8SF") (V16HI "V8SF") (V8SI "V8SF") (V4DI "V8SF")])
(define_mode_attr avxhalfvecmode (define_mode_attr avxhalfvecmode
[(V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI") (V4DI "V2DI") [(V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI") (V4DI "V2DI")
(V8SF "V4SF") (V4DF "V2DF") (V8SF "V4SF") (V4DF "V2DF")
...@@ -5775,10 +5772,10 @@ ...@@ -5775,10 +5772,10 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "one_cmpl<mode>2" (define_expand "one_cmpl<mode>2"
[(set (match_operand:SSEMODEI 0 "register_operand" "") [(set (match_operand:VI 0 "register_operand" "")
(xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "") (xor:VI (match_operand:VI 1 "nonimmediate_operand" "")
(match_dup 2)))] (match_dup 2)))]
"TARGET_SSE2" "TARGET_SSE"
{ {
int i, n = GET_MODE_NUNITS (<MODE>mode); int i, n = GET_MODE_NUNITS (<MODE>mode);
rtvec v = rtvec_alloc (n); rtvec v = rtvec_alloc (n);
...@@ -5789,112 +5786,123 @@ ...@@ -5789,112 +5786,123 @@
operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v)); operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
}) })
(define_insn "*avx_andnot<mode>3" (define_expand "sse2_andnot<mode>3"
[(set (match_operand:AVX256MODEI 0 "register_operand" "=x") [(set (match_operand:VI_128 0 "register_operand" "")
(and:AVX256MODEI (and:VI_128
(not:AVX256MODEI (match_operand:AVX256MODEI 1 "register_operand" "x")) (not:VI_128 (match_operand:VI_128 1 "register_operand" ""))
(match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))] (match_operand:VI_128 2 "nonimmediate_operand" "")))]
"TARGET_AVX" "TARGET_SSE2")
"vandnps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecpsmode>")])
(define_insn "*sse_andnot<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(and:SSEMODEI
(not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)"
"andnps\t{%2, %0|%0, %2}"
[(set_attr "type" "sselog")
(set_attr "mode" "V4SF")])
(define_insn "*avx_andnot<mode>3" (define_insn "*andnot<mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x") [(set (match_operand:VI 0 "register_operand" "=x,x")
(and:SSEMODEI (and:VI
(not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "x")) (not:VI (match_operand:VI 1 "register_operand" "0,x"))
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] (match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_AVX" "TARGET_SSE"
"vpandn\t{%2, %1, %0|%0, %1, %2}" {
[(set_attr "type" "sselog") static char buf[32];
(set_attr "prefix" "vex") const char *ops;
(set_attr "mode" "TI")]) const char *tmp
= (get_attr_mode (insn) == MODE_TI) ? "pandn" : "andnps";
(define_insn "sse2_andnot<mode>3" switch (which_alternative)
[(set (match_operand:SSEMODEI 0 "register_operand" "=x") {
(and:SSEMODEI case 0:
(not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0")) ops = "%s\t{%%2, %%0|%%0, %%2}";
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] break;
"TARGET_SSE2" case 1:
"pandn\t{%2, %0|%0, %2}" ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
[(set_attr "type" "sselog") break;
(set_attr "prefix_data16" "1") default:
(set_attr "mode" "TI")]) gcc_unreachable ();
}
(define_insn "*andnottf3" snprintf (buf, sizeof (buf), ops, tmp);
[(set (match_operand:TF 0 "register_operand" "=x") return buf;
(and:TF }
(not:TF (match_operand:TF 1 "register_operand" "0")) [(set_attr "isa" "noavx,avx")
(match_operand:TF 2 "nonimmediate_operand" "xm")))] (set_attr "type" "sselog")
"TARGET_SSE2" (set (attr "prefix_data16")
"pandn\t{%2, %0|%0, %2}" (if_then_else
[(set_attr "type" "sselog") (and (eq_attr "alternative" "0")
(set_attr "prefix_data16" "1") (eq_attr "mode" "TI"))
(set_attr "mode" "TI")]) (const_string "1")
(const_string "*")))
(set_attr "prefix" "orig,vex")
(set (attr "mode")
(cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
(const_string "V8SF")
(ne (symbol_ref "TARGET_SSE2") (const_int 0))
(const_string "TI")
]
(const_string "V4SF")))])
(define_expand "<code><mode>3" (define_expand "<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "") [(set (match_operand:VI 0 "register_operand" "")
(any_logic:SSEMODEI (any_logic:VI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "") (match_operand:VI 1 "nonimmediate_operand" "")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] (match_operand:VI 2 "nonimmediate_operand" "")))]
"TARGET_SSE" "TARGET_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*avx_<code><mode>3" (define_insn "*<code><mode>3"
[(set (match_operand:AVX256MODEI 0 "register_operand" "=x") [(set (match_operand:VI 0 "register_operand" "=x,x")
(any_logic:AVX256MODEI (any_logic:VI
(match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x") (match_operand:VI 1 "nonimmediate_operand" "%0,x")
(match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))] (match_operand:VI 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_AVX "TARGET_SSE
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sselog")
(set_attr "prefix" "vex")
(set_attr "mode" "<avxvecpsmode>")])
(define_insn "*sse_<code><mode>3"
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
(any_logic:SSEMODEI
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
"(TARGET_SSE && !TARGET_SSE2)
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"<logic>ps\t{%2, %0|%0, %2}" {
[(set_attr "type" "sselog") static char buf[32];
(set_attr "mode" "V4SF")]) const char *ops;
const char *tmp
= (get_attr_mode (insn) == MODE_TI) ? "p<logic>" : "<logic>ps";
(define_insn "*avx_<code><mode>3" switch (which_alternative)
[(set (match_operand:SSEMODEI 0 "register_operand" "=x") {
(any_logic:SSEMODEI case 0:
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%x") ops = "%s\t{%%2, %%0|%%0, %%2}";
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] break;
"TARGET_AVX case 1:
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
"vp<logic>\t{%2, %1, %0|%0, %1, %2}" break;
[(set_attr "type" "sselog") default:
(set_attr "prefix" "vex") gcc_unreachable ();
(set_attr "mode" "TI")]) }
(define_insn "*sse2_<code><mode>3" snprintf (buf, sizeof (buf), ops, tmp);
[(set (match_operand:SSEMODEI 0 "register_operand" "=x") return buf;
(any_logic:SSEMODEI }
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") [(set_attr "isa" "noavx,avx")
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] (set_attr "type" "sselog")
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" (set (attr "prefix_data16")
"p<logic>\t{%2, %0|%0, %2}" (if_then_else
[(set_attr "type" "sselog") (and (eq_attr "alternative" "0")
(set_attr "prefix_data16" "1") (eq_attr "mode" "TI"))
(const_string "1")
(const_string "*")))
(set_attr "prefix" "orig,vex")
(set (attr "mode")
(cond [(ne (symbol_ref "GET_MODE_SIZE (<MODE>mode) > 128") (const_int 0))
(const_string "V8SF")
(ne (symbol_ref "TARGET_SSE2") (const_int 0))
(const_string "TI")
]
(const_string "V4SF")))])
(define_insn "*andnottf3"
[(set (match_operand:TF 0 "register_operand" "=x,x")
(and:TF
(not:TF (match_operand:TF 1 "register_operand" "0,x"))
(match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2"
"@
pandn\t{%2, %0|%0, %2}
vpandn\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
(define_expand "<code>tf3" (define_expand "<code>tf3"
...@@ -5906,14 +5914,19 @@ ...@@ -5906,14 +5914,19 @@
"ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);") "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
(define_insn "*<code>tf3" (define_insn "*<code>tf3"
[(set (match_operand:TF 0 "register_operand" "=x") [(set (match_operand:TF 0 "register_operand" "=x,x")
(any_logic:TF (any_logic:TF
(match_operand:TF 1 "nonimmediate_operand" "%0") (match_operand:TF 1 "nonimmediate_operand" "%0,x")
(match_operand:TF 2 "nonimmediate_operand" "xm")))] (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))]
"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)" "TARGET_SSE2
"p<logic>\t{%2, %0|%0, %2}" && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
[(set_attr "type" "sselog") "@
(set_attr "prefix_data16" "1") p<logic>\t{%2, %0|%0, %2}
vp<logic>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
(set_attr "prefix_data16" "1,*")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")]) (set_attr "mode" "TI")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
......
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