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riscv-gcc-1
Commit d537c24d by Richard Kenner
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(EXTRA_CONSTRAINT, case 'R'): Fix error in last change. 

From-SVN: r8607
parent a1fa1e22
Showing with 1 additions and 2 deletions
gcc/config/rs6000/rs6000.h
...@@ -733,8 +733,7 @@ enum reg_class { NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS, ...@@ -733,8 +733,7 @@ enum reg_class { NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS,
#define EXTRA_CONSTRAINT(OP, C) \ #define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
: (C) == 'R' ? (GET_CODE (OP) == SYMBOL_REF \ : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
&& LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP)) \
: 0) : 0)
/* Given an rtx X being reloaded into a reg required to be /* Given an rtx X being reloaded into a reg required to be
......
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