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riscv-gcc-1
Commit d435a4be by Kyrylo Tkachov Committed by Richard Earnshaw
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arm.c: Use CONST_INT_P... 

2012-09-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c: Use CONST_INT_P, CONST_DOUBLE_P, REG_P, MEM_P,
	LABEL_P, JUMP_P, CALL_P, NOTE_P, BARRIER_P consistently.
	* config/arm/arm.h: Use REG_P, MEM_P consistently.
	* config/arm/arm.md: Use CONST_INT_P, REG_P, MEM_P, CONST_DOUBLE_P
	consistently.
	* config/arm/neon.md: Use REG_P consistently.
	* config/arm/predicates.md: Use CONST_INT_P, REG_P, MEM_P
	consistently.
	* config/arm/thumb2.md: Use CONST_INT_P, REG_P consistently.
	* config/arm/vec-common.md: Use REG_P consistently.

From-SVN: r191034
parent c2b3ec18
Showing with 381 additions and 371 deletions
gcc/ChangeLog
2012-09-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c: Use CONST_INT_P, CONST_DOUBLE_P, REG_P, MEM_P,
LABEL_P, JUMP_P, CALL_P, NOTE_P, BARRIER_P consistently.
* config/arm/arm.h: Use REG_P, MEM_P consistently.
* config/arm/arm.md: Use CONST_INT_P, REG_P, MEM_P, CONST_DOUBLE_P
consistently.
* config/arm/neon.md: Use REG_P consistently.
* config/arm/predicates.md: Use CONST_INT_P, REG_P, MEM_P
consistently.
* config/arm/thumb2.md: Use CONST_INT_P, REG_P consistently.
* config/arm/vec-common.md: Use REG_P consistently.
2012-09-06 Richard Guenther <rguenther@suse.de> 2012-09-06 Richard Guenther <rguenther@suse.de>
PR tree-optimization/54498 PR tree-optimization/54498
......
gcc/config/arm/arm.c
...@@ -2337,7 +2337,7 @@ use_return_insn (int iscond, rtx sibling) ...@@ -2337,7 +2337,7 @@ use_return_insn (int iscond, rtx sibling)
/* ... or for a tail-call argument ... */ /* ... or for a tail-call argument ... */
if (sibling) if (sibling)
{ {
gcc_assert (GET_CODE (sibling) == CALL_INSN); gcc_assert (CALL_P (sibling));
if (find_regno_fusage (sibling, USE, 3)) if (find_regno_fusage (sibling, USE, 3))
return 0; return 0;
...@@ -2558,7 +2558,7 @@ arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, ...@@ -2558,7 +2558,7 @@ arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
cond = NULL_RTX; cond = NULL_RTX;
if (subtargets || code == SET if (subtargets || code == SET
|| (GET_CODE (target) == REG && GET_CODE (source) == REG || (REG_P (target) && REG_P (source)
&& REGNO (target) != REGNO (source))) && REGNO (target) != REGNO (source)))
{ {
/* After arm_reorg has been called, we can't fix up expensive /* After arm_reorg has been called, we can't fix up expensive
...@@ -3530,7 +3530,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) ...@@ -3530,7 +3530,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1)
{ {
/* Missing comparison. First try to use an available /* Missing comparison. First try to use an available
comparison. */ comparison. */
if (GET_CODE (*op1) == CONST_INT) if (CONST_INT_P (*op1))
{ {
i = INTVAL (*op1); i = INTVAL (*op1);
switch (code) switch (code)
...@@ -3583,7 +3583,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) ...@@ -3583,7 +3583,7 @@ arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1)
/* Comparisons smaller than DImode. Only adjust comparisons against /* Comparisons smaller than DImode. Only adjust comparisons against
an out-of-range constant. */ an out-of-range constant. */
if (GET_CODE (*op1) != CONST_INT if (!CONST_INT_P (*op1)
|| const_ok_for_arm (INTVAL (*op1)) || const_ok_for_arm (INTVAL (*op1))
|| const_ok_for_arm (- INTVAL (*op1))) || const_ok_for_arm (- INTVAL (*op1)))
return code; return code;
...@@ -4160,7 +4160,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) ...@@ -4160,7 +4160,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep)
tree index = TYPE_DOMAIN (type); tree index = TYPE_DOMAIN (type);
/* Can't handle incomplete types. */ /* Can't handle incomplete types. */
if (!COMPLETE_TYPE_P(type)) if (!COMPLETE_TYPE_P (type))
return -1; return -1;
count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep); count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep);
...@@ -4192,7 +4192,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) ...@@ -4192,7 +4192,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep)
tree field; tree field;
/* Can't handle incomplete types. */ /* Can't handle incomplete types. */
if (!COMPLETE_TYPE_P(type)) if (!COMPLETE_TYPE_P (type))
return -1; return -1;
for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
...@@ -4224,7 +4224,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) ...@@ -4224,7 +4224,7 @@ aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep)
tree field; tree field;
/* Can't handle incomplete types. */ /* Can't handle incomplete types. */
if (!COMPLETE_TYPE_P(type)) if (!COMPLETE_TYPE_P (type))
return -1; return -1;
for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
...@@ -5442,7 +5442,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) ...@@ -5442,7 +5442,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
&& GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC
&& XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS) && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS)
{ {
gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT); gcc_assert (CONST_INT_P (XEXP (XEXP (orig, 0), 1)));
return orig; return orig;
} }
...@@ -5458,7 +5458,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) ...@@ -5458,7 +5458,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
base == reg ? 0 : reg); base == reg ? 0 : reg);
if (GET_CODE (offset) == CONST_INT) if (CONST_INT_P (offset))
{ {
/* The base register doesn't really matter, we only want to /* The base register doesn't really matter, we only want to
test the index for the appropriate mode. */ test the index for the appropriate mode. */
...@@ -5468,7 +5468,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) ...@@ -5468,7 +5468,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
offset = force_reg (Pmode, offset); offset = force_reg (Pmode, offset);
} }
if (GET_CODE (offset) == CONST_INT) if (CONST_INT_P (offset))
return plus_constant (Pmode, base, INTVAL (offset)); return plus_constant (Pmode, base, INTVAL (offset));
} }
...@@ -5649,7 +5649,7 @@ arm_address_register_rtx_p (rtx x, int strict_p) ...@@ -5649,7 +5649,7 @@ arm_address_register_rtx_p (rtx x, int strict_p)
{ {
int regno; int regno;
if (GET_CODE (x) != REG) if (!REG_P (x))
return 0; return 0;
regno = REGNO (x); regno = REGNO (x);
...@@ -5716,7 +5716,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, ...@@ -5716,7 +5716,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer,
to fixup invalid register choices. */ to fixup invalid register choices. */
if (use_ldrd if (use_ldrd
&& GET_CODE (x) == POST_MODIFY && GET_CODE (x) == POST_MODIFY
&& GET_CODE (addend) == REG) && REG_P (addend))
return 0; return 0;
return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
...@@ -5730,7 +5730,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, ...@@ -5730,7 +5730,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer,
|| (code == CONST || (code == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1; return 1;
else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
...@@ -5742,7 +5742,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, ...@@ -5742,7 +5742,7 @@ arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer,
rtx xop1 = XEXP (x, 1); rtx xop1 = XEXP (x, 1);
return ((arm_address_register_rtx_p (xop0, strict_p) return ((arm_address_register_rtx_p (xop0, strict_p)
&& ((GET_CODE(xop1) == CONST_INT && ((CONST_INT_P (xop1)
&& arm_legitimate_index_p (mode, xop1, outer, strict_p)) && arm_legitimate_index_p (mode, xop1, outer, strict_p))
|| (!strict_p && will_be_in_index_register (xop1)))) || (!strict_p && will_be_in_index_register (xop1))))
|| (arm_address_register_rtx_p (xop1, strict_p) || (arm_address_register_rtx_p (xop1, strict_p)
...@@ -5800,7 +5800,7 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) ...@@ -5800,7 +5800,7 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
rtx addend = XEXP (XEXP (x, 1), 1); rtx addend = XEXP (XEXP (x, 1), 1);
HOST_WIDE_INT offset; HOST_WIDE_INT offset;
if (GET_CODE (addend) != CONST_INT) if (!CONST_INT_P (addend))
return 0; return 0;
offset = INTVAL(addend); offset = INTVAL(addend);
...@@ -5818,7 +5818,7 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) ...@@ -5818,7 +5818,7 @@ thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
|| (code == CONST || (code == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1; return 1;
else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
...@@ -5930,7 +5930,7 @@ arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, ...@@ -5930,7 +5930,7 @@ arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
rtx op = XEXP (index, 1); rtx op = XEXP (index, 1);
return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
&& GET_CODE (op) == CONST_INT && CONST_INT_P (op)
&& INTVAL (op) > 0 && INTVAL (op) > 0
&& INTVAL (op) <= 31); && INTVAL (op) <= 31);
} }
...@@ -5962,7 +5962,7 @@ thumb2_index_mul_operand (rtx op) ...@@ -5962,7 +5962,7 @@ thumb2_index_mul_operand (rtx op)
{ {
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE(op) != CONST_INT) if (!CONST_INT_P (op))
return false; return false;
val = INTVAL(op); val = INTVAL(op);
...@@ -6052,7 +6052,7 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) ...@@ -6052,7 +6052,7 @@ thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
rtx op = XEXP (index, 1); rtx op = XEXP (index, 1);
return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
&& GET_CODE (op) == CONST_INT && CONST_INT_P (op)
&& INTVAL (op) > 0 && INTVAL (op) > 0
&& INTVAL (op) <= 3); && INTVAL (op) <= 3);
} }
...@@ -6068,7 +6068,7 @@ thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) ...@@ -6068,7 +6068,7 @@ thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
{ {
int regno; int regno;
if (GET_CODE (x) != REG) if (!REG_P (x))
return 0; return 0;
regno = REGNO (x); regno = REGNO (x);
...@@ -6142,7 +6142,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) ...@@ -6142,7 +6142,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
|| (GET_CODE (x) == CONST || (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1; return 1;
/* Post-inc indexing only supported for SImode and larger. */ /* Post-inc indexing only supported for SImode and larger. */
...@@ -6167,7 +6167,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) ...@@ -6167,7 +6167,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
/* REG+const has 5-7 bit offset for non-SP registers. */ /* REG+const has 5-7 bit offset for non-SP registers. */
else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
|| XEXP (x, 0) == arg_pointer_rtx) || XEXP (x, 0) == arg_pointer_rtx)
&& GET_CODE (XEXP (x, 1)) == CONST_INT && CONST_INT_P (XEXP (x, 1))
&& thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
return 1; return 1;
...@@ -6175,23 +6175,23 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) ...@@ -6175,23 +6175,23 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
larger is supported. */ larger is supported. */
/* ??? Should probably check for DI/DFmode overflow here /* ??? Should probably check for DI/DFmode overflow here
just like GO_IF_LEGITIMATE_OFFSET does. */ just like GO_IF_LEGITIMATE_OFFSET does. */
else if (GET_CODE (XEXP (x, 0)) == REG else if (REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode) >= 4 && GET_MODE_SIZE (mode) >= 4
&& GET_CODE (XEXP (x, 1)) == CONST_INT && CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) >= 0
&& INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
&& (INTVAL (XEXP (x, 1)) & 3) == 0) && (INTVAL (XEXP (x, 1)) & 3) == 0)
return 1; return 1;
else if (GET_CODE (XEXP (x, 0)) == REG else if (REG_P (XEXP (x, 0))
&& (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
|| REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
|| (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
&& REGNO (XEXP (x, 0)) && REGNO (XEXP (x, 0))
<= LAST_VIRTUAL_POINTER_REGISTER)) <= LAST_VIRTUAL_POINTER_REGISTER))
&& GET_MODE_SIZE (mode) >= 4 && GET_MODE_SIZE (mode) >= 4
&& GET_CODE (XEXP (x, 1)) == CONST_INT && CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) & 3) == 0) && (INTVAL (XEXP (x, 1)) & 3) == 0)
return 1; return 1;
} }
...@@ -6495,7 +6495,7 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) ...@@ -6495,7 +6495,7 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
xop1 = force_reg (SImode, xop1); xop1 = force_reg (SImode, xop1);
if (ARM_BASE_REGISTER_RTX_P (xop0) if (ARM_BASE_REGISTER_RTX_P (xop0)
&& GET_CODE (xop1) == CONST_INT) && CONST_INT_P (xop1))
{ {
HOST_WIDE_INT n, low_n; HOST_WIDE_INT n, low_n;
rtx base_reg, val; rtx base_reg, val;
...@@ -6551,7 +6551,7 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) ...@@ -6551,7 +6551,7 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
with absolute addresses which often allows for the base register to with absolute addresses which often allows for the base register to
be factorized for multiple adjacent memory references, and it might be factorized for multiple adjacent memory references, and it might
even allows for the mini pool to be avoided entirely. */ even allows for the mini pool to be avoided entirely. */
else if (GET_CODE (x) == CONST_INT && optimize > 0) else if (CONST_INT_P (x) && optimize > 0)
{ {
unsigned int bits; unsigned int bits;
HOST_WIDE_INT mask, base, index; HOST_WIDE_INT mask, base, index;
...@@ -6598,7 +6598,7 @@ thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) ...@@ -6598,7 +6598,7 @@ thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
return legitimize_tls_address (x, NULL_RTX); return legitimize_tls_address (x, NULL_RTX);
if (GET_CODE (x) == PLUS if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == CONST_INT && CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
|| INTVAL (XEXP (x, 1)) < 0)) || INTVAL (XEXP (x, 1)) < 0))
{ {
...@@ -6668,9 +6668,9 @@ arm_legitimize_reload_address (rtx *p, ...@@ -6668,9 +6668,9 @@ arm_legitimize_reload_address (rtx *p,
/* We must recognize output that we have already generated ourselves. */ /* We must recognize output that we have already generated ourselves. */
if (GET_CODE (*p) == PLUS if (GET_CODE (*p) == PLUS
&& GET_CODE (XEXP (*p, 0)) == PLUS && GET_CODE (XEXP (*p, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (*p, 0), 0)) == REG && REG_P (XEXP (XEXP (*p, 0), 0))
&& GET_CODE (XEXP (XEXP (*p, 0), 1)) == CONST_INT && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
&& GET_CODE (XEXP (*p, 1)) == CONST_INT) && CONST_INT_P (XEXP (*p, 1)))
{ {
push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
MODE_BASE_REG_CLASS (mode), GET_MODE (*p), MODE_BASE_REG_CLASS (mode), GET_MODE (*p),
...@@ -6679,13 +6679,13 @@ arm_legitimize_reload_address (rtx *p, ...@@ -6679,13 +6679,13 @@ arm_legitimize_reload_address (rtx *p,
} }
if (GET_CODE (*p) == PLUS if (GET_CODE (*p) == PLUS
&& GET_CODE (XEXP (*p, 0)) == REG && REG_P (XEXP (*p, 0))
&& ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0))) && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0)))
/* If the base register is equivalent to a constant, let the generic /* If the base register is equivalent to a constant, let the generic
code handle it. Otherwise we will run into problems if a future code handle it. Otherwise we will run into problems if a future
reload pass decides to rematerialize the constant. */ reload pass decides to rematerialize the constant. */
&& !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p, 0))) && !reg_equiv_constant (ORIGINAL_REGNO (XEXP (*p, 0)))
&& GET_CODE (XEXP (*p, 1)) == CONST_INT) && CONST_INT_P (XEXP (*p, 1)))
{ {
HOST_WIDE_INT val = INTVAL (XEXP (*p, 1)); HOST_WIDE_INT val = INTVAL (XEXP (*p, 1));
HOST_WIDE_INT low, high; HOST_WIDE_INT low, high;
...@@ -6854,7 +6854,7 @@ thumb_legitimize_reload_address (rtx *x_p, ...@@ -6854,7 +6854,7 @@ thumb_legitimize_reload_address (rtx *x_p,
&& GET_MODE_SIZE (mode) < 4 && GET_MODE_SIZE (mode) < 4
&& REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 0))
&& XEXP (x, 0) == stack_pointer_rtx && XEXP (x, 0) == stack_pointer_rtx
&& GET_CODE (XEXP (x, 1)) == CONST_INT && CONST_INT_P (XEXP (x, 1))
&& !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
{ {
rtx orig_x = x; rtx orig_x = x;
...@@ -6952,8 +6952,8 @@ arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x) ...@@ -6952,8 +6952,8 @@ arm_legitimate_constant_p_1 (enum machine_mode mode, rtx x)
static bool static bool
thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) thumb_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{ {
return (GET_CODE (x) == CONST_INT return (CONST_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE || CONST_DOUBLE_P (x)
|| CONSTANT_ADDRESS_P (x) || CONSTANT_ADDRESS_P (x)
|| flag_pic); || flag_pic);
} }
...@@ -6985,11 +6985,11 @@ arm_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) ...@@ -6985,11 +6985,11 @@ arm_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
} }
#define REG_OR_SUBREG_REG(X) \ #define REG_OR_SUBREG_REG(X) \
(GET_CODE (X) == REG \ (REG_P (X) \
|| (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))))
#define REG_OR_SUBREG_RTX(X) \ #define REG_OR_SUBREG_RTX(X) \
(GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) (REG_P (X) ? (X) : SUBREG_REG (X))
static inline int static inline int
thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
...@@ -7011,7 +7011,7 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) ...@@ -7011,7 +7011,7 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
return COSTS_N_INSNS (1); return COSTS_N_INSNS (1);
case MULT: case MULT:
if (GET_CODE (XEXP (x, 1)) == CONST_INT) if (CONST_INT_P (XEXP (x, 1)))
{ {
int cycles = 0; int cycles = 0;
unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
...@@ -7027,8 +7027,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) ...@@ -7027,8 +7027,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
case SET: case SET:
return (COSTS_N_INSNS (1) return (COSTS_N_INSNS (1)
+ 4 * ((GET_CODE (SET_SRC (x)) == MEM) + 4 * ((MEM_P (SET_SRC (x)))
+ GET_CODE (SET_DEST (x)) == MEM)); + MEM_P (SET_DEST (x))));
case CONST_INT: case CONST_INT:
if (outer == SET) if (outer == SET)
...@@ -7144,9 +7144,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7144,9 +7144,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
return false; return false;
case ROTATE: case ROTATE:
if (GET_CODE (XEXP (x, 1)) == REG) if (REG_P (XEXP (x, 1)))
*total = COSTS_N_INSNS (1); /* Need to subtract from 32 */ *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
else if (GET_CODE (XEXP (x, 1)) != CONST_INT) else if (!CONST_INT_P (XEXP (x, 1)))
*total = rtx_cost (XEXP (x, 1), code, 1, speed); *total = rtx_cost (XEXP (x, 1), code, 1, speed);
/* Fall through */ /* Fall through */
...@@ -7170,7 +7170,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7170,7 +7170,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
/* Increase the cost of complex shifts because they aren't any faster, /* Increase the cost of complex shifts because they aren't any faster,
and reduce dual issue opportunities. */ and reduce dual issue opportunities. */
if (arm_tune_cortex_a9 if (arm_tune_cortex_a9
&& outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT) && outer != SET && !CONST_INT_P (XEXP (x, 1)))
++*total; ++*total;
return true; return true;
...@@ -7179,14 +7179,14 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7179,14 +7179,14 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
if (mode == DImode) if (mode == DImode)
{ {
*total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
if (GET_CODE (XEXP (x, 0)) == CONST_INT if (CONST_INT_P (XEXP (x, 0))
&& const_ok_for_arm (INTVAL (XEXP (x, 0)))) && const_ok_for_arm (INTVAL (XEXP (x, 0))))
{ {
*total += rtx_cost (XEXP (x, 1), code, 1, speed); *total += rtx_cost (XEXP (x, 1), code, 1, speed);
return true; return true;
} }
if (GET_CODE (XEXP (x, 1)) == CONST_INT if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_arm (INTVAL (XEXP (x, 1)))) && const_ok_for_arm (INTVAL (XEXP (x, 1))))
{ {
*total += rtx_cost (XEXP (x, 0), code, 0, speed); *total += rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7203,14 +7203,14 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7203,14 +7203,14 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
|| (mode == DFmode && !TARGET_VFP_SINGLE))) || (mode == DFmode && !TARGET_VFP_SINGLE)))
{ {
*total = COSTS_N_INSNS (1); *total = COSTS_N_INSNS (1);
if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE if (CONST_DOUBLE_P (XEXP (x, 0))
&& arm_const_double_rtx (XEXP (x, 0))) && arm_const_double_rtx (XEXP (x, 0)))
{ {
*total += rtx_cost (XEXP (x, 1), code, 1, speed); *total += rtx_cost (XEXP (x, 1), code, 1, speed);
return true; return true;
} }
if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE if (CONST_DOUBLE_P (XEXP (x, 1))
&& arm_const_double_rtx (XEXP (x, 1))) && arm_const_double_rtx (XEXP (x, 1)))
{ {
*total += rtx_cost (XEXP (x, 0), code, 0, speed); *total += rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7224,7 +7224,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7224,7 +7224,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
} }
*total = COSTS_N_INSNS (1); *total = COSTS_N_INSNS (1);
if (GET_CODE (XEXP (x, 0)) == CONST_INT if (CONST_INT_P (XEXP (x, 0))
&& const_ok_for_arm (INTVAL (XEXP (x, 0)))) && const_ok_for_arm (INTVAL (XEXP (x, 0))))
{ {
*total += rtx_cost (XEXP (x, 1), code, 1, speed); *total += rtx_cost (XEXP (x, 1), code, 1, speed);
...@@ -7262,7 +7262,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7262,7 +7262,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
|| GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE) || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE)
{ {
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed); *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG if (REG_P (XEXP (XEXP (x, 1), 0))
&& REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM) && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM)
*total += COSTS_N_INSNS (1); *total += COSTS_N_INSNS (1);
...@@ -7300,7 +7300,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7300,7 +7300,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
|| (mode == DFmode && !TARGET_VFP_SINGLE))) || (mode == DFmode && !TARGET_VFP_SINGLE)))
{ {
*total = COSTS_N_INSNS (1); *total = COSTS_N_INSNS (1);
if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE if (CONST_DOUBLE_P (XEXP (x, 1))
&& arm_const_double_rtx (XEXP (x, 1))) && arm_const_double_rtx (XEXP (x, 1)))
{ {
*total += rtx_cost (XEXP (x, 0), code, 0, speed); *total += rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7318,7 +7318,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7318,7 +7318,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
|| GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE) || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE)
{ {
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, 1, speed); *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, 1, speed);
if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG if (REG_P (XEXP (XEXP (x, 0), 0))
&& REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM) && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM)
*total += COSTS_N_INSNS (1); *total += COSTS_N_INSNS (1);
return true; return true;
...@@ -7335,13 +7335,13 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7335,13 +7335,13 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
operand. */ operand. */
if (REG_OR_SUBREG_REG (XEXP (x, 0)) if (REG_OR_SUBREG_REG (XEXP (x, 0))
&& ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
&& GET_CODE (XEXP (x, 1)) != CONST_INT) && !CONST_INT_P (XEXP (x, 1)))
*total = COSTS_N_INSNS (1); *total = COSTS_N_INSNS (1);
if (mode == DImode) if (mode == DImode)
{ {
*total += COSTS_N_INSNS (2); *total += COSTS_N_INSNS (2);
if (GET_CODE (XEXP (x, 1)) == CONST_INT if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_op (INTVAL (XEXP (x, 1)), code)) && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
{ {
*total += rtx_cost (XEXP (x, 0), code, 0, speed); *total += rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7352,7 +7352,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7352,7 +7352,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
} }
*total += COSTS_N_INSNS (1); *total += COSTS_N_INSNS (1);
if (GET_CODE (XEXP (x, 1)) == CONST_INT if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_op (INTVAL (XEXP (x, 1)), code)) && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
{ {
*total += rtx_cost (XEXP (x, 0), code, 0, speed); *total += rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7432,7 +7432,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7432,7 +7432,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
{ {
*total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed); *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, 0, speed);
/* Register shifts cost an extra cycle. */ /* Register shifts cost an extra cycle. */
if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) if (!CONST_INT_P (XEXP (XEXP (x, 0), 1)))
*total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1), *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1),
subcode, 1, speed); subcode, 1, speed);
return true; return true;
...@@ -7452,7 +7452,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7452,7 +7452,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE
|| GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE) || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE)
&& GET_CODE (XEXP (operand, 0)) == REG && REG_P (XEXP (operand, 0))
&& REGNO (XEXP (operand, 0)) == CC_REGNUM)) && REGNO (XEXP (operand, 0)) == CC_REGNUM))
*total += COSTS_N_INSNS (1); *total += COSTS_N_INSNS (1);
*total += (rtx_cost (XEXP (x, 1), code, 1, speed) *total += (rtx_cost (XEXP (x, 1), code, 1, speed)
...@@ -7468,7 +7468,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7468,7 +7468,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
goto scc_insn; goto scc_insn;
case GE: case GE:
if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
&& mode == SImode && XEXP (x, 1) == const0_rtx) && mode == SImode && XEXP (x, 1) == const0_rtx)
{ {
*total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed); *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7477,7 +7477,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7477,7 +7477,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
goto scc_insn; goto scc_insn;
case LT: case LT:
if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) if ((!REG_P (XEXP (x, 0)) || REGNO (XEXP (x, 0)) != CC_REGNUM)
&& mode == SImode && XEXP (x, 1) == const0_rtx) && mode == SImode && XEXP (x, 1) == const0_rtx)
{ {
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed); *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7504,21 +7504,21 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7504,21 +7504,21 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
performed, then they cost 2 instructions. Otherwise they need performed, then they cost 2 instructions. Otherwise they need
an additional comparison before them. */ an additional comparison before them. */
*total = COSTS_N_INSNS (2); *total = COSTS_N_INSNS (2);
if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
{ {
return true; return true;
} }
/* Fall through */ /* Fall through */
case COMPARE: case COMPARE:
if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == CC_REGNUM)
{ {
*total = 0; *total = 0;
return true; return true;
} }
*total += COSTS_N_INSNS (1); *total += COSTS_N_INSNS (1);
if (GET_CODE (XEXP (x, 1)) == CONST_INT if (CONST_INT_P (XEXP (x, 1))
&& const_ok_for_op (INTVAL (XEXP (x, 1)), code)) && const_ok_for_op (INTVAL (XEXP (x, 1)), code))
{ {
*total += rtx_cost (XEXP (x, 0), code, 0, speed); *total += rtx_cost (XEXP (x, 0), code, 0, speed);
...@@ -7550,7 +7550,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) ...@@ -7550,7 +7550,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed)
case SMIN: case SMIN:
case SMAX: case SMAX:
*total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed); *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, speed);
if (GET_CODE (XEXP (x, 1)) != CONST_INT if (!CONST_INT_P (XEXP (x, 1))
|| !const_ok_for_arm (INTVAL (XEXP (x, 1)))) || !const_ok_for_arm (INTVAL (XEXP (x, 1))))
*total += rtx_cost (XEXP (x, 1), code, 1, speed); *total += rtx_cost (XEXP (x, 1), code, 1, speed);
return true; return true;
...@@ -7716,7 +7716,7 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) ...@@ -7716,7 +7716,7 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
return COSTS_N_INSNS (1); return COSTS_N_INSNS (1);
case MULT: case MULT:
if (GET_CODE (XEXP (x, 1)) == CONST_INT) if (CONST_INT_P (XEXP (x, 1)))
{ {
/* Thumb1 mul instruction can't operate on const. We must Load it /* Thumb1 mul instruction can't operate on const. We must Load it
into a register first. */ into a register first. */
...@@ -7727,8 +7727,8 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) ...@@ -7727,8 +7727,8 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
case SET: case SET:
return (COSTS_N_INSNS (1) return (COSTS_N_INSNS (1)
+ 4 * ((GET_CODE (SET_SRC (x)) == MEM) + 4 * ((MEM_P (SET_SRC (x)))
+ GET_CODE (SET_DEST (x)) == MEM)); + MEM_P (SET_DEST (x))));
case CONST_INT: case CONST_INT:
if (outer == SET) if (outer == SET)
...@@ -7804,14 +7804,14 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) ...@@ -7804,14 +7804,14 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
{ {
case QImode: case QImode:
return (1 + (mode == DImode ? 4 : 0) return (1 + (mode == DImode ? 4 : 0)
+ (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + (MEM_P (XEXP (x, 0)) ? 10 : 0));
case HImode: case HImode:
return (4 + (mode == DImode ? 4 : 0) return (4 + (mode == DImode ? 4 : 0)
+ (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + (MEM_P (XEXP (x, 0)) ? 10 : 0));
case SImode: case SImode:
return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); return (1 + (MEM_P (XEXP (x, 0)) ? 10 : 0));
default: default:
return 99; return 99;
...@@ -7861,7 +7861,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -7861,7 +7861,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
return false; return false;
case ROTATE: case ROTATE:
if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) if (mode == SImode && REG_P (XEXP (x, 1)))
{ {
*total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, false); *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, 0, false);
return true; return true;
...@@ -7871,7 +7871,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -7871,7 +7871,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
case ASHIFT: case ASHIFT:
case LSHIFTRT: case LSHIFTRT:
case ASHIFTRT: case ASHIFTRT:
if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) if (mode == DImode && CONST_INT_P (XEXP (x, 1)))
{ {
*total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, 0, false); *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, 0, false);
return true; return true;
...@@ -7880,7 +7880,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -7880,7 +7880,7 @@ arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
{ {
*total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, false); *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, 0, false);
/* Slightly disparage register shifts, but not by much. */ /* Slightly disparage register shifts, but not by much. */
if (GET_CODE (XEXP (x, 1)) != CONST_INT) if (!CONST_INT_P (XEXP (x, 1)))
*total += 1 + rtx_cost (XEXP (x, 1), code, 1, false); *total += 1 + rtx_cost (XEXP (x, 1), code, 1, false);
return true; return true;
} }
...@@ -8097,7 +8097,7 @@ arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -8097,7 +8097,7 @@ arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
return false; return false;
} }
if (GET_CODE (XEXP (x, 1)) == CONST_INT) if (CONST_INT_P (XEXP (x, 1)))
{ {
unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
& (unsigned HOST_WIDE_INT) 0xffffffff); & (unsigned HOST_WIDE_INT) 0xffffffff);
...@@ -8163,7 +8163,7 @@ arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -8163,7 +8163,7 @@ arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
return false; return false;
} }
if (GET_CODE (XEXP (x, 1)) == CONST_INT) if (CONST_INT_P (XEXP (x, 1)))
{ {
unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
& (unsigned HOST_WIDE_INT) 0xffffffff); & (unsigned HOST_WIDE_INT) 0xffffffff);
...@@ -8255,7 +8255,7 @@ arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, ...@@ -8255,7 +8255,7 @@ arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
return false; return false;
} }
if (GET_CODE (XEXP (x, 1)) == CONST_INT) if (CONST_INT_P (XEXP (x, 1)))
{ {
/* If operand 1 is a constant we can more accurately /* If operand 1 is a constant we can more accurately
calculate the cost of the multiply. The multiplier can calculate the cost of the multiply. The multiplier can
...@@ -8383,7 +8383,7 @@ arm_arm_address_cost (rtx x) ...@@ -8383,7 +8383,7 @@ arm_arm_address_cost (rtx x)
if (c == PLUS) if (c == PLUS)
{ {
if (GET_CODE (XEXP (x, 1)) == CONST_INT) if (CONST_INT_P (XEXP (x, 1)))
return 2; return 2;
if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
...@@ -8403,8 +8403,8 @@ arm_thumb_address_cost (rtx x) ...@@ -8403,8 +8403,8 @@ arm_thumb_address_cost (rtx x)
if (c == REG) if (c == REG)
return 1; return 1;
if (c == PLUS if (c == PLUS
&& GET_CODE (XEXP (x, 0)) == REG && REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == CONST_INT) && CONST_INT_P (XEXP (x, 1)))
return 1; return 1;
return 2; return 2;
...@@ -8655,13 +8655,13 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) ...@@ -8655,13 +8655,13 @@ arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
/* Call insns don't incur a stall, even if they follow a load. */ /* Call insns don't incur a stall, even if they follow a load. */
if (REG_NOTE_KIND (link) == 0 if (REG_NOTE_KIND (link) == 0
&& GET_CODE (insn) == CALL_INSN) && CALL_P (insn))
return 1; return 1;
if ((i_pat = single_set (insn)) != NULL if ((i_pat = single_set (insn)) != NULL
&& GET_CODE (SET_SRC (i_pat)) == MEM && MEM_P (SET_SRC (i_pat))
&& (d_pat = single_set (dep)) != NULL && (d_pat = single_set (dep)) != NULL
&& GET_CODE (SET_DEST (d_pat)) == MEM) && MEM_P (SET_DEST (d_pat)))
{ {
rtx src_mem = XEXP (SET_SRC (i_pat), 0); rtx src_mem = XEXP (SET_SRC (i_pat), 0);
/* This is a load after a store, there is no conflict if the load reads /* This is a load after a store, there is no conflict if the load reads
...@@ -8756,7 +8756,7 @@ vfp3_const_double_index (rtx x) ...@@ -8756,7 +8756,7 @@ vfp3_const_double_index (rtx x)
HOST_WIDE_INT m1, m2; HOST_WIDE_INT m1, m2;
int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE) if (!TARGET_VFP3 || !CONST_DOUBLE_P (x))
return -1; return -1;
REAL_VALUE_FROM_CONST_DOUBLE (r, x); REAL_VALUE_FROM_CONST_DOUBLE (r, x);
...@@ -8959,12 +8959,12 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, ...@@ -8959,12 +8959,12 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
unsigned HOST_WIDE_INT elpart; unsigned HOST_WIDE_INT elpart;
unsigned int part, parts; unsigned int part, parts;
if (GET_CODE (el) == CONST_INT) if (CONST_INT_P (el))
{ {
elpart = INTVAL (el); elpart = INTVAL (el);
parts = 1; parts = 1;
} }
else if (GET_CODE (el) == CONST_DOUBLE) else if (CONST_DOUBLE_P (el))
{ {
elpart = CONST_DOUBLE_LOW (el); elpart = CONST_DOUBLE_LOW (el);
parts = 2; parts = 2;
...@@ -8980,7 +8980,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, ...@@ -8980,7 +8980,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
bytes[idx++] = (elpart & 0xff) ^ invmask; bytes[idx++] = (elpart & 0xff) ^ invmask;
elpart >>= BITS_PER_UNIT; elpart >>= BITS_PER_UNIT;
} }
if (GET_CODE (el) == CONST_DOUBLE) if (CONST_DOUBLE_P (el))
elpart = CONST_DOUBLE_HIGH (el); elpart = CONST_DOUBLE_HIGH (el);
} }
} }
...@@ -9154,9 +9154,9 @@ neon_immediate_valid_for_shift (rtx op, enum machine_mode mode, ...@@ -9154,9 +9154,9 @@ neon_immediate_valid_for_shift (rtx op, enum machine_mode mode,
rtx el = CONST_VECTOR_ELT (op, i); rtx el = CONST_VECTOR_ELT (op, i);
unsigned HOST_WIDE_INT elpart; unsigned HOST_WIDE_INT elpart;
if (GET_CODE (el) == CONST_INT) if (CONST_INT_P (el))
elpart = INTVAL (el); elpart = INTVAL (el);
else if (GET_CODE (el) == CONST_DOUBLE) else if (CONST_DOUBLE_P (el))
return 0; return 0;
else else
gcc_unreachable (); gcc_unreachable ();
...@@ -9326,7 +9326,7 @@ neon_make_constant (rtx vals) ...@@ -9326,7 +9326,7 @@ neon_make_constant (rtx vals)
for (i = 0; i < n_elts; ++i) for (i = 0; i < n_elts; ++i)
{ {
rtx x = XVECEXP (vals, 0, i); rtx x = XVECEXP (vals, 0, i);
if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
n_const++; n_const++;
} }
if (n_const == n_elts) if (n_const == n_elts)
...@@ -9467,7 +9467,7 @@ bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high, ...@@ -9467,7 +9467,7 @@ bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
{ {
HOST_WIDE_INT lane; HOST_WIDE_INT lane;
gcc_assert (GET_CODE (operand) == CONST_INT); gcc_assert (CONST_INT_P (operand));
lane = INTVAL (operand); lane = INTVAL (operand);
...@@ -9524,7 +9524,7 @@ arm_coproc_mem_operand (rtx op, bool wb) ...@@ -9524,7 +9524,7 @@ arm_coproc_mem_operand (rtx op, bool wb)
return FALSE; return FALSE;
/* Constants are converted into offsets from labels. */ /* Constants are converted into offsets from labels. */
if (GET_CODE (op) != MEM) if (!MEM_P (op))
return FALSE; return FALSE;
ind = XEXP (op, 0); ind = XEXP (op, 0);
...@@ -9534,11 +9534,11 @@ arm_coproc_mem_operand (rtx op, bool wb) ...@@ -9534,11 +9534,11 @@ arm_coproc_mem_operand (rtx op, bool wb)
|| (GET_CODE (ind) == CONST || (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS && GET_CODE (XEXP (ind, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE; return TRUE;
/* Match: (mem (reg)). */ /* Match: (mem (reg)). */
if (GET_CODE (ind) == REG) if (REG_P (ind))
return arm_address_register_rtx_p (ind, 0); return arm_address_register_rtx_p (ind, 0);
/* Autoincremment addressing modes. POST_INC and PRE_DEC are /* Autoincremment addressing modes. POST_INC and PRE_DEC are
...@@ -9563,9 +9563,9 @@ arm_coproc_mem_operand (rtx op, bool wb) ...@@ -9563,9 +9563,9 @@ arm_coproc_mem_operand (rtx op, bool wb)
(plus (reg) (plus (reg)
(const)). */ (const)). */
if (GET_CODE (ind) == PLUS if (GET_CODE (ind) == PLUS
&& GET_CODE (XEXP (ind, 0)) == REG && REG_P (XEXP (ind, 0))
&& REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
&& GET_CODE (XEXP (ind, 1)) == CONST_INT && CONST_INT_P (XEXP (ind, 1))
&& INTVAL (XEXP (ind, 1)) > -1024 && INTVAL (XEXP (ind, 1)) > -1024
&& INTVAL (XEXP (ind, 1)) < 1024 && INTVAL (XEXP (ind, 1)) < 1024
&& (INTVAL (XEXP (ind, 1)) & 3) == 0) && (INTVAL (XEXP (ind, 1)) & 3) == 0)
...@@ -9596,7 +9596,7 @@ neon_vector_mem_operand (rtx op, int type) ...@@ -9596,7 +9596,7 @@ neon_vector_mem_operand (rtx op, int type)
return FALSE; return FALSE;
/* Constants are converted into offsets from labels. */ /* Constants are converted into offsets from labels. */
if (GET_CODE (op) != MEM) if (!MEM_P (op))
return FALSE; return FALSE;
ind = XEXP (op, 0); ind = XEXP (op, 0);
...@@ -9606,11 +9606,11 @@ neon_vector_mem_operand (rtx op, int type) ...@@ -9606,11 +9606,11 @@ neon_vector_mem_operand (rtx op, int type)
|| (GET_CODE (ind) == CONST || (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS && GET_CODE (XEXP (ind, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE; return TRUE;
/* Match: (mem (reg)). */ /* Match: (mem (reg)). */
if (GET_CODE (ind) == REG) if (REG_P (ind))
return arm_address_register_rtx_p (ind, 0); return arm_address_register_rtx_p (ind, 0);
/* Allow post-increment with Neon registers. */ /* Allow post-increment with Neon registers. */
...@@ -9625,9 +9625,9 @@ neon_vector_mem_operand (rtx op, int type) ...@@ -9625,9 +9625,9 @@ neon_vector_mem_operand (rtx op, int type)
(const)). */ (const)). */
if (type == 0 if (type == 0
&& GET_CODE (ind) == PLUS && GET_CODE (ind) == PLUS
&& GET_CODE (XEXP (ind, 0)) == REG && REG_P (XEXP (ind, 0))
&& REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
&& GET_CODE (XEXP (ind, 1)) == CONST_INT && CONST_INT_P (XEXP (ind, 1))
&& INTVAL (XEXP (ind, 1)) > -1024 && INTVAL (XEXP (ind, 1)) > -1024
&& INTVAL (XEXP (ind, 1)) < 1016 && INTVAL (XEXP (ind, 1)) < 1016
&& (INTVAL (XEXP (ind, 1)) & 3) == 0) && (INTVAL (XEXP (ind, 1)) & 3) == 0)
...@@ -9654,7 +9654,7 @@ neon_struct_mem_operand (rtx op) ...@@ -9654,7 +9654,7 @@ neon_struct_mem_operand (rtx op)
return FALSE; return FALSE;
/* Constants are converted into offsets from labels. */ /* Constants are converted into offsets from labels. */
if (GET_CODE (op) != MEM) if (!MEM_P (op))
return FALSE; return FALSE;
ind = XEXP (op, 0); ind = XEXP (op, 0);
...@@ -9664,11 +9664,11 @@ neon_struct_mem_operand (rtx op) ...@@ -9664,11 +9664,11 @@ neon_struct_mem_operand (rtx op)
|| (GET_CODE (ind) == CONST || (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS && GET_CODE (XEXP (ind, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE; return TRUE;
/* Match: (mem (reg)). */ /* Match: (mem (reg)). */
if (GET_CODE (ind) == REG) if (REG_P (ind))
return arm_address_register_rtx_p (ind, 0); return arm_address_register_rtx_p (ind, 0);
/* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */ /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
...@@ -9903,12 +9903,12 @@ adjacent_mem_locations (rtx a, rtx b) ...@@ -9903,12 +9903,12 @@ adjacent_mem_locations (rtx a, rtx b)
if (volatile_refs_p (a) || volatile_refs_p (b)) if (volatile_refs_p (a) || volatile_refs_p (b))
return 0; return 0;
if ((GET_CODE (XEXP (a, 0)) == REG if ((REG_P (XEXP (a, 0))
|| (GET_CODE (XEXP (a, 0)) == PLUS || (GET_CODE (XEXP (a, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) && CONST_INT_P (XEXP (XEXP (a, 0), 1))))
&& (GET_CODE (XEXP (b, 0)) == REG && (REG_P (XEXP (b, 0))
|| (GET_CODE (XEXP (b, 0)) == PLUS || (GET_CODE (XEXP (b, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) && CONST_INT_P (XEXP (XEXP (b, 0), 1)))))
{ {
HOST_WIDE_INT val0 = 0, val1 = 0; HOST_WIDE_INT val0 = 0, val1 = 0;
rtx reg0, reg1; rtx reg0, reg1;
...@@ -10292,7 +10292,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, ...@@ -10292,7 +10292,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
if (GET_CODE (operands[nops + i]) == SUBREG) if (GET_CODE (operands[nops + i]) == SUBREG)
operands[nops + i] = alter_subreg (operands + (nops + i)); operands[nops + i] = alter_subreg (operands + (nops + i));
gcc_assert (GET_CODE (operands[nops + i]) == MEM); gcc_assert (MEM_P (operands[nops + i]));
/* Don't reorder volatile memory references; it doesn't seem worth /* Don't reorder volatile memory references; it doesn't seem worth
looking for the case where the order is ok anyway. */ looking for the case where the order is ok anyway. */
...@@ -10301,16 +10301,15 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, ...@@ -10301,16 +10301,15 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
offset = const0_rtx; offset = const0_rtx;
if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG if ((REG_P (reg = XEXP (operands[nops + i], 0))
|| (GET_CODE (reg) == SUBREG || (GET_CODE (reg) == SUBREG
&& GET_CODE (reg = SUBREG_REG (reg)) == REG)) && REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
&& ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
== REG)
|| (GET_CODE (reg) == SUBREG || (GET_CODE (reg) == SUBREG
&& GET_CODE (reg = SUBREG_REG (reg)) == REG)) && REG_P (reg = SUBREG_REG (reg))))
&& (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) && (CONST_INT_P (offset
== CONST_INT))) = XEXP (XEXP (operands[nops + i], 0), 1)))))
{ {
if (i == 0) if (i == 0)
{ {
...@@ -10323,7 +10322,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, ...@@ -10323,7 +10322,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
/* Not addressed from the same base register. */ /* Not addressed from the same base register. */
return 0; return 0;
unsorted_regs[i] = (GET_CODE (operands[i]) == REG unsorted_regs[i] = (REG_P (operands[i])
? REGNO (operands[i]) ? REGNO (operands[i])
: REGNO (SUBREG_REG (operands[i]))); : REGNO (SUBREG_REG (operands[i])));
...@@ -10445,7 +10444,7 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total, ...@@ -10445,7 +10444,7 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
if (GET_CODE (operands[nops + i]) == SUBREG) if (GET_CODE (operands[nops + i]) == SUBREG)
operands[nops + i] = alter_subreg (operands + (nops + i)); operands[nops + i] = alter_subreg (operands + (nops + i));
gcc_assert (GET_CODE (operands[nops + i]) == MEM); gcc_assert (MEM_P (operands[nops + i]));
/* Don't reorder volatile memory references; it doesn't seem worth /* Don't reorder volatile memory references; it doesn't seem worth
looking for the case where the order is ok anyway. */ looking for the case where the order is ok anyway. */
...@@ -10454,18 +10453,17 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total, ...@@ -10454,18 +10453,17 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
offset = const0_rtx; offset = const0_rtx;
if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG if ((REG_P (reg = XEXP (operands[nops + i], 0))
|| (GET_CODE (reg) == SUBREG || (GET_CODE (reg) == SUBREG
&& GET_CODE (reg = SUBREG_REG (reg)) == REG)) && REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
&& ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) && ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
== REG)
|| (GET_CODE (reg) == SUBREG || (GET_CODE (reg) == SUBREG
&& GET_CODE (reg = SUBREG_REG (reg)) == REG)) && REG_P (reg = SUBREG_REG (reg))))
&& (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) && (CONST_INT_P (offset
== CONST_INT))) = XEXP (XEXP (operands[nops + i], 0), 1)))))
{ {
unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG unsorted_reg_rtxs[i] = (REG_P (operands[i])
? operands[i] : SUBREG_REG (operands[i])); ? operands[i] : SUBREG_REG (operands[i]));
unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]); unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]);
...@@ -11286,8 +11284,8 @@ arm_gen_movmemqi (rtx *operands) ...@@ -11286,8 +11284,8 @@ arm_gen_movmemqi (rtx *operands)
rtx part_bytes_reg = NULL; rtx part_bytes_reg = NULL;
rtx mem; rtx mem;
if (GET_CODE (operands[2]) != CONST_INT if (!CONST_INT_P (operands[2])
|| GET_CODE (operands[3]) != CONST_INT || !CONST_INT_P (operands[3])
|| INTVAL (operands[2]) > 64) || INTVAL (operands[2]) > 64)
return 0; return 0;
...@@ -11632,13 +11630,13 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) ...@@ -11632,13 +11630,13 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
equalities and unsigned inequalities). */ equalities and unsigned inequalities). */
if (GET_MODE (x) == SImode if (GET_MODE (x) == SImode
&& GET_CODE (x) == ASHIFT && GET_CODE (x) == ASHIFT
&& GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 24
&& GET_CODE (XEXP (x, 0)) == SUBREG && GET_CODE (XEXP (x, 0)) == SUBREG
&& GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM && MEM_P (SUBREG_REG (XEXP (x, 0)))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
&& (op == EQ || op == NE && (op == EQ || op == NE
|| op == GEU || op == GTU || op == LTU || op == LEU) || op == GEU || op == GTU || op == LTU || op == LEU)
&& GET_CODE (y) == CONST_INT) && CONST_INT_P (y))
return CC_Zmode; return CC_Zmode;
/* A construct for a conditional compare, if the false arm contains /* A construct for a conditional compare, if the false arm contains
...@@ -11828,7 +11826,7 @@ arm_reload_in_hi (rtx *operands) ...@@ -11828,7 +11826,7 @@ arm_reload_in_hi (rtx *operands)
ref = SUBREG_REG (ref); ref = SUBREG_REG (ref);
} }
if (GET_CODE (ref) == REG) if (REG_P (ref))
{ {
/* We have a pseudo which has been spilt onto the stack; there /* We have a pseudo which has been spilt onto the stack; there
are two cases here: the first where there is a simple are two cases here: the first where there is a simple
...@@ -11848,7 +11846,7 @@ arm_reload_in_hi (rtx *operands) ...@@ -11848,7 +11846,7 @@ arm_reload_in_hi (rtx *operands)
/* Handle the case where the address is too complex to be offset by 1. */ /* Handle the case where the address is too complex to be offset by 1. */
if (GET_CODE (base) == MINUS if (GET_CODE (base) == MINUS
|| (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1))))
{ {
rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
...@@ -11945,7 +11943,7 @@ arm_reload_out_hi (rtx *operands) ...@@ -11945,7 +11943,7 @@ arm_reload_out_hi (rtx *operands)
ref = SUBREG_REG (ref); ref = SUBREG_REG (ref);
} }
if (GET_CODE (ref) == REG) if (REG_P (ref))
{ {
/* We have a pseudo which has been spilt onto the stack; there /* We have a pseudo which has been spilt onto the stack; there
are two cases here: the first where there is a simple are two cases here: the first where there is a simple
...@@ -11967,7 +11965,7 @@ arm_reload_out_hi (rtx *operands) ...@@ -11967,7 +11965,7 @@ arm_reload_out_hi (rtx *operands)
/* Handle the case where the address is too complex to be offset by 1. */ /* Handle the case where the address is too complex to be offset by 1. */
if (GET_CODE (base) == MINUS if (GET_CODE (base) == MINUS
|| (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) || (GET_CODE (base) == PLUS && !CONST_INT_P (XEXP (base, 1))))
{ {
rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
...@@ -12352,7 +12350,7 @@ is_jump_table (rtx insn) ...@@ -12352,7 +12350,7 @@ is_jump_table (rtx insn)
&& ((table = next_real_insn (JUMP_LABEL (insn))) && ((table = next_real_insn (JUMP_LABEL (insn)))
== next_real_insn (insn)) == next_real_insn (insn))
&& table != NULL && table != NULL
&& GET_CODE (table) == JUMP_INSN && JUMP_P (table)
&& (GET_CODE (PATTERN (table)) == ADDR_VEC && (GET_CODE (PATTERN (table)) == ADDR_VEC
|| GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
return table; return table;
...@@ -12498,7 +12496,7 @@ add_minipool_forward_ref (Mfix *fix) ...@@ -12498,7 +12496,7 @@ add_minipool_forward_ref (Mfix *fix)
{ {
if (GET_CODE (fix->value) == GET_CODE (mp->value) if (GET_CODE (fix->value) == GET_CODE (mp->value)
&& fix->mode == mp->mode && fix->mode == mp->mode
&& (GET_CODE (fix->value) != CODE_LABEL && (!LABEL_P (fix->value)
|| (CODE_LABEL_NUMBER (fix->value) || (CODE_LABEL_NUMBER (fix->value)
== CODE_LABEL_NUMBER (mp->value))) == CODE_LABEL_NUMBER (mp->value)))
&& rtx_equal_p (fix->value, mp->value)) && rtx_equal_p (fix->value, mp->value))
...@@ -12675,7 +12673,7 @@ add_minipool_backward_ref (Mfix *fix) ...@@ -12675,7 +12673,7 @@ add_minipool_backward_ref (Mfix *fix)
{ {
if (GET_CODE (fix->value) == GET_CODE (mp->value) if (GET_CODE (fix->value) == GET_CODE (mp->value)
&& fix->mode == mp->mode && fix->mode == mp->mode
&& (GET_CODE (fix->value) != CODE_LABEL && (!LABEL_P (fix->value)
|| (CODE_LABEL_NUMBER (fix->value) || (CODE_LABEL_NUMBER (fix->value)
== CODE_LABEL_NUMBER (mp->value))) == CODE_LABEL_NUMBER (mp->value)))
&& rtx_equal_p (fix->value, mp->value) && rtx_equal_p (fix->value, mp->value)
...@@ -12907,7 +12905,7 @@ arm_barrier_cost (rtx insn) ...@@ -12907,7 +12905,7 @@ arm_barrier_cost (rtx insn)
int base_cost = 50; int base_cost = 50;
rtx next = next_nonnote_insn (insn); rtx next = next_nonnote_insn (insn);
if (next != NULL && GET_CODE (next) == CODE_LABEL) if (next != NULL && LABEL_P (next))
base_cost -= 20; base_cost -= 20;
switch (GET_CODE (insn)) switch (GET_CODE (insn))
...@@ -12958,7 +12956,7 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) ...@@ -12958,7 +12956,7 @@ create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
/* This code shouldn't have been called if there was a natural barrier /* This code shouldn't have been called if there was a natural barrier
within range. */ within range. */
gcc_assert (GET_CODE (from) != BARRIER); gcc_assert (!BARRIER_P (from));
/* Count the length of this insn. This must stay in sync with the /* Count the length of this insn. This must stay in sync with the
code that pushes minipool fixes. */ code that pushes minipool fixes. */
...@@ -13125,8 +13123,8 @@ arm_const_double_inline_cost (rtx val) ...@@ -13125,8 +13123,8 @@ arm_const_double_inline_cost (rtx val)
lowpart = gen_lowpart (SImode, val); lowpart = gen_lowpart (SImode, val);
highpart = gen_highpart_mode (SImode, mode, val); highpart = gen_highpart_mode (SImode, mode, val);
gcc_assert (GET_CODE (lowpart) == CONST_INT); gcc_assert (CONST_INT_P (lowpart));
gcc_assert (GET_CODE (highpart) == CONST_INT); gcc_assert (CONST_INT_P (highpart));
return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
NULL_RTX, NULL_RTX, 0, 0) NULL_RTX, NULL_RTX, 0, 0)
...@@ -13152,7 +13150,7 @@ arm_const_double_by_parts (rtx val) ...@@ -13152,7 +13150,7 @@ arm_const_double_by_parts (rtx val)
part = gen_highpart_mode (SImode, mode, val); part = gen_highpart_mode (SImode, mode, val);
gcc_assert (GET_CODE (part) == CONST_INT); gcc_assert (CONST_INT_P (part));
if (const_ok_for_arm (INTVAL (part)) if (const_ok_for_arm (INTVAL (part))
|| const_ok_for_arm (~INTVAL (part))) || const_ok_for_arm (~INTVAL (part)))
...@@ -13160,7 +13158,7 @@ arm_const_double_by_parts (rtx val) ...@@ -13160,7 +13158,7 @@ arm_const_double_by_parts (rtx val)
part = gen_lowpart (SImode, val); part = gen_lowpart (SImode, val);
gcc_assert (GET_CODE (part) == CONST_INT); gcc_assert (CONST_INT_P (part));
if (const_ok_for_arm (INTVAL (part)) if (const_ok_for_arm (INTVAL (part))
|| const_ok_for_arm (~INTVAL (part))) || const_ok_for_arm (~INTVAL (part)))
...@@ -13182,14 +13180,14 @@ arm_const_double_by_immediates (rtx val) ...@@ -13182,14 +13180,14 @@ arm_const_double_by_immediates (rtx val)
part = gen_highpart_mode (SImode, mode, val); part = gen_highpart_mode (SImode, mode, val);
gcc_assert (GET_CODE (part) == CONST_INT); gcc_assert (CONST_INT_P (part));
if (!const_ok_for_arm (INTVAL (part))) if (!const_ok_for_arm (INTVAL (part)))
return false; return false;
part = gen_lowpart (SImode, val); part = gen_lowpart (SImode, val);
gcc_assert (GET_CODE (part) == CONST_INT); gcc_assert (CONST_INT_P (part));
if (!const_ok_for_arm (INTVAL (part))) if (!const_ok_for_arm (INTVAL (part)))
return false; return false;
...@@ -13237,7 +13235,7 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) ...@@ -13237,7 +13235,7 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
push_minipool_fix (insn, address, recog_data.operand_loc[opno], push_minipool_fix (insn, address, recog_data.operand_loc[opno],
recog_data.operand_mode[opno], op); recog_data.operand_mode[opno], op);
} }
else if (GET_CODE (op) == MEM else if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == SYMBOL_REF && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
{ {
...@@ -13476,13 +13474,13 @@ arm_reorg (void) ...@@ -13476,13 +13474,13 @@ arm_reorg (void)
/* The first insn must always be a note, or the code below won't /* The first insn must always be a note, or the code below won't
scan it properly. */ scan it properly. */
insn = get_insns (); insn = get_insns ();
gcc_assert (GET_CODE (insn) == NOTE); gcc_assert (NOTE_P (insn));
minipool_pad = 0; minipool_pad = 0;
/* Scan all the insns and record the operands that will need fixing. */ /* Scan all the insns and record the operands that will need fixing. */
for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
{ {
if (GET_CODE (insn) == BARRIER) if (BARRIER_P (insn))
push_minipool_barrier (insn, address); push_minipool_barrier (insn, address);
else if (INSN_P (insn)) else if (INSN_P (insn))
{ {
...@@ -13518,7 +13516,7 @@ arm_reorg (void) ...@@ -13518,7 +13516,7 @@ arm_reorg (void)
Mfix * this_fix; Mfix * this_fix;
/* Skip any further barriers before the next fix. */ /* Skip any further barriers before the next fix. */
while (fix && GET_CODE (fix->insn) == BARRIER) while (fix && BARRIER_P (fix->insn))
fix = fix->next; fix = fix->next;
/* No more fixes. */ /* No more fixes. */
...@@ -13529,7 +13527,7 @@ arm_reorg (void) ...@@ -13529,7 +13527,7 @@ arm_reorg (void)
for (ftmp = fix; ftmp; ftmp = ftmp->next) for (ftmp = fix; ftmp; ftmp = ftmp->next)
{ {
if (GET_CODE (ftmp->insn) == BARRIER) if (BARRIER_P (ftmp->insn))
{ {
if (ftmp->address >= minipool_vector_head->max_address) if (ftmp->address >= minipool_vector_head->max_address)
break; break;
...@@ -13589,7 +13587,7 @@ arm_reorg (void) ...@@ -13589,7 +13587,7 @@ arm_reorg (void)
while (ftmp) while (ftmp)
{ {
if (GET_CODE (ftmp->insn) != BARRIER if (!BARRIER_P (ftmp->insn)
&& ((ftmp->minipool = add_minipool_backward_ref (ftmp)) && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
== NULL)) == NULL))
break; break;
...@@ -13601,7 +13599,7 @@ arm_reorg (void) ...@@ -13601,7 +13599,7 @@ arm_reorg (void)
up and adding the constants to the pool itself. */ up and adding the constants to the pool itself. */
for (this_fix = fix; this_fix && ftmp != this_fix; for (this_fix = fix; this_fix && ftmp != this_fix;
this_fix = this_fix->next) this_fix = this_fix->next)
if (GET_CODE (this_fix->insn) != BARRIER) if (!BARRIER_P (this_fix->insn))
{ {
rtx addr rtx addr
= plus_constant (Pmode, = plus_constant (Pmode,
...@@ -13744,7 +13742,7 @@ vfp_output_fstmd (rtx * operands) ...@@ -13744,7 +13742,7 @@ vfp_output_fstmd (rtx * operands)
strcpy (pattern, "fstmfdd%?\t%m0!, {%P1"); strcpy (pattern, "fstmfdd%?\t%m0!, {%P1");
p = strlen (pattern); p = strlen (pattern);
gcc_assert (GET_CODE (operands[1]) == REG); gcc_assert (REG_P (operands[1]));
base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
for (i = 1; i < XVECLEN (operands[2], 0); i++) for (i = 1; i < XVECLEN (operands[2], 0); i++)
...@@ -14085,7 +14083,7 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14085,7 +14083,7 @@ output_move_double (rtx *operands, bool emit, int *count)
FIXME: IWMMXT allows offsets larger than ldrd can FIXME: IWMMXT allows offsets larger than ldrd can
handle, fix these up with a pair of ldr. */ handle, fix these up with a pair of ldr. */
if (TARGET_THUMB2 if (TARGET_THUMB2
|| GET_CODE (otherops[2]) != CONST_INT || !CONST_INT_P (otherops[2])
|| (INTVAL (otherops[2]) > -256 || (INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256)) && INTVAL (otherops[2]) < 256))
{ {
...@@ -14111,7 +14109,7 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14111,7 +14109,7 @@ output_move_double (rtx *operands, bool emit, int *count)
FIXME: IWMMXT allows offsets larger than ldrd can handle, FIXME: IWMMXT allows offsets larger than ldrd can handle,
fix these up with a pair of ldr. */ fix these up with a pair of ldr. */
if (TARGET_THUMB2 if (TARGET_THUMB2
|| GET_CODE (otherops[2]) != CONST_INT || !CONST_INT_P (otherops[2])
|| (INTVAL (otherops[2]) > -256 || (INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256)) && INTVAL (otherops[2]) < 256))
{ {
...@@ -14165,7 +14163,7 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14165,7 +14163,7 @@ output_move_double (rtx *operands, bool emit, int *count)
if (GET_CODE (XEXP (operands[1], 0)) == PLUS) if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
{ {
if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) if (CONST_INT_P (otherops[2]) && !TARGET_LDRD)
{ {
switch ((int) INTVAL (otherops[2])) switch ((int) INTVAL (otherops[2]))
{ {
...@@ -14190,9 +14188,9 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14190,9 +14188,9 @@ output_move_double (rtx *operands, bool emit, int *count)
otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1); otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1);
operands[1] = otherops[0]; operands[1] = otherops[0];
if (TARGET_LDRD if (TARGET_LDRD
&& (GET_CODE (otherops[2]) == REG && (REG_P (otherops[2])
|| TARGET_THUMB2 || TARGET_THUMB2
|| (GET_CODE (otherops[2]) == CONST_INT || (CONST_INT_P (otherops[2])
&& INTVAL (otherops[2]) > -256 && INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256))) && INTVAL (otherops[2]) < 256)))
{ {
...@@ -14228,7 +14226,7 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14228,7 +14226,7 @@ output_move_double (rtx *operands, bool emit, int *count)
return ""; return "";
} }
if (GET_CODE (otherops[2]) == CONST_INT) if (CONST_INT_P (otherops[2]))
{ {
if (emit) if (emit)
{ {
...@@ -14345,7 +14343,7 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14345,7 +14343,7 @@ output_move_double (rtx *operands, bool emit, int *count)
/* IWMMXT allows offsets larger than ldrd can handle, /* IWMMXT allows offsets larger than ldrd can handle,
fix these up with a pair of ldr. */ fix these up with a pair of ldr. */
if (!TARGET_THUMB2 if (!TARGET_THUMB2
&& GET_CODE (otherops[2]) == CONST_INT && CONST_INT_P (otherops[2])
&& (INTVAL(otherops[2]) <= -256 && (INTVAL(otherops[2]) <= -256
|| INTVAL(otherops[2]) >= 256)) || INTVAL(otherops[2]) >= 256))
{ {
...@@ -14384,7 +14382,7 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14384,7 +14382,7 @@ output_move_double (rtx *operands, bool emit, int *count)
case PLUS: case PLUS:
otherops[2] = XEXP (XEXP (operands[0], 0), 1); otherops[2] = XEXP (XEXP (operands[0], 0), 1);
if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) if (CONST_INT_P (otherops[2]) && !TARGET_LDRD)
{ {
switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
{ {
...@@ -14409,9 +14407,9 @@ output_move_double (rtx *operands, bool emit, int *count) ...@@ -14409,9 +14407,9 @@ output_move_double (rtx *operands, bool emit, int *count)
} }
} }
if (TARGET_LDRD if (TARGET_LDRD
&& (GET_CODE (otherops[2]) == REG && (REG_P (otherops[2])
|| TARGET_THUMB2 || TARGET_THUMB2
|| (GET_CODE (otherops[2]) == CONST_INT || (CONST_INT_P (otherops[2])
&& INTVAL (otherops[2]) > -256 && INTVAL (otherops[2]) > -256
&& INTVAL (otherops[2]) < 256))) && INTVAL (otherops[2]) < 256)))
{ {
...@@ -14761,10 +14759,10 @@ arm_address_offset_is_imm (rtx insn) ...@@ -14761,10 +14759,10 @@ arm_address_offset_is_imm (rtx insn)
addr = XEXP (mem, 0); addr = XEXP (mem, 0);
if (GET_CODE (addr) == REG if (REG_P (addr)
|| (GET_CODE (addr) == PLUS || (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == REG && REG_P (XEXP (addr, 0))
&& GET_CODE (XEXP (addr, 1)) == CONST_INT)) && CONST_INT_P (XEXP (addr, 1))))
return 1; return 1;
else else
return 0; return 0;
...@@ -16910,7 +16908,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -16910,7 +16908,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
case 'B': case 'B':
if (GET_CODE (x) == CONST_INT) if (CONST_INT_P (x))
{ {
HOST_WIDE_INT val; HOST_WIDE_INT val;
val = ARM_SIGN_EXTEND (~INTVAL (x)); val = ARM_SIGN_EXTEND (~INTVAL (x));
...@@ -16991,14 +16989,14 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -16991,14 +16989,14 @@ arm_print_operand (FILE *stream, rtx x, int code)
The 'Q' and 'R' constraints are also available for 64-bit The 'Q' and 'R' constraints are also available for 64-bit
constants. */ constants. */
case 'Q': case 'Q':
if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
{ {
rtx part = gen_lowpart (SImode, x); rtx part = gen_lowpart (SImode, x);
fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
return; return;
} }
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17008,7 +17006,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17008,7 +17006,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
case 'R': case 'R':
if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
{ {
enum machine_mode mode = GET_MODE (x); enum machine_mode mode = GET_MODE (x);
rtx part; rtx part;
...@@ -17020,7 +17018,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17020,7 +17018,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
} }
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17030,7 +17028,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17030,7 +17028,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
case 'H': case 'H':
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17040,7 +17038,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17040,7 +17038,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
case 'J': case 'J':
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17050,7 +17048,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17050,7 +17048,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
case 'K': case 'K':
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) if (!REG_P (x) || REGNO (x) > LAST_ARM_REGNUM)
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17061,7 +17059,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17061,7 +17059,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
case 'm': case 'm':
asm_fprintf (stream, "%r", asm_fprintf (stream, "%r",
GET_CODE (XEXP (x, 0)) == REG REG_P (XEXP (x, 0))
? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
return; return;
...@@ -17129,7 +17127,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17129,7 +17127,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
case 'U': case 'U':
if (GET_CODE (x) != REG if (!REG_P (x)
|| REGNO (x) < FIRST_IWMMXT_GR_REGNUM || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
|| REGNO (x) > LAST_IWMMXT_GR_REGNUM) || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
/* Bad value for wCG register number. */ /* Bad value for wCG register number. */
...@@ -17144,7 +17142,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17144,7 +17142,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
/* Print an iWMMXt control register name. */ /* Print an iWMMXt control register name. */
case 'w': case 'w':
if (GET_CODE (x) != CONST_INT if (!CONST_INT_P (x)
|| INTVAL (x) < 0 || INTVAL (x) < 0
|| INTVAL (x) >= 16) || INTVAL (x) >= 16)
/* Bad value for wC register number. */ /* Bad value for wC register number. */
...@@ -17174,7 +17172,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17174,7 +17172,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
int mode = GET_MODE (x); int mode = GET_MODE (x);
int regno; int regno;
if (GET_MODE_SIZE (mode) != 8 || GET_CODE (x) != REG) if (GET_MODE_SIZE (mode) != 8 || !REG_P (x))
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17205,7 +17203,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17205,7 +17203,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
} }
if (GET_CODE (x) != REG if (!REG_P (x)
|| !IS_VFP_REGNUM (REGNO (x))) || !IS_VFP_REGNUM (REGNO (x)))
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
...@@ -17235,7 +17233,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17235,7 +17233,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
int regno; int regno;
if ((GET_MODE_SIZE (mode) != 16 if ((GET_MODE_SIZE (mode) != 16
&& GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) && GET_MODE_SIZE (mode) != 32) || !REG_P (x))
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17315,7 +17313,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17315,7 +17313,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
bool postinc = FALSE; bool postinc = FALSE;
unsigned align, memsize, align_bits; unsigned align, memsize, align_bits;
gcc_assert (GET_CODE (x) == MEM); gcc_assert (MEM_P (x));
addr = XEXP (x, 0); addr = XEXP (x, 0);
if (GET_CODE (addr) == POST_INC) if (GET_CODE (addr) == POST_INC)
{ {
...@@ -17354,9 +17352,9 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17354,9 +17352,9 @@ arm_print_operand (FILE *stream, rtx x, int code)
{ {
rtx addr; rtx addr;
gcc_assert (GET_CODE (x) == MEM); gcc_assert (MEM_P (x));
addr = XEXP (x, 0); addr = XEXP (x, 0);
gcc_assert (GET_CODE (addr) == REG); gcc_assert (REG_P (addr));
asm_fprintf (stream, "[%r]", REGNO (addr)); asm_fprintf (stream, "[%r]", REGNO (addr));
} }
return; return;
...@@ -17367,7 +17365,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17367,7 +17365,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
int mode = GET_MODE (x); int mode = GET_MODE (x);
int regno; int regno;
if (GET_MODE_SIZE (mode) != 4 || GET_CODE (x) != REG) if (GET_MODE_SIZE (mode) != 4 || !REG_P (x))
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17386,7 +17384,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17386,7 +17384,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
return; return;
case 'v': case 'v':
gcc_assert (GET_CODE (x) == CONST_DOUBLE); gcc_assert (CONST_DOUBLE_P (x));
fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x)); fprintf (stream, "#%d", vfp3_const_double_for_fract_bits (x));
return; return;
...@@ -17397,7 +17395,7 @@ arm_print_operand (FILE *stream, rtx x, int code) ...@@ -17397,7 +17395,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
int mode = GET_MODE (x); int mode = GET_MODE (x);
int regno; int regno;
if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG) if (GET_MODE_SIZE (mode) != 2 || !REG_P (x))
{ {
output_operand_lossage ("invalid operand for code '%c'", code); output_operand_lossage ("invalid operand for code '%c'", code);
return; return;
...@@ -17468,15 +17466,15 @@ arm_print_operand_address (FILE *stream, rtx x) ...@@ -17468,15 +17466,15 @@ arm_print_operand_address (FILE *stream, rtx x)
{ {
int is_minus = GET_CODE (x) == MINUS; int is_minus = GET_CODE (x) == MINUS;
if (GET_CODE (x) == REG) if (REG_P (x))
asm_fprintf (stream, "[%r]", REGNO (x)); asm_fprintf (stream, "[%r]", REGNO (x));
else if (GET_CODE (x) == PLUS || is_minus) else if (GET_CODE (x) == PLUS || is_minus)
{ {
rtx base = XEXP (x, 0); rtx base = XEXP (x, 0);
rtx index = XEXP (x, 1); rtx index = XEXP (x, 1);
HOST_WIDE_INT offset = 0; HOST_WIDE_INT offset = 0;
if (GET_CODE (base) != REG if (!REG_P (base)
|| (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) || (REG_P (index) && REGNO (index) == SP_REGNUM))
{ {
/* Ensure that BASE is a register. */ /* Ensure that BASE is a register. */
/* (one of them must be). */ /* (one of them must be). */
...@@ -17524,7 +17522,7 @@ arm_print_operand_address (FILE *stream, rtx x) ...@@ -17524,7 +17522,7 @@ arm_print_operand_address (FILE *stream, rtx x)
{ {
extern enum machine_mode output_memory_reference_mode; extern enum machine_mode output_memory_reference_mode;
gcc_assert (GET_CODE (XEXP (x, 0)) == REG); gcc_assert (REG_P (XEXP (x, 0)));
if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC) if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC)
asm_fprintf (stream, "[%r, #%s%d]!", asm_fprintf (stream, "[%r, #%s%d]!",
...@@ -17540,7 +17538,7 @@ arm_print_operand_address (FILE *stream, rtx x) ...@@ -17540,7 +17538,7 @@ arm_print_operand_address (FILE *stream, rtx x)
else if (GET_CODE (x) == PRE_MODIFY) else if (GET_CODE (x) == PRE_MODIFY)
{ {
asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0))); asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0)));
if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) if (CONST_INT_P (XEXP (XEXP (x, 1), 1)))
asm_fprintf (stream, "#%wd]!", asm_fprintf (stream, "#%wd]!",
INTVAL (XEXP (XEXP (x, 1), 1))); INTVAL (XEXP (XEXP (x, 1), 1)));
else else
...@@ -17550,7 +17548,7 @@ arm_print_operand_address (FILE *stream, rtx x) ...@@ -17550,7 +17548,7 @@ arm_print_operand_address (FILE *stream, rtx x)
else if (GET_CODE (x) == POST_MODIFY) else if (GET_CODE (x) == POST_MODIFY)
{ {
asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0))); asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0)));
if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) if (CONST_INT_P (XEXP (XEXP (x, 1), 1)))
asm_fprintf (stream, "#%wd", asm_fprintf (stream, "#%wd",
INTVAL (XEXP (XEXP (x, 1), 1))); INTVAL (XEXP (XEXP (x, 1), 1)));
else else
...@@ -17561,14 +17559,14 @@ arm_print_operand_address (FILE *stream, rtx x) ...@@ -17561,14 +17559,14 @@ arm_print_operand_address (FILE *stream, rtx x)
} }
else else
{ {
if (GET_CODE (x) == REG) if (REG_P (x))
asm_fprintf (stream, "[%r]", REGNO (x)); asm_fprintf (stream, "[%r]", REGNO (x));
else if (GET_CODE (x) == POST_INC) else if (GET_CODE (x) == POST_INC)
asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0))); asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0)));
else if (GET_CODE (x) == PLUS) else if (GET_CODE (x) == PLUS)
{ {
gcc_assert (GET_CODE (XEXP (x, 0)) == REG); gcc_assert (REG_P (XEXP (x, 0)));
if (GET_CODE (XEXP (x, 1)) == CONST_INT) if (CONST_INT_P (XEXP (x, 1)))
asm_fprintf (stream, "[%r, #%wd]", asm_fprintf (stream, "[%r, #%wd]",
REGNO (XEXP (x, 0)), REGNO (XEXP (x, 0)),
INTVAL (XEXP (x, 1))); INTVAL (XEXP (x, 1)));
...@@ -17931,7 +17929,7 @@ thumb2_final_prescan_insn (rtx insn) ...@@ -17931,7 +17929,7 @@ thumb2_final_prescan_insn (rtx insn)
return; return;
/* Conditional jumps are implemented directly. */ /* Conditional jumps are implemented directly. */
if (GET_CODE (insn) == JUMP_INSN) if (JUMP_P (insn))
return; return;
predicate = COND_EXEC_TEST (body); predicate = COND_EXEC_TEST (body);
...@@ -17948,7 +17946,7 @@ thumb2_final_prescan_insn (rtx insn) ...@@ -17948,7 +17946,7 @@ thumb2_final_prescan_insn (rtx insn)
/* Jumping into the middle of an IT block is illegal, so a label or /* Jumping into the middle of an IT block is illegal, so a label or
barrier terminates the block. */ barrier terminates the block. */
if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN) if (!NONJUMP_INSN_P (insn) && !JUMP_P (insn))
break; break;
body = PATTERN (insn); body = PATTERN (insn);
...@@ -17977,7 +17975,7 @@ thumb2_final_prescan_insn (rtx insn) ...@@ -17977,7 +17975,7 @@ thumb2_final_prescan_insn (rtx insn)
arm_condexec_masklen += n; arm_condexec_masklen += n;
/* A jump must be the last instruction in a conditional block. */ /* A jump must be the last instruction in a conditional block. */
if (GET_CODE(insn) == JUMP_INSN) if (JUMP_P (insn))
break; break;
} }
/* Restore recog_data (getting the attributes of other insns can /* Restore recog_data (getting the attributes of other insns can
...@@ -18025,12 +18023,12 @@ arm_final_prescan_insn (rtx insn) ...@@ -18025,12 +18023,12 @@ arm_final_prescan_insn (rtx insn)
if (simplejump_p (insn)) if (simplejump_p (insn))
{ {
start_insn = next_nonnote_insn (start_insn); start_insn = next_nonnote_insn (start_insn);
if (GET_CODE (start_insn) == BARRIER) if (BARRIER_P (start_insn))
{ {
/* XXX Isn't this always a barrier? */ /* XXX Isn't this always a barrier? */
start_insn = next_nonnote_insn (start_insn); start_insn = next_nonnote_insn (start_insn);
} }
if (GET_CODE (start_insn) == CODE_LABEL if (LABEL_P (start_insn)
&& CODE_LABEL_NUMBER (start_insn) == arm_target_label && CODE_LABEL_NUMBER (start_insn) == arm_target_label
&& LABEL_NUSES (start_insn) == 1) && LABEL_NUSES (start_insn) == 1)
reverse = TRUE; reverse = TRUE;
...@@ -18040,9 +18038,9 @@ arm_final_prescan_insn (rtx insn) ...@@ -18040,9 +18038,9 @@ arm_final_prescan_insn (rtx insn)
else if (ANY_RETURN_P (body)) else if (ANY_RETURN_P (body))
{ {
start_insn = next_nonnote_insn (start_insn); start_insn = next_nonnote_insn (start_insn);
if (GET_CODE (start_insn) == BARRIER) if (BARRIER_P (start_insn))
start_insn = next_nonnote_insn (start_insn); start_insn = next_nonnote_insn (start_insn);
if (GET_CODE (start_insn) == CODE_LABEL if (LABEL_P (start_insn)
&& CODE_LABEL_NUMBER (start_insn) == arm_target_label && CODE_LABEL_NUMBER (start_insn) == arm_target_label
&& LABEL_NUSES (start_insn) == 1) && LABEL_NUSES (start_insn) == 1)
{ {
...@@ -18058,7 +18056,7 @@ arm_final_prescan_insn (rtx insn) ...@@ -18058,7 +18056,7 @@ arm_final_prescan_insn (rtx insn)
} }
gcc_assert (!arm_ccfsm_state || reverse); gcc_assert (!arm_ccfsm_state || reverse);
if (GET_CODE (insn) != JUMP_INSN) if (!JUMP_P (insn))
return; return;
/* This jump might be paralleled with a clobber of the condition codes /* This jump might be paralleled with a clobber of the condition codes
...@@ -18159,7 +18157,7 @@ arm_final_prescan_insn (rtx insn) ...@@ -18159,7 +18157,7 @@ arm_final_prescan_insn (rtx insn)
if the following two insns are a barrier and the if the following two insns are a barrier and the
target label. */ target label. */
this_insn = next_nonnote_insn (this_insn); this_insn = next_nonnote_insn (this_insn);
if (this_insn && GET_CODE (this_insn) == BARRIER) if (this_insn && BARRIER_P (this_insn))
this_insn = next_nonnote_insn (this_insn); this_insn = next_nonnote_insn (this_insn);
if (this_insn && this_insn == label if (this_insn && this_insn == label
...@@ -18245,8 +18243,8 @@ arm_final_prescan_insn (rtx insn) ...@@ -18245,8 +18243,8 @@ arm_final_prescan_insn (rtx insn)
{ {
this_insn = next_nonnote_insn (this_insn); this_insn = next_nonnote_insn (this_insn);
gcc_assert (!this_insn gcc_assert (!this_insn
|| (GET_CODE (this_insn) != BARRIER || (!BARRIER_P (this_insn)
&& GET_CODE (this_insn) != CODE_LABEL)); && !LABEL_P (this_insn)));
} }
if (!this_insn) if (!this_insn)
{ {
...@@ -18445,7 +18443,7 @@ arm_debugger_arg_offset (int value, rtx addr) ...@@ -18445,7 +18443,7 @@ arm_debugger_arg_offset (int value, rtx addr)
return 0; return 0;
/* We can only cope with the case where the address is held in a register. */ /* We can only cope with the case where the address is held in a register. */
if (GET_CODE (addr) != REG) if (!REG_P (addr))
return 0; return 0;
/* If we are using the frame pointer to point at the argument, then /* If we are using the frame pointer to point at the argument, then
...@@ -18492,13 +18490,13 @@ arm_debugger_arg_offset (int value, rtx addr) ...@@ -18492,13 +18490,13 @@ arm_debugger_arg_offset (int value, rtx addr)
for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{ {
if ( GET_CODE (insn) == INSN if ( NONJUMP_INSN_P (insn)
&& GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (insn)) == SET
&& REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
&& GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
&& GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG && REG_P (XEXP (XEXP (PATTERN (insn), 1), 0))
&& REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
&& GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT && CONST_INT_P (XEXP (XEXP (PATTERN (insn), 1), 1))
) )
{ {
value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
...@@ -20873,7 +20871,7 @@ arm_expand_builtin (tree exp, ...@@ -20873,7 +20871,7 @@ arm_expand_builtin (tree exp,
op0 = expand_normal (arg0); op0 = expand_normal (arg0);
op1 = expand_normal (arg1); op1 = expand_normal (arg1);
op2 = expand_normal (arg2); op2 = expand_normal (arg2);
if (GET_CODE (op2) == CONST_INT) if (CONST_INT_P (op2))
{ {
icode = CODE_FOR_iwmmxt_waligni; icode = CODE_FOR_iwmmxt_waligni;
tmode = insn_data[icode].operand[0].mode; tmode = insn_data[icode].operand[0].mode;
...@@ -21815,7 +21813,7 @@ thumb_far_jump_used_p (void) ...@@ -21815,7 +21813,7 @@ thumb_far_jump_used_p (void)
insn with the far jump attribute set. */ insn with the far jump attribute set. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{ {
if (GET_CODE (insn) == JUMP_INSN if (JUMP_P (insn)
/* Ignore tablejump patterns. */ /* Ignore tablejump patterns. */
&& GET_CODE (PATTERN (insn)) != ADDR_VEC && GET_CODE (PATTERN (insn)) != ADDR_VEC
&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
...@@ -22983,7 +22981,7 @@ thumb1_output_interwork (void) ...@@ -22983,7 +22981,7 @@ thumb1_output_interwork (void)
const char * name; const char * name;
FILE *f = asm_out_file; FILE *f = asm_out_file;
gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); gcc_assert (MEM_P (DECL_RTL (current_function_decl)));
gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
== SYMBOL_REF); == SYMBOL_REF);
name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
...@@ -23027,8 +23025,8 @@ thumb_load_double_from_address (rtx *operands) ...@@ -23027,8 +23025,8 @@ thumb_load_double_from_address (rtx *operands)
rtx arg1; rtx arg1;
rtx arg2; rtx arg2;
gcc_assert (GET_CODE (operands[0]) == REG); gcc_assert (REG_P (operands[0]));
gcc_assert (GET_CODE (operands[1]) == MEM); gcc_assert (MEM_P (operands[1]));
/* Get the memory address. */ /* Get the memory address. */
addr = XEXP (operands[1], 0); addr = XEXP (operands[1], 0);
...@@ -23068,10 +23066,10 @@ thumb_load_double_from_address (rtx *operands) ...@@ -23068,10 +23066,10 @@ thumb_load_double_from_address (rtx *operands)
else else
base = arg1, offset = arg2; base = arg1, offset = arg2;
gcc_assert (GET_CODE (base) == REG); gcc_assert (REG_P (base));
/* Catch the case of <address> = <reg> + <reg> */ /* Catch the case of <address> = <reg> + <reg> */
if (GET_CODE (offset) == REG) if (REG_P (offset))
{ {
int reg_offset = REGNO (offset); int reg_offset = REGNO (offset);
int reg_base = REGNO (base); int reg_base = REGNO (base);
...@@ -23671,10 +23669,10 @@ arm_output_load_gr (rtx *operands) ...@@ -23671,10 +23669,10 @@ arm_output_load_gr (rtx *operands)
rtx wcgr; rtx wcgr;
rtx sum; rtx sum;
if (GET_CODE (operands [1]) != MEM if (!MEM_P (operands [1])
|| GET_CODE (sum = XEXP (operands [1], 0)) != PLUS || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
|| GET_CODE (reg = XEXP (sum, 0)) != REG || !REG_P (reg = XEXP (sum, 0))
|| GET_CODE (offset = XEXP (sum, 1)) != CONST_INT || !CONST_INT_P (offset = XEXP (sum, 1))
|| ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
return "wldrw%?\t%0, %1"; return "wldrw%?\t%0, %1";
...@@ -23809,7 +23807,7 @@ arm_no_early_alu_shift_dep (rtx producer, rtx consumer) ...@@ -23809,7 +23807,7 @@ arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
/* This is either an actual independent shift, or a shift applied to /* This is either an actual independent shift, or a shift applied to
the first operand of another operation. We want the whole shift the first operand of another operation. We want the whole shift
operation. */ operation. */
if (GET_CODE (early_op) == REG) if (REG_P (early_op))
early_op = op; early_op = op;
return !reg_overlap_mentioned_p (value, early_op); return !reg_overlap_mentioned_p (value, early_op);
...@@ -23842,7 +23840,7 @@ arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) ...@@ -23842,7 +23840,7 @@ arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
/* This is either an actual independent shift, or a shift applied to /* This is either an actual independent shift, or a shift applied to
the first operand of another operation. We want the value being the first operand of another operation. We want the value being
shifted, in either case. */ shifted, in either case. */
if (GET_CODE (early_op) != REG) if (!REG_P (early_op))
early_op = XEXP (early_op, 0); early_op = XEXP (early_op, 0);
return !reg_overlap_mentioned_p (value, early_op); return !reg_overlap_mentioned_p (value, early_op);
...@@ -24342,7 +24340,7 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) ...@@ -24342,7 +24340,7 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
/* First insn will adjust the stack pointer. */ /* First insn will adjust the stack pointer. */
if (GET_CODE (e) != SET if (GET_CODE (e) != SET
|| GET_CODE (XEXP (e, 0)) != REG || !REG_P (XEXP (e, 0))
|| REGNO (XEXP (e, 0)) != SP_REGNUM || REGNO (XEXP (e, 0)) != SP_REGNUM
|| GET_CODE (XEXP (e, 1)) != PLUS) || GET_CODE (XEXP (e, 1)) != PLUS)
abort (); abort ();
...@@ -24386,8 +24384,8 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) ...@@ -24386,8 +24384,8 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
e = XVECEXP (p, 0, i); e = XVECEXP (p, 0, i);
if (GET_CODE (e) != SET if (GET_CODE (e) != SET
|| GET_CODE (XEXP (e, 0)) != MEM || !MEM_P (XEXP (e, 0))
|| GET_CODE (XEXP (e, 1)) != REG) || !REG_P (XEXP (e, 1)))
abort (); abort ();
reg = REGNO (XEXP (e, 1)); reg = REGNO (XEXP (e, 1));
...@@ -24409,14 +24407,14 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) ...@@ -24409,14 +24407,14 @@ arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
if (GET_CODE (e) == PLUS) if (GET_CODE (e) == PLUS)
{ {
offset += reg_size; offset += reg_size;
if (GET_CODE (XEXP (e, 0)) != REG if (!REG_P (XEXP (e, 0))
|| REGNO (XEXP (e, 0)) != SP_REGNUM || REGNO (XEXP (e, 0)) != SP_REGNUM
|| GET_CODE (XEXP (e, 1)) != CONST_INT || !CONST_INT_P (XEXP (e, 1))
|| offset != INTVAL (XEXP (e, 1))) || offset != INTVAL (XEXP (e, 1)))
abort (); abort ();
} }
else if (i != 1 else if (i != 1
|| GET_CODE (e) != REG || !REG_P (e)
|| REGNO (e) != SP_REGNUM) || REGNO (e) != SP_REGNUM)
abort (); abort ();
#endif #endif
...@@ -24440,7 +24438,7 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) ...@@ -24440,7 +24438,7 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p)
case MEM: case MEM:
/* Pushing a single register. */ /* Pushing a single register. */
if (GET_CODE (XEXP (e0, 0)) != PRE_DEC if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
|| GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG || !REG_P (XEXP (XEXP (e0, 0), 0))
|| REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
abort (); abort ();
...@@ -24457,9 +24455,9 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) ...@@ -24457,9 +24455,9 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p)
{ {
/* A stack increment. */ /* A stack increment. */
if (GET_CODE (e1) != PLUS if (GET_CODE (e1) != PLUS
|| GET_CODE (XEXP (e1, 0)) != REG || !REG_P (XEXP (e1, 0))
|| REGNO (XEXP (e1, 0)) != SP_REGNUM || REGNO (XEXP (e1, 0)) != SP_REGNUM
|| GET_CODE (XEXP (e1, 1)) != CONST_INT) || !CONST_INT_P (XEXP (e1, 1)))
abort (); abort ();
asm_fprintf (asm_out_file, "\t.pad #%wd\n", asm_fprintf (asm_out_file, "\t.pad #%wd\n",
...@@ -24471,8 +24469,8 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) ...@@ -24471,8 +24469,8 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p)
if (GET_CODE (e1) == PLUS) if (GET_CODE (e1) == PLUS)
{ {
if (GET_CODE (XEXP (e1, 0)) != REG if (!REG_P (XEXP (e1, 0))
|| GET_CODE (XEXP (e1, 1)) != CONST_INT) || !CONST_INT_P (XEXP (e1, 1)))
abort (); abort ();
reg = REGNO (XEXP (e1, 0)); reg = REGNO (XEXP (e1, 0));
offset = INTVAL (XEXP (e1, 1)); offset = INTVAL (XEXP (e1, 1));
...@@ -24480,7 +24478,7 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) ...@@ -24480,7 +24478,7 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p)
HARD_FRAME_POINTER_REGNUM, reg, HARD_FRAME_POINTER_REGNUM, reg,
offset); offset);
} }
else if (GET_CODE (e1) == REG) else if (REG_P (e1))
{ {
reg = REGNO (e1); reg = REGNO (e1);
asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
...@@ -24489,15 +24487,15 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p) ...@@ -24489,15 +24487,15 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p)
else else
abort (); abort ();
} }
else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) else if (REG_P (e1) && REGNO (e1) == SP_REGNUM)
{ {
/* Move from sp to reg. */ /* Move from sp to reg. */
asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
} }
else if (GET_CODE (e1) == PLUS else if (GET_CODE (e1) == PLUS
&& GET_CODE (XEXP (e1, 0)) == REG && REG_P (XEXP (e1, 0))
&& REGNO (XEXP (e1, 0)) == SP_REGNUM && REGNO (XEXP (e1, 0)) == SP_REGNUM
&& GET_CODE (XEXP (e1, 1)) == CONST_INT) && CONST_INT_P (XEXP (e1, 1)))
{ {
/* Set reg to offset from sp. */ /* Set reg to offset from sp. */
asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
...@@ -24607,7 +24605,7 @@ arm_output_ttype (rtx x) ...@@ -24607,7 +24605,7 @@ arm_output_ttype (rtx x)
fputs ("\t.word\t", asm_out_file); fputs ("\t.word\t", asm_out_file);
output_addr_const (asm_out_file, x); output_addr_const (asm_out_file, x);
/* Use special relocations for symbol references. */ /* Use special relocations for symbol references. */
if (GET_CODE (x) != CONST_INT) if (!CONST_INT_P (x))
fputs ("(TARGET2)", asm_out_file); fputs ("(TARGET2)", asm_out_file);
fputc ('\n', asm_out_file); fputc ('\n', asm_out_file);
...@@ -25294,7 +25292,7 @@ vfp3_const_double_for_fract_bits (rtx operand) ...@@ -25294,7 +25292,7 @@ vfp3_const_double_for_fract_bits (rtx operand)
{ {
REAL_VALUE_TYPE r0; REAL_VALUE_TYPE r0;
if (GET_CODE (operand) != CONST_DOUBLE) if (!CONST_DOUBLE_P (operand))
return 0; return 0;
REAL_VALUE_FROM_CONST_DOUBLE (r0, operand); REAL_VALUE_FROM_CONST_DOUBLE (r0, operand);
......
gcc/config/arm/arm.h
...@@ -1262,8 +1262,8 @@ enum reg_class ...@@ -1262,8 +1262,8 @@ enum reg_class
&& CONSTANT_P (X)) \ && CONSTANT_P (X)) \
? GENERAL_REGS : \ ? GENERAL_REGS : \
(((MODE) == HImode && ! arm_arch4 \ (((MODE) == HImode && ! arm_arch4 \
&& (GET_CODE (X) == MEM \ && (MEM_P (X) \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ || ((REG_P (X) || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \ && true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS) \ ? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
...@@ -1909,10 +1909,10 @@ enum arm_auto_incmodes ...@@ -1909,10 +1909,10 @@ enum arm_auto_incmodes
REG_OK_FOR_INDEX_P (X) REG_OK_FOR_INDEX_P (X)
#define ARM_BASE_REGISTER_RTX_P(X) \ #define ARM_BASE_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
#define ARM_INDEX_REGISTER_RTX_P(X) \ #define ARM_INDEX_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
/* Specify the machine mode that this machine uses /* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */ for the index in the tablejump instruction. */
......
gcc/config/arm/arm.md
...@@ -607,9 +607,9 @@ ...@@ -607,9 +607,9 @@
" "
if (TARGET_THUMB1) if (TARGET_THUMB1)
{ {
if (GET_CODE (operands[1]) != REG) if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]); operands[1] = force_reg (DImode, operands[1]);
if (GET_CODE (operands[2]) != REG) if (!REG_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]); operands[2] = force_reg (DImode, operands[2]);
} }
" "
...@@ -716,7 +716,7 @@ ...@@ -716,7 +716,7 @@
(match_operand:SI 2 "reg_or_int_operand" "")))] (match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
" "
if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) if (TARGET_32BIT && CONST_INT_P (operands[2]))
{ {
arm_split_constant (PLUS, SImode, NULL_RTX, arm_split_constant (PLUS, SImode, NULL_RTX,
INTVAL (operands[2]), operands[0], operands[1], INTVAL (operands[2]), operands[0], operands[1],
...@@ -764,7 +764,7 @@ ...@@ -764,7 +764,7 @@
subw%?\\t%0, %1, #%n2 subw%?\\t%0, %1, #%n2
#" #"
"TARGET_32BIT "TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT && CONST_INT_P (operands[2])
&& !const_ok_for_op (INTVAL (operands[2]), PLUS) && !const_ok_for_op (INTVAL (operands[2]), PLUS)
&& (reload_completed || !arm_eliminable_register (operands[1]))" && (reload_completed || !arm_eliminable_register (operands[1]))"
[(clobber (const_int 0))] [(clobber (const_int 0))]
...@@ -799,7 +799,7 @@ ...@@ -799,7 +799,7 @@
\"#\" \"#\"
}; };
if ((which_alternative == 2 || which_alternative == 6) if ((which_alternative == 2 || which_alternative == 6)
&& GET_CODE (operands[2]) == CONST_INT && CONST_INT_P (operands[2])
&& INTVAL (operands[2]) < 0) && INTVAL (operands[2]) < 0)
return \"sub\\t%0, %1, #%n2\"; return \"sub\\t%0, %1, #%n2\";
return asms[which_alternative]; return asms[which_alternative];
...@@ -1111,9 +1111,9 @@ ...@@ -1111,9 +1111,9 @@
" "
if (TARGET_THUMB1) if (TARGET_THUMB1)
{ {
if (GET_CODE (operands[1]) != REG) if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]); operands[1] = force_reg (DImode, operands[1]);
if (GET_CODE (operands[2]) != REG) if (!REG_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]); operands[2] = force_reg (DImode, operands[2]);
} }
" "
...@@ -1207,7 +1207,7 @@ ...@@ -1207,7 +1207,7 @@
(match_operand:SI 2 "s_register_operand" "")))] (match_operand:SI 2 "s_register_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
" "
if (GET_CODE (operands[1]) == CONST_INT) if (CONST_INT_P (operands[1]))
{ {
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
...@@ -1242,7 +1242,7 @@ ...@@ -1242,7 +1242,7 @@
sub%?\\t%0, %1, %2 sub%?\\t%0, %1, %2
sub%?\\t%0, %1, %2 sub%?\\t%0, %1, %2
#" #"
"&& (GET_CODE (operands[1]) == CONST_INT "&& (CONST_INT_P (operands[1])
&& !const_ok_for_arm (INTVAL (operands[1])))" && !const_ok_for_arm (INTVAL (operands[1])))"
[(clobber (const_int 0))] [(clobber (const_int 0))]
" "
...@@ -2097,7 +2097,7 @@ ...@@ -2097,7 +2097,7 @@
" "
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
{ {
if (INTVAL (operands[2]) == 255 && arm_arch6) if (INTVAL (operands[2]) == 255 && arm_arch6)
{ {
...@@ -2116,7 +2116,7 @@ ...@@ -2116,7 +2116,7 @@
} }
else /* TARGET_THUMB1 */ else /* TARGET_THUMB1 */
{ {
if (GET_CODE (operands[2]) != CONST_INT) if (!CONST_INT_P (operands[2]))
{ {
rtx tmp = force_reg (SImode, operands[2]); rtx tmp = force_reg (SImode, operands[2]);
if (rtx_equal_p (operands[0], operands[1])) if (rtx_equal_p (operands[0], operands[1]))
...@@ -2179,7 +2179,7 @@ ...@@ -2179,7 +2179,7 @@
bic%?\\t%0, %1, #%B2 bic%?\\t%0, %1, #%B2
#" #"
"TARGET_32BIT "TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT && CONST_INT_P (operands[2])
&& !(const_ok_for_arm (INTVAL (operands[2])) && !(const_ok_for_arm (INTVAL (operands[2]))
|| const_ok_for_arm (~INTVAL (operands[2])))" || const_ok_for_arm (~INTVAL (operands[2])))"
[(clobber (const_int 0))] [(clobber (const_int 0))]
...@@ -2512,7 +2512,7 @@ ...@@ -2512,7 +2512,7 @@
{ {
bool use_bfi = TRUE; bool use_bfi = TRUE;
if (GET_CODE (operands[3]) == CONST_INT) if (CONST_INT_P (operands[3]))
{ {
HOST_WIDE_INT val = INTVAL (operands[3]) & mask; HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
...@@ -2530,7 +2530,7 @@ ...@@ -2530,7 +2530,7 @@
if (use_bfi) if (use_bfi)
{ {
if (GET_CODE (operands[3]) != REG) if (!REG_P (operands[3]))
operands[3] = force_reg (SImode, operands[3]); operands[3] = force_reg (SImode, operands[3]);
emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2], emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
...@@ -2558,7 +2558,7 @@ ...@@ -2558,7 +2558,7 @@
else else
subtarget = target; subtarget = target;
if (GET_CODE (operands[3]) == CONST_INT) if (CONST_INT_P (operands[3]))
{ {
/* Since we are inserting a known constant, we may be able to /* Since we are inserting a known constant, we may be able to
reduce the number of bits that we have to clear so that reduce the number of bits that we have to clear so that
...@@ -2625,7 +2625,7 @@ ...@@ -2625,7 +2625,7 @@
/* Mask out any bits in operand[3] that are not needed. */ /* Mask out any bits in operand[3] that are not needed. */
emit_insn (gen_andsi3 (op1, operands[3], op0)); emit_insn (gen_andsi3 (op1, operands[3], op0));
if (GET_CODE (op0) == CONST_INT if (CONST_INT_P (op0)
&& (const_ok_for_arm (mask << start_bit) && (const_ok_for_arm (mask << start_bit)
|| const_ok_for_arm (~(mask << start_bit)))) || const_ok_for_arm (~(mask << start_bit))))
{ {
...@@ -2634,7 +2634,7 @@ ...@@ -2634,7 +2634,7 @@
} }
else else
{ {
if (GET_CODE (op0) == CONST_INT) if (CONST_INT_P (op0))
{ {
rtx tmp = gen_reg_rtx (SImode); rtx tmp = gen_reg_rtx (SImode);
...@@ -2871,7 +2871,7 @@ ...@@ -2871,7 +2871,7 @@
(match_operand:SI 2 "reg_or_int_operand" "")))] (match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
" "
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
{ {
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
...@@ -2905,7 +2905,7 @@ ...@@ -2905,7 +2905,7 @@
orn%?\\t%0, %1, #%B2 orn%?\\t%0, %1, #%B2
#" #"
"TARGET_32BIT "TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT && CONST_INT_P (operands[2])
&& !(const_ok_for_arm (INTVAL (operands[2])) && !(const_ok_for_arm (INTVAL (operands[2]))
|| (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))" || (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))"
[(clobber (const_int 0))] [(clobber (const_int 0))]
...@@ -3010,7 +3010,7 @@ ...@@ -3010,7 +3010,7 @@
(xor:SI (match_operand:SI 1 "s_register_operand" "") (xor:SI (match_operand:SI 1 "s_register_operand" "")
(match_operand:SI 2 "reg_or_int_operand" "")))] (match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
"if (GET_CODE (operands[2]) == CONST_INT) "if (CONST_INT_P (operands[2]))
{ {
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
...@@ -3042,7 +3042,7 @@ ...@@ -3042,7 +3042,7 @@
eor%?\\t%0, %1, %2 eor%?\\t%0, %1, %2
#" #"
"TARGET_32BIT "TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT && CONST_INT_P (operands[2])
&& !const_ok_for_arm (INTVAL (operands[2]))" && !const_ok_for_arm (INTVAL (operands[2]))"
[(clobber (const_int 0))] [(clobber (const_int 0))]
{ {
...@@ -3542,7 +3542,7 @@ ...@@ -3542,7 +3542,7 @@
(match_operand:SI 2 "arm_rhs_operand" "")))] (match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
" "
if (GET_CODE (operands[2]) == CONST_INT if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
{ {
emit_insn (gen_movsi (operands[0], const0_rtx)); emit_insn (gen_movsi (operands[0], const0_rtx));
...@@ -3617,7 +3617,7 @@ ...@@ -3617,7 +3617,7 @@
(match_operand:SI 2 "arm_rhs_operand" "")))] (match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
" "
if (GET_CODE (operands[2]) == CONST_INT if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
operands[2] = GEN_INT (31); operands[2] = GEN_INT (31);
" "
...@@ -3689,7 +3689,7 @@ ...@@ -3689,7 +3689,7 @@
(match_operand:SI 2 "arm_rhs_operand" "")))] (match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
" "
if (GET_CODE (operands[2]) == CONST_INT if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
{ {
emit_insn (gen_movsi (operands[0], const0_rtx)); emit_insn (gen_movsi (operands[0], const0_rtx));
...@@ -3713,7 +3713,7 @@ ...@@ -3713,7 +3713,7 @@
(match_operand:SI 2 "reg_or_int_operand" "")))] (match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_32BIT" "TARGET_32BIT"
" "
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32); operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32);
else else
{ {
...@@ -3732,13 +3732,13 @@ ...@@ -3732,13 +3732,13 @@
" "
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
if (GET_CODE (operands[2]) == CONST_INT if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) % 32); operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
} }
else /* TARGET_THUMB1 */ else /* TARGET_THUMB1 */
{ {
if (GET_CODE (operands [2]) == CONST_INT) if (CONST_INT_P (operands [2]))
operands [2] = force_reg (SImode, operands[2]); operands [2] = force_reg (SImode, operands[2]);
} }
" "
...@@ -4595,7 +4595,7 @@ ...@@ -4595,7 +4595,7 @@
rtx a = XEXP (mem, 0); rtx a = XEXP (mem, 0);
/* This can happen due to bugs in reload. */ /* This can happen due to bugs in reload. */
if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM) if (REG_P (a) && REGNO (a) == SP_REGNUM)
{ {
rtx ops[2]; rtx ops[2];
ops[0] = operands[0]; ops[0] = operands[0];
...@@ -4653,7 +4653,7 @@ ...@@ -4653,7 +4653,7 @@
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
"TARGET_EITHER" "TARGET_EITHER"
{ {
if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM) if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1]))
{ {
emit_insn (gen_andsi3 (operands[0], emit_insn (gen_andsi3 (operands[0],
gen_lowpart (SImode, operands[1]), gen_lowpart (SImode, operands[1]),
...@@ -4746,7 +4746,7 @@ ...@@ -4746,7 +4746,7 @@
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0))) (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
(clobber (match_operand:SI 2 "s_register_operand" ""))] (clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN" "TARGET_32BIT && (!MEM_P (operands[1])) && ! BYTES_BIG_ENDIAN"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))] (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
"" ""
...@@ -4756,7 +4756,7 @@ ...@@ -4756,7 +4756,7 @@
[(set (match_operand:SI 0 "s_register_operand" "") [(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3))) (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3)))
(clobber (match_operand:SI 2 "s_register_operand" ""))] (clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && BYTES_BIG_ENDIAN" "TARGET_32BIT && (!MEM_P (operands[1])) && BYTES_BIG_ENDIAN"
[(set (match_dup 2) (match_dup 1)) [(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))] (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
"" ""
...@@ -4872,10 +4872,10 @@ ...@@ -4872,10 +4872,10 @@
rtx b = XEXP (mem, 1); rtx b = XEXP (mem, 1);
if (GET_CODE (a) == LABEL_REF if (GET_CODE (a) == LABEL_REF
&& GET_CODE (b) == CONST_INT) && CONST_INT_P (b))
return \"ldr\\t%0, %1\"; return \"ldr\\t%0, %1\";
if (GET_CODE (b) == REG) if (REG_P (b))
return \"ldrsh\\t%0, %1\"; return \"ldrsh\\t%0, %1\";
ops[1] = a; ops[1] = a;
...@@ -4887,7 +4887,7 @@ ...@@ -4887,7 +4887,7 @@
ops[2] = const0_rtx; ops[2] = const0_rtx;
} }
gcc_assert (GET_CODE (ops[1]) == REG); gcc_assert (REG_P (ops[1]));
ops[0] = operands[0]; ops[0] = operands[0];
if (reg_mentioned_p (operands[2], ops[1])) if (reg_mentioned_p (operands[2], ops[1]))
...@@ -4998,7 +4998,7 @@ ...@@ -4998,7 +4998,7 @@
"TARGET_ARM" "TARGET_ARM"
" "
{ {
if (arm_arch4 && GET_CODE (operands[1]) == MEM) if (arm_arch4 && MEM_P (operands[1]))
{ {
emit_insn (gen_rtx_SET (VOIDmode, emit_insn (gen_rtx_SET (VOIDmode,
operands[0], operands[0],
...@@ -5235,11 +5235,11 @@ ...@@ -5235,11 +5235,11 @@
;;{ ;;{
;; rtx insn; ;; rtx insn;
;; ;;
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) ;; if (MEM_P (operands[0]) && MEM_P (operands[1]))
;; operands[1] = copy_to_reg (operands[1]); ;; operands[1] = copy_to_reg (operands[1]);
;; if (GET_CODE (operands[0]) == MEM) ;; if (MEM_P (operands[0]))
;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]); ;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]);
;; else if (GET_CODE (operands[1]) == MEM) ;; else if (MEM_P (operands[1]))
;; insn = gen_loadti (operands[0], XEXP (operands[1], 0)); ;; insn = gen_loadti (operands[0], XEXP (operands[1], 0));
;; else ;; else
;; FAIL; ;; FAIL;
...@@ -5280,7 +5280,7 @@ ...@@ -5280,7 +5280,7 @@
" "
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]); operands[1] = force_reg (DImode, operands[1]);
} }
" "
...@@ -5462,10 +5462,10 @@ ...@@ -5462,10 +5462,10 @@
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
/* Everything except mem = const or mem = mem can be done easily. */ /* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
if (arm_general_register_operand (operands[0], SImode) if (arm_general_register_operand (operands[0], SImode)
&& GET_CODE (operands[1]) == CONST_INT && CONST_INT_P (operands[1])
&& !(const_ok_for_arm (INTVAL (operands[1])) && !(const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1])))) || const_ok_for_arm (~INTVAL (operands[1]))))
{ {
...@@ -5479,7 +5479,7 @@ ...@@ -5479,7 +5479,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
} }
} }
...@@ -5886,7 +5886,7 @@ ...@@ -5886,7 +5886,7 @@
rtx addr = XEXP (op1, 0); rtx addr = XEXP (op1, 0);
enum rtx_code code = GET_CODE (addr); enum rtx_code code = GET_CODE (addr);
if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT) if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS) || code == MINUS)
op1 = replace_equiv_address (operands[1], force_reg (SImode, addr)); op1 = replace_equiv_address (operands[1], force_reg (SImode, addr));
...@@ -5911,7 +5911,7 @@ ...@@ -5911,7 +5911,7 @@
rtx addr = XEXP (op1, 0); rtx addr = XEXP (op1, 0);
enum rtx_code code = GET_CODE (addr); enum rtx_code code = GET_CODE (addr);
if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT) if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS) || code == MINUS)
op1 = replace_equiv_address (op1, force_reg (SImode, addr)); op1 = replace_equiv_address (op1, force_reg (SImode, addr));
...@@ -5937,7 +5937,7 @@ ...@@ -5937,7 +5937,7 @@
rtx op0 = operands[0]; rtx op0 = operands[0];
enum rtx_code code = GET_CODE (addr); enum rtx_code code = GET_CODE (addr);
if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT) if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS) || code == MINUS)
op0 = replace_equiv_address (op0, force_reg (SImode, addr)); op0 = replace_equiv_address (op0, force_reg (SImode, addr));
...@@ -5991,18 +5991,18 @@ ...@@ -5991,18 +5991,18 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
{ {
if (arm_arch4) if (arm_arch4)
{ {
emit_insn (gen_storehi_single_op (operands[0], operands[1])); emit_insn (gen_storehi_single_op (operands[0], operands[1]));
DONE; DONE;
} }
if (GET_CODE (operands[1]) == CONST_INT) if (CONST_INT_P (operands[1]))
emit_insn (gen_storeinthi (operands[0], operands[1])); emit_insn (gen_storeinthi (operands[0], operands[1]));
else else
{ {
if (GET_CODE (operands[1]) == MEM) if (MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
if (BYTES_BIG_ENDIAN) if (BYTES_BIG_ENDIAN)
emit_insn (gen_storehi_bigend (operands[1], operands[0])); emit_insn (gen_storehi_bigend (operands[1], operands[0]));
...@@ -6012,7 +6012,7 @@ ...@@ -6012,7 +6012,7 @@
DONE; DONE;
} }
/* Sign extend a constant, and keep it in an SImode reg. */ /* Sign extend a constant, and keep it in an SImode reg. */
else if (GET_CODE (operands[1]) == CONST_INT) else if (CONST_INT_P (operands[1]))
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff; HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
...@@ -6034,7 +6034,7 @@ ...@@ -6034,7 +6034,7 @@
operands[1] = gen_lowpart (HImode, reg); operands[1] = gen_lowpart (HImode, reg);
} }
else if (arm_arch4 && optimize && can_create_pseudo_p () else if (arm_arch4 && optimize && can_create_pseudo_p ()
&& GET_CODE (operands[1]) == MEM) && MEM_P (operands[1]))
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
...@@ -6043,18 +6043,17 @@ ...@@ -6043,18 +6043,17 @@
} }
else if (!arm_arch4) else if (!arm_arch4)
{ {
if (GET_CODE (operands[1]) == MEM) if (MEM_P (operands[1]))
{ {
rtx base; rtx base;
rtx offset = const0_rtx; rtx offset = const0_rtx;
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
if ((GET_CODE (base = XEXP (operands[1], 0)) == REG if ((REG_P (base = XEXP (operands[1], 0))
|| (GET_CODE (base) == PLUS || (GET_CODE (base) == PLUS
&& (GET_CODE (offset = XEXP (base, 1)) && (CONST_INT_P (offset = XEXP (base, 1)))
== CONST_INT)
&& ((INTVAL(offset) & 1) != 1) && ((INTVAL(offset) & 1) != 1)
&& GET_CODE (base = XEXP (base, 0)) == REG)) && REG_P (base = XEXP (base, 0))))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 32) && REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{ {
rtx new_rtx; rtx new_rtx;
...@@ -6080,13 +6079,13 @@ ...@@ -6080,13 +6079,13 @@
} }
} }
/* Handle loading a large integer during reload. */ /* Handle loading a large integer during reload. */
else if (GET_CODE (operands[1]) == CONST_INT else if (CONST_INT_P (operands[1])
&& !const_ok_for_arm (INTVAL (operands[1])) && !const_ok_for_arm (INTVAL (operands[1]))
&& !const_ok_for_arm (~INTVAL (operands[1]))) && !const_ok_for_arm (~INTVAL (operands[1])))
{ {
/* Writing a constant to memory needs a scratch, which should /* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */ be handled with SECONDARY_RELOADs. */
gcc_assert (GET_CODE (operands[0]) == REG); gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1])); emit_insn (gen_movsi (operands[0], operands[1]));
...@@ -6098,10 +6097,10 @@ ...@@ -6098,10 +6097,10 @@
/* Thumb-2 can do everything except mem=mem and mem=const easily. */ /* Thumb-2 can do everything except mem=mem and mem=const easily. */
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
/* Zero extend a constant, and keep it in an SImode reg. */ /* Zero extend a constant, and keep it in an SImode reg. */
else if (GET_CODE (operands[1]) == CONST_INT) else if (CONST_INT_P (operands[1]))
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff; HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
...@@ -6115,7 +6114,7 @@ ...@@ -6115,7 +6114,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[1]) == CONST_INT) if (CONST_INT_P (operands[1]))
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
...@@ -6131,21 +6130,21 @@ ...@@ -6131,21 +6130,21 @@
fixup_stack_1, by checking for other kinds of invalid addresses, fixup_stack_1, by checking for other kinds of invalid addresses,
e.g. a bare reference to a virtual register. This may confuse the e.g. a bare reference to a virtual register. This may confuse the
alpha though, which must handle this case differently. */ alpha though, which must handle this case differently. */
if (GET_CODE (operands[0]) == MEM if (MEM_P (operands[0])
&& !memory_address_p (GET_MODE (operands[0]), && !memory_address_p (GET_MODE (operands[0]),
XEXP (operands[0], 0))) XEXP (operands[0], 0)))
operands[0] operands[0]
= replace_equiv_address (operands[0], = replace_equiv_address (operands[0],
copy_to_reg (XEXP (operands[0], 0))); copy_to_reg (XEXP (operands[0], 0)));
if (GET_CODE (operands[1]) == MEM if (MEM_P (operands[1])
&& !memory_address_p (GET_MODE (operands[1]), && !memory_address_p (GET_MODE (operands[1]),
XEXP (operands[1], 0))) XEXP (operands[1], 0)))
operands[1] operands[1]
= replace_equiv_address (operands[1], = replace_equiv_address (operands[1],
copy_to_reg (XEXP (operands[1], 0))); copy_to_reg (XEXP (operands[1], 0)));
if (GET_CODE (operands[1]) == MEM && optimize > 0) if (MEM_P (operands[1]) && optimize > 0)
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
...@@ -6153,17 +6152,17 @@ ...@@ -6153,17 +6152,17 @@
operands[1] = gen_lowpart (HImode, reg); operands[1] = gen_lowpart (HImode, reg);
} }
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]); operands[1] = force_reg (HImode, operands[1]);
} }
else if (GET_CODE (operands[1]) == CONST_INT else if (CONST_INT_P (operands[1])
&& !satisfies_constraint_I (operands[1])) && !satisfies_constraint_I (operands[1]))
{ {
/* Handle loading a large integer during reload. */ /* Handle loading a large integer during reload. */
/* Writing a constant to memory needs a scratch, which should /* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */ be handled with SECONDARY_RELOADs. */
gcc_assert (GET_CODE (operands[0]) == REG); gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1])); emit_insn (gen_movsi (operands[0], operands[1]));
...@@ -6192,7 +6191,7 @@ ...@@ -6192,7 +6191,7 @@
/* The stack pointer can end up being taken as an index register. /* The stack pointer can end up being taken as an index register.
Catch this case here and deal with it. */ Catch this case here and deal with it. */
if (GET_CODE (XEXP (operands[1], 0)) == PLUS if (GET_CODE (XEXP (operands[1], 0)) == PLUS
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG && REG_P (XEXP (XEXP (operands[1], 0), 0))
&& REGNO (XEXP (XEXP (operands[1], 0), 0)) == SP_REGNUM) && REGNO (XEXP (XEXP (operands[1], 0), 0)) == SP_REGNUM)
{ {
rtx ops[2]; rtx ops[2];
...@@ -6347,7 +6346,7 @@ ...@@ -6347,7 +6346,7 @@
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[1]) == CONST_INT) if (CONST_INT_P (operands[1]))
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
...@@ -6370,13 +6369,13 @@ ...@@ -6370,13 +6369,13 @@
fixup_stack_1, by checking for other kinds of invalid addresses, fixup_stack_1, by checking for other kinds of invalid addresses,
e.g. a bare reference to a virtual register. This may confuse the e.g. a bare reference to a virtual register. This may confuse the
alpha though, which must handle this case differently. */ alpha though, which must handle this case differently. */
if (GET_CODE (operands[0]) == MEM if (MEM_P (operands[0])
&& !memory_address_p (GET_MODE (operands[0]), && !memory_address_p (GET_MODE (operands[0]),
XEXP (operands[0], 0))) XEXP (operands[0], 0)))
operands[0] operands[0]
= replace_equiv_address (operands[0], = replace_equiv_address (operands[0],
copy_to_reg (XEXP (operands[0], 0))); copy_to_reg (XEXP (operands[0], 0)));
if (GET_CODE (operands[1]) == MEM if (MEM_P (operands[1])
&& !memory_address_p (GET_MODE (operands[1]), && !memory_address_p (GET_MODE (operands[1]),
XEXP (operands[1], 0))) XEXP (operands[1], 0)))
operands[1] operands[1]
...@@ -6384,7 +6383,7 @@ ...@@ -6384,7 +6383,7 @@
copy_to_reg (XEXP (operands[1], 0))); copy_to_reg (XEXP (operands[1], 0)));
} }
if (GET_CODE (operands[1]) == MEM && optimize > 0) if (MEM_P (operands[1]) && optimize > 0)
{ {
rtx reg = gen_reg_rtx (SImode); rtx reg = gen_reg_rtx (SImode);
...@@ -6392,18 +6391,18 @@ ...@@ -6392,18 +6391,18 @@
operands[1] = gen_lowpart (QImode, reg); operands[1] = gen_lowpart (QImode, reg);
} }
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]); operands[1] = force_reg (QImode, operands[1]);
} }
else if (TARGET_THUMB else if (TARGET_THUMB
&& GET_CODE (operands[1]) == CONST_INT && CONST_INT_P (operands[1])
&& !satisfies_constraint_I (operands[1])) && !satisfies_constraint_I (operands[1]))
{ {
/* Handle loading a large integer during reload. */ /* Handle loading a large integer during reload. */
/* Writing a constant to memory needs a scratch, which should /* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */ be handled with SECONDARY_RELOADs. */
gcc_assert (GET_CODE (operands[0]) == REG); gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0); operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1])); emit_insn (gen_movsi (operands[0], operands[1]));
...@@ -6460,14 +6459,14 @@ ...@@ -6460,14 +6459,14 @@
" "
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (HFmode, operands[1]); operands[1] = force_reg (HFmode, operands[1]);
} }
else /* TARGET_THUMB1 */ else /* TARGET_THUMB1 */
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (HFmode, operands[1]); operands[1] = force_reg (HFmode, operands[1]);
} }
} }
...@@ -6531,13 +6530,13 @@ ...@@ -6531,13 +6530,13 @@
case 1: case 1:
{ {
rtx addr; rtx addr;
gcc_assert (GET_CODE(operands[1]) == MEM); gcc_assert (MEM_P (operands[1]));
addr = XEXP (operands[1], 0); addr = XEXP (operands[1], 0);
if (GET_CODE (addr) == LABEL_REF if (GET_CODE (addr) == LABEL_REF
|| (GET_CODE (addr) == CONST || (GET_CODE (addr) == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS && GET_CODE (XEXP (addr, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF && GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)) && CONST_INT_P (XEXP (XEXP (addr, 0), 1))))
{ {
/* Constant pool entry. */ /* Constant pool entry. */
return \"ldr\\t%0, %1\"; return \"ldr\\t%0, %1\";
...@@ -6561,14 +6560,14 @@ ...@@ -6561,14 +6560,14 @@
" "
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]); operands[1] = force_reg (SFmode, operands[1]);
} }
else /* TARGET_THUMB1 */ else /* TARGET_THUMB1 */
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]); operands[1] = force_reg (SFmode, operands[1]);
} }
} }
...@@ -6582,7 +6581,7 @@ ...@@ -6582,7 +6581,7 @@
(match_operand:SF 1 "immediate_operand" ""))] (match_operand:SF 1 "immediate_operand" ""))]
"TARGET_EITHER "TARGET_EITHER
&& reload_completed && reload_completed
&& GET_CODE (operands[1]) == CONST_DOUBLE" && CONST_DOUBLE_P (operands[1])"
[(set (match_dup 2) (match_dup 3))] [(set (match_dup 2) (match_dup 3))]
" "
operands[2] = gen_lowpart (SImode, operands[0]); operands[2] = gen_lowpart (SImode, operands[0]);
...@@ -6597,7 +6596,7 @@ ...@@ -6597,7 +6596,7 @@
(match_operand:SF 1 "general_operand" "r,mE,r"))] (match_operand:SF 1 "general_operand" "r,mE,r"))]
"TARGET_32BIT "TARGET_32BIT
&& TARGET_SOFT_FLOAT && TARGET_SOFT_FLOAT
&& (GET_CODE (operands[0]) != MEM && (!MEM_P (operands[0])
|| register_operand (operands[1], SFmode))" || register_operand (operands[1], SFmode))"
"@ "@
mov%?\\t%0, %1 mov%?\\t%0, %1
...@@ -6640,14 +6639,14 @@ ...@@ -6640,14 +6639,14 @@
" "
if (TARGET_32BIT) if (TARGET_32BIT)
{ {
if (GET_CODE (operands[0]) == MEM) if (MEM_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]); operands[1] = force_reg (DFmode, operands[1]);
} }
else /* TARGET_THUMB */ else /* TARGET_THUMB */
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]); operands[1] = force_reg (DFmode, operands[1]);
} }
} }
...@@ -6778,11 +6777,11 @@ ...@@ -6778,11 +6777,11 @@
HOST_WIDE_INT offset = 0; HOST_WIDE_INT offset = 0;
/* Support only fixed point registers. */ /* Support only fixed point registers. */
if (GET_CODE (operands[2]) != CONST_INT if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > 14 || INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2 || INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != MEM || !MEM_P (operands[1])
|| GET_CODE (operands[0]) != REG || !REG_P (operands[0])
|| REGNO (operands[0]) > (LAST_ARM_REGNUM - 1) || REGNO (operands[0]) > (LAST_ARM_REGNUM - 1)
|| REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM) || REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL; FAIL;
...@@ -6803,11 +6802,11 @@ ...@@ -6803,11 +6802,11 @@
HOST_WIDE_INT offset = 0; HOST_WIDE_INT offset = 0;
/* Support only fixed point registers. */ /* Support only fixed point registers. */
if (GET_CODE (operands[2]) != CONST_INT if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > 14 || INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2 || INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != REG || !REG_P (operands[1])
|| GET_CODE (operands[0]) != MEM || !MEM_P (operands[0])
|| REGNO (operands[1]) > (LAST_ARM_REGNUM - 1) || REGNO (operands[1]) > (LAST_ARM_REGNUM - 1)
|| REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM) || REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL; FAIL;
...@@ -7430,7 +7429,7 @@ ...@@ -7430,7 +7429,7 @@
cond[1] = operands[2]; cond[1] = operands[2];
cond[2] = operands[3]; cond[2] = operands[3];
if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0) if (CONST_INT_P (cond[2]) && INTVAL (cond[2]) < 0)
output_asm_insn (\"sub\\t%0, %1, #%n2\", cond); output_asm_insn (\"sub\\t%0, %1, #%n2\", cond);
else else
output_asm_insn (\"add\\t%0, %1, %2\", cond); output_asm_insn (\"add\\t%0, %1, %2\", cond);
...@@ -9849,13 +9848,13 @@ ...@@ -9849,13 +9848,13 @@
if (GET_CODE (operands[5]) == LT if (GET_CODE (operands[5]) == LT
&& (operands[4] == const0_rtx)) && (operands[4] == const0_rtx))
{ {
if (which_alternative != 1 && GET_CODE (operands[1]) == REG) if (which_alternative != 1 && REG_P (operands[1]))
{ {
if (operands[2] == const0_rtx) if (operands[2] == const0_rtx)
return \"and\\t%0, %1, %3, asr #31\"; return \"and\\t%0, %1, %3, asr #31\";
return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\"; return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\";
} }
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) else if (which_alternative != 0 && REG_P (operands[2]))
{ {
if (operands[1] == const0_rtx) if (operands[1] == const0_rtx)
return \"bic\\t%0, %2, %3, asr #31\"; return \"bic\\t%0, %2, %3, asr #31\";
...@@ -9868,13 +9867,13 @@ ...@@ -9868,13 +9867,13 @@
if (GET_CODE (operands[5]) == GE if (GET_CODE (operands[5]) == GE
&& (operands[4] == const0_rtx)) && (operands[4] == const0_rtx))
{ {
if (which_alternative != 1 && GET_CODE (operands[1]) == REG) if (which_alternative != 1 && REG_P (operands[1]))
{ {
if (operands[2] == const0_rtx) if (operands[2] == const0_rtx)
return \"bic\\t%0, %1, %3, asr #31\"; return \"bic\\t%0, %1, %3, asr #31\";
return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\"; return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\";
} }
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) else if (which_alternative != 0 && REG_P (operands[2]))
{ {
if (operands[1] == const0_rtx) if (operands[1] == const0_rtx)
return \"and\\t%0, %2, %3, asr #31\"; return \"and\\t%0, %2, %3, asr #31\";
...@@ -9883,7 +9882,7 @@ ...@@ -9883,7 +9882,7 @@
/* The only case that falls through to here is when both ops 1 & 2 /* The only case that falls through to here is when both ops 1 & 2
are constants. */ are constants. */
} }
if (GET_CODE (operands[4]) == CONST_INT if (CONST_INT_P (operands[4])
&& !const_ok_for_arm (INTVAL (operands[4]))) && !const_ok_for_arm (INTVAL (operands[4])))
output_asm_insn (\"cmn\\t%3, #%n4\", operands); output_asm_insn (\"cmn\\t%3, #%n4\", operands);
else else
...@@ -10023,8 +10022,8 @@ ...@@ -10023,8 +10022,8 @@
everything is in registers then we can do this in two instructions. */ everything is in registers then we can do this in two instructions. */
if (operands[3] == const0_rtx if (operands[3] == const0_rtx
&& GET_CODE (operands[7]) != AND && GET_CODE (operands[7]) != AND
&& GET_CODE (operands[5]) == REG && REG_P (operands[5])
&& GET_CODE (operands[1]) == REG && REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[4]) && REGNO (operands[1]) == REGNO (operands[4])
&& REGNO (operands[4]) != REGNO (operands[0])) && REGNO (operands[4]) != REGNO (operands[0]))
{ {
...@@ -10033,7 +10032,7 @@ ...@@ -10033,7 +10032,7 @@
else if (GET_CODE (operands[6]) == GE) else if (GET_CODE (operands[6]) == GE)
return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\";
} }
if (GET_CODE (operands[3]) == CONST_INT if (CONST_INT_P (operands[3])
&& !const_ok_for_arm (INTVAL (operands[3]))) && !const_ok_for_arm (INTVAL (operands[3])))
output_asm_insn (\"cmn\\t%2, #%n3\", operands); output_asm_insn (\"cmn\\t%2, #%n3\", operands);
else else
...@@ -10081,8 +10080,8 @@ ...@@ -10081,8 +10080,8 @@
everything is in registers then we can do this in two instructions */ everything is in registers then we can do this in two instructions */
if (operands[5] == const0_rtx if (operands[5] == const0_rtx
&& GET_CODE (operands[7]) != AND && GET_CODE (operands[7]) != AND
&& GET_CODE (operands[3]) == REG && REG_P (operands[3])
&& GET_CODE (operands[1]) == REG && REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[2]) && REGNO (operands[1]) == REGNO (operands[2])
&& REGNO (operands[2]) != REGNO (operands[0])) && REGNO (operands[2]) != REGNO (operands[0]))
{ {
...@@ -10092,7 +10091,7 @@ ...@@ -10092,7 +10091,7 @@
return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\";
} }
if (GET_CODE (operands[5]) == CONST_INT if (CONST_INT_P (operands[5])
&& !const_ok_for_arm (INTVAL (operands[5]))) && !const_ok_for_arm (INTVAL (operands[5])))
output_asm_insn (\"cmn\\t%4, #%n5\", operands); output_asm_insn (\"cmn\\t%4, #%n5\", operands);
else else
...@@ -10677,7 +10676,7 @@ ...@@ -10677,7 +10676,7 @@
" "
{ {
cfun->machine->eh_epilogue_sp_ofs = operands[1]; cfun->machine->eh_epilogue_sp_ofs = operands[1];
if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 2) if (!REG_P (operands[2]) || REGNO (operands[2]) != 2)
{ {
rtx ra = gen_rtx_REG (Pmode, 2); rtx ra = gen_rtx_REG (Pmode, 2);
......
gcc/config/arm/neon.md
...@@ -255,7 +255,7 @@ ...@@ -255,7 +255,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (TImode, operands[1]); operands[1] = force_reg (TImode, operands[1]);
} }
}) })
...@@ -267,7 +267,7 @@ ...@@ -267,7 +267,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]); operands[1] = force_reg (<MODE>mode, operands[1]);
} }
}) })
......
gcc/config/arm/predicates.md
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
/* We don't consider registers whose class is NO_REGS /* We don't consider registers whose class is NO_REGS
to be a register operand. */ to be a register operand. */
/* XXX might have to check for lo regs only for thumb ??? */ /* XXX might have to check for lo regs only for thumb ??? */
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER && (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
}) })
...@@ -55,7 +55,7 @@ ...@@ -55,7 +55,7 @@
if (GET_CODE (op) == SUBREG) if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op); op = SUBREG_REG (op);
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) <= LAST_ARM_REGNUM && (REGNO (op) <= LAST_ARM_REGNUM
|| REGNO (op) >= FIRST_PSEUDO_REGISTER)); || REGNO (op) >= FIRST_PSEUDO_REGISTER));
}) })
...@@ -68,7 +68,7 @@ ...@@ -68,7 +68,7 @@
/* We don't consider registers whose class is NO_REGS /* We don't consider registers whose class is NO_REGS
to be a register operand. */ to be a register operand. */
return (GET_CODE (op) == REG return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER && (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
|| REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
...@@ -178,7 +178,7 @@ ...@@ -178,7 +178,7 @@
(and (match_code "mem,reg,subreg") (and (match_code "mem,reg,subreg")
(match_test "(!CONSTANT_P (op) (match_test "(!CONSTANT_P (op)
&& (true_regnum(op) == -1 && (true_regnum(op) == -1
|| (GET_CODE (op) == REG || (REG_P (op)
&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))"))) && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
(define_predicate "vfp_compare_operand" (define_predicate "vfp_compare_operand"
...@@ -195,7 +195,7 @@ ...@@ -195,7 +195,7 @@
(define_predicate "index_operand" (define_predicate "index_operand"
(ior (match_operand 0 "s_register_operand") (ior (match_operand 0 "s_register_operand")
(and (match_operand 0 "immediate_operand") (and (match_operand 0 "immediate_operand")
(match_test "(GET_CODE (op) != CONST_INT (match_test "(!CONST_INT_P (op)
|| (INTVAL (op) < 4096 && INTVAL (op) > -4096))")))) || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
;; True for operators that can be combined with a shift in ARM state. ;; True for operators that can be combined with a shift in ARM state.
...@@ -223,10 +223,10 @@ ...@@ -223,10 +223,10 @@
(and (ior (ior (and (match_code "mult") (and (ior (ior (and (match_code "mult")
(match_test "power_of_two_operand (XEXP (op, 1), mode)")) (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "rotate") (and (match_code "rotate")
(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT (match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
(and (match_code "ashift,ashiftrt,lshiftrt,rotatert") (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
(match_test "GET_CODE (XEXP (op, 1)) != CONST_INT (match_test "!CONST_INT_P (XEXP (op, 1))
|| ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))) || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
(match_test "mode == GET_MODE (op)"))) (match_test "mode == GET_MODE (op)")))
...@@ -235,7 +235,7 @@ ...@@ -235,7 +235,7 @@
(and (ior (and (match_code "mult") (and (ior (and (match_code "mult")
(match_test "power_of_two_operand (XEXP (op, 1), mode)")) (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "ashift,ashiftrt") (and (match_code "ashift,ashiftrt")
(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT (match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)"))) && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
(match_test "mode == GET_MODE (op)"))) (match_test "mode == GET_MODE (op)")))
...@@ -332,7 +332,7 @@ ...@@ -332,7 +332,7 @@
if (GET_CODE (op) == SUBREG) if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op); op = SUBREG_REG (op);
return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0)); return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
}) })
(define_predicate "di_operand" (define_predicate "di_operand"
...@@ -349,7 +349,7 @@ ...@@ -349,7 +349,7 @@
if (GET_CODE (op) == SUBREG) if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op); op = SUBREG_REG (op);
return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0)); return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
}) })
(define_predicate "soft_df_operand" (define_predicate "soft_df_operand"
...@@ -559,7 +559,7 @@ ...@@ -559,7 +559,7 @@
rtx elt = XVECEXP (op, 0, i); rtx elt = XVECEXP (op, 0, i);
int val; int val;
if (GET_CODE (elt) != CONST_INT) if (!CONST_INT_P (elt))
return false; return false;
val = INTVAL (elt); val = INTVAL (elt);
...@@ -588,7 +588,7 @@ ...@@ -588,7 +588,7 @@
rtx elt = XVECEXP (op, 0, i); rtx elt = XVECEXP (op, 0, i);
int val; int val;
if (GET_CODE (elt) != CONST_INT) if (!CONST_INT_P (elt))
return false; return false;
val = INTVAL (elt); val = INTVAL (elt);
......
gcc/config/arm/thumb2.md
...@@ -494,13 +494,13 @@ ...@@ -494,13 +494,13 @@
if (GET_CODE (operands[5]) == LT if (GET_CODE (operands[5]) == LT
&& (operands[4] == const0_rtx)) && (operands[4] == const0_rtx))
{ {
if (which_alternative != 1 && GET_CODE (operands[1]) == REG) if (which_alternative != 1 && REG_P (operands[1]))
{ {
if (operands[2] == const0_rtx) if (operands[2] == const0_rtx)
return \"and\\t%0, %1, %3, asr #31\"; return \"and\\t%0, %1, %3, asr #31\";
return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\"; return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
} }
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) else if (which_alternative != 0 && REG_P (operands[2]))
{ {
if (operands[1] == const0_rtx) if (operands[1] == const0_rtx)
return \"bic\\t%0, %2, %3, asr #31\"; return \"bic\\t%0, %2, %3, asr #31\";
...@@ -513,13 +513,13 @@ ...@@ -513,13 +513,13 @@
if (GET_CODE (operands[5]) == GE if (GET_CODE (operands[5]) == GE
&& (operands[4] == const0_rtx)) && (operands[4] == const0_rtx))
{ {
if (which_alternative != 1 && GET_CODE (operands[1]) == REG) if (which_alternative != 1 && REG_P (operands[1]))
{ {
if (operands[2] == const0_rtx) if (operands[2] == const0_rtx)
return \"bic\\t%0, %1, %3, asr #31\"; return \"bic\\t%0, %1, %3, asr #31\";
return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\"; return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
} }
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) else if (which_alternative != 0 && REG_P (operands[2]))
{ {
if (operands[1] == const0_rtx) if (operands[1] == const0_rtx)
return \"and\\t%0, %2, %3, asr #31\"; return \"and\\t%0, %2, %3, asr #31\";
...@@ -528,7 +528,7 @@ ...@@ -528,7 +528,7 @@
/* The only case that falls through to here is when both ops 1 & 2 /* The only case that falls through to here is when both ops 1 & 2
are constants. */ are constants. */
} }
if (GET_CODE (operands[4]) == CONST_INT if (CONST_INT_P (operands[4])
&& !const_ok_for_arm (INTVAL (operands[4]))) && !const_ok_for_arm (INTVAL (operands[4])))
output_asm_insn (\"cmn\\t%3, #%n4\", operands); output_asm_insn (\"cmn\\t%3, #%n4\", operands);
else else
...@@ -680,7 +680,7 @@ ...@@ -680,7 +680,7 @@
(clobber (reg:CC CC_REGNUM))] (clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed "TARGET_THUMB2 && reload_completed
&& ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT) && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
|| REG_P(operands[2]))" || REG_P (operands[2]))"
"* return arm_output_shift(operands, 2);" "* return arm_output_shift(operands, 2);"
[(set_attr "predicable" "yes") [(set_attr "predicable" "yes")
(set_attr "shift" "1") (set_attr "shift" "1")
...@@ -709,7 +709,7 @@ ...@@ -709,7 +709,7 @@
"* "*
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
val = INTVAL(operands[2]); val = INTVAL(operands[2]);
else else
val = 0; val = 0;
...@@ -773,7 +773,7 @@ ...@@ -773,7 +773,7 @@
"* "*
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE (operands[2]) == CONST_INT) if (CONST_INT_P (operands[2]))
val = INTVAL (operands[2]); val = INTVAL (operands[2]);
else else
val = 0; val = 0;
...@@ -797,7 +797,7 @@ ...@@ -797,7 +797,7 @@
"* "*
HOST_WIDE_INT val; HOST_WIDE_INT val;
if (GET_CODE (operands[1]) == CONST_INT) if (CONST_INT_P (operands[1]))
val = INTVAL (operands[1]); val = INTVAL (operands[1]);
else else
val = 0; val = 0;
......
gcc/config/arm/vec-common.md
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
{ {
if (can_create_pseudo_p ()) if (can_create_pseudo_p ())
{ {
if (GET_CODE (operands[0]) != REG) if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]); operands[1] = force_reg (<MODE>mode, operands[1]);
else if (TARGET_NEON && CONSTANT_P (operands[1])) else if (TARGET_NEON && CONSTANT_P (operands[1]))
{ {
......
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