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riscv-gcc-1
Commit d40c829f by Ulrich Weigand Committed by Ulrich Weigand
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* config/s390/s390.md: Replace all occurrences of \\t with \t. 

From-SVN: r70221
parent a5342656
Showing with 668 additions and 664 deletions
gcc/ChangeLog
2003-08-07 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.md: Replace all occurrences of \\t with \t.
2003-08-07 Richard Sandiford <rsandifo@redhat.com>
* local-alloc.c (combine_regs): Fix comment typo.
......
gcc/config/s390/s390.md
......@@ -373,10 +373,10 @@
switch (part)
{
case 0: return "tmhh\\t%0,%x2";
case 1: return "tmhl\\t%0,%x2";
case 2: return "tmlh\\t%0,%x2";
case 3: return "tmll\\t%0,%x2";
case 0: return "tmhh\t%0,%x2";
case 1: return "tmhl\t%0,%x2";
case 2: return "tmlh\t%0,%x2";
case 3: return "tmll\t%0,%x2";
default: abort ();
}
}
......@@ -402,8 +402,8 @@
switch (part)
{
case 0: return "tmh\\t%0,%x2";
case 1: return "tml\\t%0,%x2";
case 0: return "tmh\t%0,%x2";
case 1: return "tml\t%0,%x2";
default: abort ();
}
}
......@@ -423,7 +423,7 @@
int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
operands[2] = GEN_INT (block << shift);
return which_alternative == 0 ? "tm\\t%0,%b2" : "tmy\\t%0,%b2";
return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2";
}
[(set_attr "op_type" "SI,SIY")])
......@@ -443,7 +443,7 @@
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? "tm\\t%0,%b1" : "tmy\\t%0,%b1";
return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
}
[(set_attr "op_type" "SI,SIY")])
......@@ -460,7 +460,7 @@
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? "tm\\t%0,%b1" : "tmy\\t%0,%b1";
return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
}
[(set_attr "op_type" "SI")])
......@@ -477,7 +477,7 @@
operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? "tm\\t%0,%b1" : "tmy\\t%0,%b1";
return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
}
[(set_attr "op_type" "SI")])
......@@ -488,8 +488,8 @@
(match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"@
tm\\t%0,%b1
tmy\\t%0,%b1"
tm\t%0,%b1
tmy\t%0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg"
......@@ -506,10 +506,10 @@
switch (part)
{
case 0: return "tmhh\\t%0,%x1";
case 1: return "tmhl\\t%0,%x1";
case 2: return "tmlh\\t%0,%x1";
case 3: return "tmll\\t%0,%x1";
case 0: return "tmhh\t%0,%x1";
case 1: return "tmhl\t%0,%x1";
case 2: return "tmlh\t%0,%x1";
case 3: return "tmll\t%0,%x1";
default: abort ();
}
}
......@@ -528,8 +528,8 @@
switch (part)
{
case 0: return "tmh\\t%0,%x1";
case 1: return "tml\\t%0,%x1";
case 0: return "tmh\t%0,%x1";
case 1: return "tml\t%0,%x1";
default: abort ();
}
}
......@@ -540,7 +540,7 @@
(compare (match_operand:HI 0 "register_operand" "d")
(match_operand:HI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
"tml\\t%0,65535"
"tml\t%0,65535"
[(set_attr "op_type" "RX")])
(define_insn "*tmqi_full"
......@@ -548,7 +548,7 @@
(compare (match_operand:QI 0 "register_operand" "d")
(match_operand:QI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
"tml\\t%0,255"
"tml\t%0,255"
[(set_attr "op_type" "RI")])
......@@ -562,7 +562,7 @@
(set (match_operand:DI 2 "register_operand" "=d")
(sign_extend:DI (match_dup 0)))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"ltgfr\\t%2,%0"
"ltgfr\t%2,%0"
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi"
......@@ -572,7 +572,7 @@
(set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"ltgr\\t%2,%0"
"ltgr\t%2,%0"
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi_cconly"
......@@ -580,7 +580,7 @@
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"ltgr\\t%0,%0"
"ltgr\t%0,%0"
[(set_attr "op_type" "RRE")])
(define_insn "*tstdi_cconly_31"
......@@ -588,7 +588,7 @@
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
"srda\\t%0,0"
"srda\t%0,0"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -601,9 +601,9 @@
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%2,%0
icm\\t%2,15,%0
icmy\\t%2,15,%0"
ltr\t%2,%0
icm\t%2,15,%0
icmy\t%2,15,%0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly"
......@@ -613,9 +613,9 @@
(clobber (match_scratch:SI 2 "=X,d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
ltr\\t%0,%0
icm\\t%2,15,%0
icmy\\t%2,15,%0"
ltr\t%0,%0
icm\t%2,15,%0
icmy\t%2,15,%0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2"
......@@ -623,7 +623,7 @@
(compare (match_operand:SI 0 "register_operand" "d")
(match_operand:SI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode)"
"ltr\\t%0,%0"
"ltr\t%0,%0"
[(set_attr "op_type" "RR")])
(define_insn "*tsthiCCT"
......@@ -634,9 +634,9 @@
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
icmy\\t%2,3,%0
tml\\t%0,65535"
icm\t%2,3,%0
icmy\t%2,3,%0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthiCCT_cconly"
......@@ -646,9 +646,9 @@
(clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,3,%0
icmy\\t%2,3,%0
tml\\t%0,65535"
icm\t%2,3,%0
icmy\t%2,3,%0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthi"
......@@ -659,8 +659,8 @@
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
icm\\t%2,3,%0
icmy\\t%2,3,%0"
icm\t%2,3,%0
icmy\t%2,3,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tsthi_cconly"
......@@ -670,8 +670,8 @@
(clobber (match_scratch:HI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
icm\\t%2,3,%0
icmy\\t%2,3,%0"
icm\t%2,3,%0
icmy\t%2,3,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqiCCT"
......@@ -682,9 +682,9 @@
(match_dup 0))]
"s390_match_ccmode(insn, CCTmode)"
"@
icm\\t%2,1,%0
icmy\\t%2,1,%0
tml\\t%0,255"
icm\t%2,1,%0
icmy\t%2,1,%0
tml\t%0,255"
[(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tstqiCCT_cconly"
......@@ -693,9 +693,9 @@
(match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)"
"@
cli\\t%0,0
cliy\\t%0,0
tml\\t%0,255"
cli\t%0,0
cliy\t%0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")])
(define_insn "*tstqi"
......@@ -706,8 +706,8 @@
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"@
icm\\t%2,1,%0
icmy\\t%2,1,%0"
icm\t%2,1,%0
icmy\t%2,1,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqi_cconly"
......@@ -717,8 +717,8 @@
(clobber (match_scratch:QI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
icm\\t%2,1,%0
icmy\\t%2,1,%0"
icm\t%2,1,%0
icmy\t%2,1,%0"
[(set_attr "op_type" "RS,RSY")])
......@@ -730,8 +730,8 @@
(match_operand:DI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
cgfr\t%0,%1
cgf\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs"
......@@ -740,9 +740,9 @@
(match_operand:DI 1 "general_operand" "d,K,m")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"@
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
cgr\t%0,%1
cghi\t%0,%c1
cg\t%0,%1"
[(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign"
......@@ -751,8 +751,8 @@
(match_operand:SI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode)"
"@
ch\\t%0,%1
chy\\t%0,%1"
ch\t%0,%1
chy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs"
......@@ -761,10 +761,10 @@
(match_operand:SI 1 "general_operand" "d,K,R,T")))]
"s390_match_ccmode(insn, CCSmode)"
"@
cr\\t%0,%1
chi\\t%0,%c1
c\\t%0,%1
cy\\t%0,%1"
cr\t%0,%1
chi\t%0,%c1
c\t%0,%1
cy\t%0,%1"
[(set_attr "op_type" "RR,RI,RX,RXY")])
......@@ -776,8 +776,8 @@
(match_operand:DI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
clgfr\t%0,%1
clgf\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccu"
......@@ -786,8 +786,8 @@
(match_operand:DI 1 "general_operand" "d,m")))]
"s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
"@
clgr\\t%0,%1
clg\\t%0,%1"
clgr\t%0,%1
clg\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpsi_ccu"
......@@ -796,9 +796,9 @@
(match_operand:SI 1 "general_operand" "d,R,T")))]
"s390_match_ccmode(insn, CCUmode)"
"@
clr\\t%0,%1
cl\\t%0,%1
cly\\t%0,%1"
clr\t%0,%1
cl\t%0,%1
cly\t%0,%1"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*cmphi_ccu"
......@@ -807,8 +807,8 @@
(match_operand:HI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
"@
clm\\t%0,3,%1
clmy\\t%0,3,%1"
clm\t%0,3,%1
clmy\t%0,3,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*cmpqi_ccu"
......@@ -817,8 +817,8 @@
(match_operand:QI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)"
"@
clm\\t%0,1,%1
clmy\\t%0,1,%1"
clm\t%0,1,%1
clmy\t%0,1,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*cli"
......@@ -827,8 +827,8 @@
(match_operand:QI 1 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, CCUmode)"
"@
cli\\t%0,%b1
cliy\\t%0,%b1"
cli\t%0,%b1
cliy\t%0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*cmpdi_ccu_mem"
......@@ -836,7 +836,7 @@
(compare (match_operand:DI 0 "s_operand" "Q")
(match_operand:DI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(8,%R0),%1"
"clc\t%O0(8,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*cmpsi_ccu_mem"
......@@ -844,7 +844,7 @@
(compare (match_operand:SI 0 "s_operand" "Q")
(match_operand:SI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(4,%R0),%1"
"clc\t%O0(4,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*cmphi_ccu_mem"
......@@ -852,7 +852,7 @@
(compare (match_operand:HI 0 "s_operand" "Q")
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(2,%R0),%1"
"clc\t%O0(2,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*cmpqi_ccu_mem"
......@@ -860,7 +860,7 @@
(compare (match_operand:QI 0 "s_operand" "Q")
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(1,%R0),%1"
"clc\t%O0(1,%R0),%1"
[(set_attr "op_type" "SS")])
......@@ -871,7 +871,7 @@
(compare (match_operand:DF 0 "register_operand" "f")
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltdbr\\t%0,%0"
"ltdbr\t%0,%0"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
......@@ -880,7 +880,7 @@
(compare (match_operand:DF 0 "register_operand" "f")
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"ltdr\\t%0,%0"
"ltdr\t%0,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "fsimpd")])
......@@ -890,8 +890,8 @@
(match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cdbr\\t%0,%1
cdb\\t%0,%1"
cdbr\t%0,%1
cdb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd")])
......@@ -901,8 +901,8 @@
(match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cdr\\t%0,%1
cd\\t%0,%1"
cdr\t%0,%1
cd\t%0,%1"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimpd")])
......@@ -914,7 +914,7 @@
(compare (match_operand:SF 0 "register_operand" "f")
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltebr\\t%0,%0"
"ltebr\t%0,%0"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
......@@ -923,7 +923,7 @@
(compare (match_operand:SF 0 "register_operand" "f")
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lter\\t%0,%0"
"lter\t%0,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "fsimps")])
......@@ -933,8 +933,8 @@
(match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
cebr\\t%0,%1
ceb\\t%0,%1"
cebr\t%0,%1
ceb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps")])
......@@ -944,8 +944,8 @@
(match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
cer\\t%0,%1
ce\\t%0,%1"
cer\t%0,%1
ce\t%0,%1"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimps")])
......@@ -963,11 +963,11 @@
(match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT"
"@
lmg\\t%0,%N0,%1
stmg\\t%1,%N1,%0
lmg\t%0,%N0,%1
stmg\t%1,%N1,%0
#
#
mvc\\t%O0(16,%R0),%1"
mvc\t%O0(16,%R0),%1"
[(set_attr "op_type" "RSY,RSY,NN,NN,SS")
(set_attr "type" "lm,stm,*,*,cs")])
......@@ -1052,7 +1052,7 @@
&& GET_CODE (operands[1]) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
&& !FP_REG_P (operands[0])"
"lghi\\t%0,%h1"
"lghi\t%0,%h1"
[(set_attr "op_type" "RI")])
(define_insn "*movdi_lli"
......@@ -1066,10 +1066,10 @@
switch (part)
{
case 0: return "llihh\\t%0,%x1";
case 1: return "llihl\\t%0,%x1";
case 2: return "llilh\\t%0,%x1";
case 3: return "llill\\t%0,%x1";
case 0: return "llihh\t%0,%x1";
case 1: return "llihl\t%0,%x1";
case 2: return "llilh\t%0,%x1";
case 3: return "llill\t%0,%x1";
default: abort ();
}
}
......@@ -1082,7 +1082,7 @@
&& TARGET_LONG_DISPLACEMENT
&& GET_CODE (operands[1]) == CONST_INT
&& !FP_REG_P (operands[0])"
"lay\\t%0,%a1"
"lay\t%0,%a1"
[(set_attr "op_type" "RXY")
(set_attr "type" "la")])
......@@ -1091,7 +1091,7 @@
(match_operand:DI 1 "larl_operand" "X"))]
"TARGET_64BIT
&& !FP_REG_P (operands[0])"
"larl\\t%0,%1"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")])
......@@ -1100,15 +1100,15 @@
(match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))]
"TARGET_64BIT"
"@
lgr\\t%0,%1
lg\\t%0,%1
stg\\t%1,%0
ldr\\t%0,%1
ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0
stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
mvc\t%O0(8,%R0),%1"
[(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")])
......@@ -1117,16 +1117,16 @@
(match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT"
"@
lm\\t%0,%N0,%1
stm\\t%1,%N1,%0
lm\t%0,%N0,%1
stm\t%1,%N1,%0
#
#
ldr\\t%0,%1
ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0
stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1"
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
mvc\t%O0(8,%R0),%1"
[(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
......@@ -1236,7 +1236,7 @@
"GET_CODE (operands[1]) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
&& !FP_REG_P (operands[0])"
"lhi\\t%0,%h1"
"lhi\t%0,%h1"
[(set_attr "op_type" "RI")])
(define_insn "*movsi_lli"
......@@ -1250,8 +1250,8 @@
switch (part)
{
case 0: return "llilh\\t%0,%x1";
case 1: return "llill\\t%0,%x1";
case 0: return "llilh\t%0,%x1";
case 1: return "llill\t%0,%x1";
default: abort ();
}
}
......@@ -1263,7 +1263,7 @@
"TARGET_LONG_DISPLACEMENT
&& GET_CODE (operands[1]) == CONST_INT
&& !FP_REG_P (operands[0])"
"lay\\t%0,%a1"
"lay\t%0,%a1"
[(set_attr "op_type" "RXY")
(set_attr "type" "la")])
......@@ -1272,17 +1272,17 @@
(match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
""
"@
lr\\t%0,%1
l\\t%0,%1
ly\\t%0,%1
st\\t%1,%0
sty\\t%1,%0
ler\\t%0,%1
le\\t%0,%1
ley\\t%0,%1
ste\\t%1,%0
stey\\t%1,%0
mvc\\t%O0(4,%R0),%1"
lr\t%0,%1
l\t%0,%1
ly\t%0,%1
st\t%1,%0
sty\t%1,%0
ler\t%0,%1
le\t%0,%1
ley\t%0,%1
ste\t%1,%0
stey\t%1,%0
mvc\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
......@@ -1306,13 +1306,13 @@
(match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%h1
lh\\t%0,%1
lhy\\t%0,%1
sth\\t%1,%0
sthy\\t%1,%0
mvc\\t%O0(2,%R0),%1"
lr\t%0,%1
lhi\t%0,%h1
lh\t%0,%1
lhy\t%0,%1
sth\t%1,%0
sthy\t%1,%0
mvc\t%O0(2,%R0),%1"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
(set_attr "type" "lr,*,*,*,store,store,cs")])
......@@ -1335,14 +1335,14 @@
(match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
lhi\\t%0,%b1
llgc\\t%0,%1
stc\\t%1,%0
stcy\\t%1,%0
mvi\\t%0,%b1
mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
lr\t%0,%1
lhi\t%0,%b1
llgc\t%0,%1
stc\t%1,%0
stcy\t%1,%0
mvi\t%0,%b1
mviy\t%0,%b1
mvc\t%O0(1,%R0),%1"
[(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
(set_attr "type" "lr,*,*,store,store,store,store,cs")])
......@@ -1351,15 +1351,15 @@
(match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
""
"@
lr\\t%0,%1
lhi\\t%0,%b1
ic\\t%0,%1
icy\\t%0,%1
stc\\t%1,%0
stcy\\t%1,%0
mvi\\t%0,%b1
mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
lr\t%0,%1
lhi\t%0,%b1
ic\t%0,%1
icy\t%0,%1
stc\t%1,%0
stcy\t%1,%0
mvi\t%0,%b1
mviy\t%0,%b1
mvc\t%O0(1,%R0),%1"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
(set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
......@@ -1382,8 +1382,8 @@
(match_operand:QI 1 "memory_operand" "R,T"))]
""
"@
ic\\t%0,%1
icy\\t%0,%1"
ic\t%0,%1
icy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
;
......@@ -1396,8 +1396,8 @@
(clobber (reg:CC 33))]
""
"@
icm\\t%0,3,%1
icmy\\t%0,3,%1"
icm\t%0,3,%1
icmy\t%0,3,%1"
[(set_attr "op_type" "RS,RSY")])
;
......@@ -1409,9 +1409,9 @@
(match_operand:SI 1 "general_operand" "d,R,T"))]
"TARGET_64BIT"
"@
lr\\t%0,%1
l\\t%0,%1
ly\\t%0,%1"
lr\t%0,%1
l\t%0,%1
ly\t%0,%1"
[(set_attr "op_type" "RR,RX,RXY")
(set_attr "type" "lr,load,load")])
......@@ -1436,15 +1436,15 @@
(match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
"TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0
stdy\\t%1,%0
lgr\\t%0,%1
lg\\t%0,%1
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0
mvc\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
......@@ -1453,16 +1453,16 @@
(match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT"
"@
ldr\\t%0,%1
ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0
stdy\\t%1,%0
lm\\t%0,%N0,%1
stm\\t%1,%N1,%0
ldr\t%0,%1
ld\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
lm\t%0,%N0,%1
stm\t%1,%N1,%0
#
#
mvc\\t%O0(8,%R0),%1"
mvc\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
......@@ -1540,17 +1540,17 @@
(match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
""
"@
ler\\t%0,%1
le\\t%0,%1
ley\\t%0,%1
ste\\t%1,%0
stey\\t%1,%0
lr\\t%0,%1
l\\t%0,%1
ly\\t%0,%1
st\\t%1,%0
sty\\t%1,%0
mvc\\t%O0(4,%R0),%1"
ler\t%0,%1
le\t%0,%1
ley\t%0,%1
ste\t%1,%0
stey\t%1,%0
lr\t%0,%1
l\t%0,%1
ly\t%0,%1
st\t%1,%0
sty\t%1,%0
mvc\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
......@@ -1625,7 +1625,7 @@
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
return "lmg\\t%1,%0,%2";
return "lmg\t%1,%0,%2";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "lm")])
......@@ -1638,7 +1638,7 @@
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
return which_alternative == 0 ? "lm\\t%1,%0,%2" : "lmy\\t%1,%0,%2";
return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")])
......@@ -1716,7 +1716,7 @@
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
return "stmg\\t%2,%0,%1";
return "stmg\t%2,%0,%1";
}
[(set_attr "op_type" "RSY")
(set_attr "type" "stm")])
......@@ -1730,7 +1730,7 @@
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
return which_alternative == 0 ? "stm\\t%2,%0,%1" : "stmy\\t%2,%0,%1";
return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1";
}
[(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")])
......@@ -1772,12 +1772,12 @@
switch (which_alternative)
{
case 0:
return "mvc\\t%O0(%b2+1,%R0),%1";
return "mvc\t%O0(%b2+1,%R0),%1";
case 1:
output_asm_insn ("bras\\t%3,.+10", operands);
output_asm_insn ("mvc\\t%O0(1,%R0),%1", operands);
return "ex\\t%2,0(%3)";
output_asm_insn ("bras\t%3,.+10", operands);
output_asm_insn ("mvc\t%O0(1,%R0),%1", operands);
return "ex\t%2,0(%3)";
default:
abort ();
......@@ -1798,12 +1798,12 @@
switch (which_alternative)
{
case 0:
return "mvc\\t%O0(%b2+1,%R0),%1";
return "mvc\t%O0(%b2+1,%R0),%1";
case 1:
output_asm_insn ("bras\\t%3,.+10", operands);
output_asm_insn ("mvc\\t%O0(1,%R0),%1", operands);
return "ex\\t%2,0(%3)";
output_asm_insn ("bras\t%3,.+10", operands);
output_asm_insn ("mvc\t%O0(1,%R0),%1", operands);
return "ex\t%2,0(%3)";
default:
abort ();
......@@ -1829,7 +1829,7 @@
(mem:BLK (subreg:DI (match_dup 3) 0)))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
(set_attr "length" "8")])
......@@ -1847,7 +1847,7 @@
(mem:BLK (subreg:SI (match_dup 3) 0)))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
(set_attr "length" "8")])
......@@ -1886,12 +1886,12 @@
switch (which_alternative)
{
case 0:
return "xc\\t%O0(%b1+1,%R0),%0";
return "xc\t%O0(%b1+1,%R0),%0";
case 1:
output_asm_insn ("bras\\t%2,.+10", operands);
output_asm_insn ("xc\\t%O0(1,%R0),%0", operands);
return "ex\\t%1,0(%2)";
output_asm_insn ("bras\t%2,.+10", operands);
output_asm_insn ("xc\t%O0(1,%R0),%0", operands);
return "ex\t%1,0(%2)";
default:
abort ();
......@@ -1913,12 +1913,12 @@
switch (which_alternative)
{
case 0:
return "xc\\t%O0(%b1+1,%R0),%0";
return "xc\t%O0(%b1+1,%R0),%0";
case 1:
output_asm_insn ("bras\\t%2,.+10", operands);
output_asm_insn ("xc\\t%O0(1,%R0),%0", operands);
return "ex\\t%1,0(%2)";
output_asm_insn ("bras\t%2,.+10", operands);
output_asm_insn ("xc\t%O0(1,%R0),%0", operands);
return "ex\t%1,0(%2)";
default:
abort ();
......@@ -1941,7 +1941,7 @@
(use (match_operand:TI 1 "register_operand" "d"))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
(set_attr "length" "8")])
......@@ -1956,7 +1956,7 @@
(use (match_operand:DI 1 "register_operand" "d"))
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
(set_attr "length" "8")])
......@@ -1999,12 +1999,12 @@
switch (which_alternative)
{
case 0:
return "clc\\t%O0(%b2+1,%R0),%1";
return "clc\t%O0(%b2+1,%R0),%1";
case 1:
output_asm_insn ("bras\\t%3,.+10", operands);
output_asm_insn ("clc\\t%O0(1,%R0),%1", operands);
return "ex\\t%2,0(%3)";
output_asm_insn ("bras\t%3,.+10", operands);
output_asm_insn ("clc\t%O0(1,%R0),%1", operands);
return "ex\t%2,0(%3)";
default:
abort ();
......@@ -2026,12 +2026,12 @@
switch (which_alternative)
{
case 0:
return "clc\\t%O0(%b2+1,%R0),%1";
return "clc\t%O0(%b2+1,%R0),%1";
case 1:
output_asm_insn ("bras\\t%3,.+10", operands);
output_asm_insn ("clc\\t%O0(1,%R0),%1", operands);
return "ex\\t%2,0(%3)";
output_asm_insn ("bras\t%3,.+10", operands);
output_asm_insn ("clc\t%O0(1,%R0),%1", operands);
return "ex\t%2,0(%3)";
default:
abort ();
......@@ -2053,7 +2053,7 @@
(use (match_dup 2))
(use (match_dup 3))]
"TARGET_64BIT"
"clcl\\t%0,%1"
"clcl\t%0,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "vs")])
......@@ -2066,7 +2066,7 @@
(use (match_dup 2))
(use (match_dup 3))]
"!TARGET_64BIT"
"clcl\\t%0,%1"
"clcl\t%0,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "vs")])
......@@ -2077,11 +2077,11 @@
(compare:SI (reg:CCS 33) (const_int 0)))]
""
{
output_asm_insn ("lhi\\t%0,1", operands);
output_asm_insn ("jh\\t.+12", operands);
output_asm_insn ("jl\\t.+6", operands);
output_asm_insn ("sr\\t%0,%0", operands);
return "lcr\\t%0,%0";
output_asm_insn ("lhi\t%0,1", operands);
output_asm_insn ("jh\t.+12", operands);
output_asm_insn ("jl\t.+6", operands);
output_asm_insn ("sr\t%0,%0", operands);
return "lcr\t%0,%0";
}
[(set_attr "op_type" "NN")
(set_attr "length" "16")
......@@ -2092,11 +2092,11 @@
(compare:DI (reg:CCS 33) (const_int 0)))]
"TARGET_64BIT"
{
output_asm_insn ("lghi\\t%0,1", operands);
output_asm_insn ("jh\\t.+12", operands);
output_asm_insn ("jl\\t.+6", operands);
output_asm_insn ("sgr\\t%0,%0", operands);
return "lcgr\\t%0,%0";
output_asm_insn ("lghi\t%0,1", operands);
output_asm_insn ("jh\t.+12", operands);
output_asm_insn ("jl\t.+6", operands);
output_asm_insn ("sgr\t%0,%0", operands);
return "lcgr\t%0,%0";
}
[(set_attr "op_type" "NN")
(set_attr "length" "22")
......@@ -2113,8 +2113,8 @@
(clobber (reg:CC 33))]
""
"@
icm\\t%0,8,%1
icmy\\t%0,8,%1"
icm\t%0,8,%1
icmy\t%0,8,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighhisi"
......@@ -2123,8 +2123,8 @@
(clobber (reg:CC 33))]
""
"@
icm\\t%0,12,%1
icmy\\t%0,12,%1"
icm\t%0,12,%1
icmy\t%0,12,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64"
......@@ -2132,7 +2132,7 @@
(unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
"icmh\t%0,8,%1"
[(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31"
......@@ -2141,8 +2141,8 @@
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"@
icm\\t%0,8,%1
icmy\\t%0,8,%1"
icm\t%0,8,%1
icmy\t%0,8,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi"
......@@ -2211,8 +2211,8 @@
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
"TARGET_64BIT"
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
lgfr\t%0,%1
lgf\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
;
......@@ -2246,7 +2246,7 @@
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")])
;
......@@ -2280,7 +2280,7 @@
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
"lgb\\t%0,%1"
"lgb\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_split
......@@ -2317,8 +2317,8 @@
(sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
""
"@
lh\\t%0,%1
lhy\\t%0,%1"
lh\t%0,%1
lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
;
......@@ -2342,7 +2342,7 @@
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
"lb\\t%0,%1"
"lb\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_split
......@@ -2387,8 +2387,8 @@
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
"TARGET_64BIT"
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
llgfr\t%0,%1
llgf\t%0,%1"
[(set_attr "op_type" "RRE,RXY")])
;
......@@ -2422,7 +2422,7 @@
[(set (match_operand:DI 0 "register_operand" "=d")
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
"llgh\t%0,%1"
[(set_attr "op_type" "RXY")])
;
......@@ -2456,7 +2456,7 @@
[(set (match_operand:DI 0 "register_operand" "=d")
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
;
......@@ -2479,7 +2479,7 @@
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
"llgh\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendhisi2_31"
......@@ -2516,7 +2516,7 @@
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqisi2_31"
......@@ -2550,7 +2550,7 @@
[(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqihi2_31"
......@@ -2611,7 +2611,7 @@
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC 33))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgdbr\\t%0,%h2,%1"
"cgdbr\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
......@@ -2677,7 +2677,7 @@
(unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cfdbr\\t%0,%h2,%1"
"cfdbr\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "other" )])
......@@ -2690,11 +2690,11 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
{
output_asm_insn ("sd\\t%1,%2", operands);
output_asm_insn ("aw\\t%1,%3", operands);
output_asm_insn ("std\\t%1,%4", operands);
output_asm_insn ("xi\\t%N4,128", operands);
return "l\\t%0,%N4";
output_asm_insn ("sd\t%1,%2", operands);
output_asm_insn ("aw\t%1,%3", operands);
output_asm_insn ("std\t%1,%4", operands);
output_asm_insn ("xi\t%N4,128", operands);
return "l\t%0,%N4";
}
[(set_attr "op_type" "NN")
(set_attr "type" "ftoi")
......@@ -2748,7 +2748,7 @@
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC 33))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgebr\\t%0,%h2,%1"
"cgebr\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
......@@ -2809,7 +2809,7 @@
(unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cfebr\\t%0,%h2,%1"
"cfebr\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
......@@ -2822,7 +2822,7 @@
(float:DF (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdgbr\\t%0,%1"
"cdgbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
......@@ -2835,7 +2835,7 @@
(float:SF (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cegbr\\t%0,%1"
"cegbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
......@@ -2867,7 +2867,7 @@
(float:DF (match_operand:SI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdfbr\\t%0,%1"
"cdfbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
......@@ -2879,11 +2879,11 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
{
output_asm_insn ("st\\t%1,%N3", operands);
output_asm_insn ("xi\\t%N3,128", operands);
output_asm_insn ("mvc\\t%O3(4,%R3),%2", operands);
output_asm_insn ("ld\\t%0,%3", operands);
return "sd\\t%0,%2";
output_asm_insn ("st\t%1,%N3", operands);
output_asm_insn ("xi\t%N3,128", operands);
output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
output_asm_insn ("ld\t%0,%3", operands);
return "sd\t%0,%2";
}
[(set_attr "op_type" "NN")
(set_attr "type" "other" )
......@@ -2916,7 +2916,7 @@
(float:SF (match_operand:SI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cefbr\\t%0,%1"
"cefbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof" )])
......@@ -2934,7 +2934,7 @@
[(set (match_operand:SF 0 "register_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ledbr\\t%0,%1"
"ledbr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "truncdfsf2_ibm"
......@@ -2942,8 +2942,8 @@
(float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
lrer\\t%0,%1
le\\t%0,%1"
lrer\t%0,%1
le\t%0,%1"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "floads,floads")])
......@@ -2968,8 +2968,8 @@
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
ldebr\\t%0,%1
ldeb\\t%0,%1"
ldebr\t%0,%1
ldeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "floads,floads")])
......@@ -2979,8 +2979,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
sdr\\t%0,%0\;ler\\t%0,%1
sdr\\t%0,%0\;le\\t%0,%1"
sdr\t%0,%0\;ler\t%0,%1
sdr\t%0,%0\;le\t%0,%1"
[(set_attr "op_type" "NN,NN")
(set_attr "atype" "reg,agen")
(set_attr "length" "4,6")
......@@ -3009,8 +3009,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
agfr\\t%0,%2
agf\\t%0,%2"
agfr\t%0,%2
agf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc"
......@@ -3022,8 +3022,8 @@
(plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algfr\\t%0,%2
algf\\t%0,%2"
algfr\t%0,%2
algf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly"
......@@ -3034,8 +3034,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algfr\\t%0,%2
algf\\t%0,%2"
algfr\t%0,%2
algf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero"
......@@ -3045,8 +3045,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
algfr\\t%0,%2
algf\\t%0,%2"
algfr\t%0,%2
algf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
......@@ -3059,7 +3059,7 @@
"TARGET_64BIT
&& s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"aghi\\t%0,%h2"
"aghi\t%0,%h2"
[(set_attr "op_type" "RI")])
(define_insn "*adddi3_cc"
......@@ -3071,8 +3071,8 @@
(plus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algr\\t%0,%2
alg\\t%0,%2"
algr\t%0,%2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly"
......@@ -3083,8 +3083,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
algr\\t%0,%2
alg\\t%0,%2"
algr\t%0,%2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
......@@ -3094,8 +3094,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
"@
algr\\t%0,%2
alg\\t%0,%2"
algr\t%0,%2
alg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_64"
......@@ -3105,9 +3105,9 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
agr\t%0,%2
aghi\t%0,%h2
ag\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXY")])
(define_insn_and_split "*adddi3_31"
......@@ -3157,8 +3157,8 @@
(match_operand:QI 1 "address_operand" "U,W"))]
"TARGET_64BIT"
"@
la\\t%0,%a1
lay\\t%0,%a1"
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
......@@ -3212,7 +3212,7 @@
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"ahi\\t%0,%h2"
"ahi\t%0,%h2"
[(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc"
......@@ -3224,9 +3224,9 @@
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
aly\\t%0,%2"
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
......@@ -3237,9 +3237,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
aly\\t%0,%2"
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc"
......@@ -3251,9 +3251,9 @@
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
aly\\t%0,%2"
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
......@@ -3264,9 +3264,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
aly\\t%0,%2"
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc"
......@@ -3278,9 +3278,9 @@
(plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
al\\t%0,%2
aly\\t%0,%2"
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly"
......@@ -3291,9 +3291,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
al\\t%0,%2
aly\\t%0,%2"
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2"
......@@ -3303,9 +3303,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
alr\\t%0,%2
al\\t%0,%2
aly\\t%0,%2"
alr\t%0,%2
al\t%0,%2
aly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_sign"
......@@ -3315,8 +3315,8 @@
(clobber (reg:CC 33))]
""
"@
ah\\t%0,%2
ahy\\t%0,%2"
ah\t%0,%2
ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*addsi3_sub"
......@@ -3326,8 +3326,8 @@
(clobber (reg:CC 33))]
""
"@
ah\\t%0,%2
ahy\\t%0,%2"
ah\t%0,%2
ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "addsi3"
......@@ -3337,10 +3337,10 @@
(clobber (reg:CC 33))]
""
"@
ar\\t%0,%2
ahi\\t%0,%h2
a\\t%0,%2
ay\\t%0,%2"
ar\t%0,%2
ahi\t%0,%h2
a\t%0,%2
ay\t%0,%2"
[(set_attr "op_type" "RR,RI,RX,RXY")])
(define_insn "*la_31"
......@@ -3348,8 +3348,8 @@
(match_operand:QI 1 "address_operand" "U,W"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
"@
la\\t%0,%a1
lay\\t%0,%a1"
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
......@@ -3385,8 +3385,8 @@
(const_int 2147483647)))]
"!TARGET_64BIT"
"@
la\\t%0,%a1
lay\\t%0,%a1"
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")])
......@@ -3410,8 +3410,8 @@
(use (const_int 0))]
"!TARGET_64BIT"
"@
la\\t%0,%a1
lay\\t%0,%a1"
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "la")])
......@@ -3446,8 +3446,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
adbr\\t%0,%2
adb\\t%0,%2"
adbr\t%0,%2
adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3460,8 +3460,8 @@
(plus:DF (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
adbr\\t%0,%2
adb\\t%0,%2"
adbr\t%0,%2
adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3473,8 +3473,8 @@
(clobber (match_scratch:DF 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
adbr\\t%0,%2
adb\\t%0,%2"
adbr\t%0,%2
adb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3485,8 +3485,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
adr\\t%0,%2
ad\\t%0,%2"
adr\t%0,%2
ad\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3510,8 +3510,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
aebr\\t%0,%2
aeb\\t%0,%2"
aebr\t%0,%2
aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
......@@ -3524,8 +3524,8 @@
(plus:SF (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
aebr\\t%0,%2
aeb\\t%0,%2"
aebr\t%0,%2
aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
......@@ -3537,8 +3537,8 @@
(clobber (match_scratch:SF 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
aebr\\t%0,%2
aeb\\t%0,%2"
aebr\t%0,%2
aeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
......@@ -3549,8 +3549,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
aer\\t%0,%2
ae\\t%0,%2"
aer\t%0,%2
ae\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimps,fsimps")])
......@@ -3570,8 +3570,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
sgfr\t%0,%2
sgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc"
......@@ -3583,8 +3583,8 @@
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
slgfr\t%0,%2
slgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly"
......@@ -3595,8 +3595,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
slgfr\t%0,%2
slgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero"
......@@ -3606,8 +3606,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
slgfr\t%0,%2
slgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc"
......@@ -3619,8 +3619,8 @@
(minus:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
slgr\\t%0,%2
slg\\t%0,%2"
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly"
......@@ -3631,8 +3631,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
slgr\\t%0,%2
slg\\t%0,%2"
slgr\t%0,%2
slg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_64"
......@@ -3642,8 +3642,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
sgr\\t%0,%2
sg\\t%0,%2"
sgr\t%0,%2
sg\t%0,%2"
[(set_attr "op_type" "RRE,RRE")])
(define_insn_and_split "*subdi3_31"
......@@ -3701,9 +3701,9 @@
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
sl\\t%0,%2
sly\\t%0,%2"
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_borrow_cconly"
......@@ -3714,9 +3714,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCL2mode)"
"@
slr\\t%0,%2
sl\\t%0,%2
sly\\t%0,%2"
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXE")])
(define_insn "*subsi3_cc"
......@@ -3728,9 +3728,9 @@
(minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
sl\\t%0,%2
sly\\t%0,%2"
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly"
......@@ -3741,9 +3741,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
slr\\t%0,%2
sl\\t%0,%2
sly\\t%0,%2"
slr\t%0,%2
sl\t%0,%2
sly\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_sign"
......@@ -3753,8 +3753,8 @@
(clobber (reg:CC 33))]
""
"@
sh\\t%0,%2
shy\\t%0,%2"
sh\t%0,%2
shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*subsi3_sub"
......@@ -3764,8 +3764,8 @@
(clobber (reg:CC 33))]
""
"@
sh\\t%0,%2
shy\\t%0,%2"
sh\t%0,%2
shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "subsi3"
......@@ -3775,9 +3775,9 @@
(clobber (reg:CC 33))]
""
"@
sr\\t%0,%2
s\\t%0,%2
sy\\t%0,%2"
sr\t%0,%2
s\t%0,%2
sy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
......@@ -3801,8 +3801,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sdbr\\t%0,%2
sdb\\t%0,%2"
sdbr\t%0,%2
sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3815,8 +3815,8 @@
(plus:DF (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sdbr\\t%0,%2
sdb\\t%0,%2"
sdbr\t%0,%2
sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3828,8 +3828,8 @@
(clobber (match_scratch:DF 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sdbr\\t%0,%2
sdb\\t%0,%2"
sdbr\t%0,%2
sdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3840,8 +3840,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
sdr\\t%0,%2
sd\\t%0,%2"
sdr\t%0,%2
sd\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimpd,fsimpd")])
......@@ -3865,8 +3865,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sebr\\t%0,%2
seb\\t%0,%2"
sebr\t%0,%2
seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
......@@ -3879,8 +3879,8 @@
(minus:SF (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sebr\\t%0,%2
seb\\t%0,%2"
sebr\t%0,%2
seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
......@@ -3892,8 +3892,8 @@
(clobber (match_scratch:SF 0 "=f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sebr\\t%0,%2
seb\\t%0,%2"
sebr\t%0,%2
seb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fsimps,fsimps")])
......@@ -3904,8 +3904,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
ser\\t%0,%2
se\\t%0,%2"
ser\t%0,%2
se\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fsimps,fsimps")])
......@@ -3924,8 +3924,8 @@
(match_operand:DI 1 "register_operand" "0,0")))]
"TARGET_64BIT"
"@
msgfr\\t%0,%2
msgf\\t%0,%2"
msgfr\t%0,%2
msgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")])
......@@ -3936,9 +3936,9 @@
(match_operand:DI 2 "general_operand" "d,K,m")))]
"TARGET_64BIT"
"@
msgr\\t%0,%2
mghi\\t%0,%h2
msg\\t%0,%2"
msgr\t%0,%2
mghi\t%0,%h2
msg\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXY")
(set_attr "type" "imul")])
......@@ -3952,10 +3952,10 @@
(match_operand:SI 2 "general_operand" "d,K,R,T")))]
""
"@
msr\\t%0,%2
mhi\\t%0,%h2
ms\\t%0,%2
msy\\t%0,%2"
msr\t%0,%2
mhi\t%0,%h2
ms\t%0,%2
msy\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX,RXY")
(set_attr "type" "imul")])
......@@ -3991,8 +3991,8 @@
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
"!TARGET_64BIT"
"@
mr\\t%0,%2
m\\t%0,%2"
mr\t%0,%2
m\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "imul")])
......@@ -4016,8 +4016,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
mdbr\\t%0,%2
mdb\\t%0,%2"
mdbr\t%0,%2
mdb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuld")])
......@@ -4028,8 +4028,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
mdr\\t%0,%2
md\\t%0,%2"
mdr\t%0,%2
md\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuld")])
......@@ -4053,8 +4053,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
meebr\\t%0,%2
meeb\\t%0,%2"
meebr\t%0,%2
meeb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fmuls")])
......@@ -4065,8 +4065,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
mer\\t%0,%2
me\\t%0,%2"
mer\t%0,%2
me\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fmuls")])
......@@ -4130,8 +4130,8 @@
(const_int 64))))]
"TARGET_64BIT"
"@
dsgr\\t%0,%2
dsg\\t%0,%2"
dsgr\t%0,%2
dsg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
......@@ -4148,8 +4148,8 @@
(const_int 64))))]
"TARGET_64BIT"
"@
dsgfr\\t%0,%2
dsgf\\t%0,%2"
dsgfr\t%0,%2
dsgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
......@@ -4209,8 +4209,8 @@
(const_int 64))))]
"TARGET_64BIT"
"@
dlgr\\t%0,%2
dlg\\t%0,%2"
dlgr\t%0,%2
dlg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
......@@ -4268,8 +4268,8 @@
(const_int 32))))]
"!TARGET_64BIT"
"@
dr\\t%0,%2
d\\t%0,%2"
dr\t%0,%2
d\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "idiv")])
......@@ -4480,8 +4480,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
ddbr\\t%0,%2
ddb\\t%0,%2"
ddbr\t%0,%2
ddb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fdivd")])
......@@ -4492,8 +4492,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
ddr\\t%0,%2
dd\\t%0,%2"
ddr\t%0,%2
dd\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fdivd")])
......@@ -4517,8 +4517,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
debr\\t%0,%2
deb\\t%0,%2"
debr\t%0,%2
deb\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
(set_attr "type" "fdivs")])
......@@ -4529,8 +4529,8 @@
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
der\\t%0,%2
de\\t%0,%2"
der\t%0,%2
de\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "fdivs")])
......@@ -4552,8 +4552,8 @@
(and:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ngr\\t%0,%2
ng\\t%0,%2"
ngr\t%0,%2
ng\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_cconly"
......@@ -4564,8 +4564,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ngr\\t%0,%2
ng\\t%0,%2"
ngr\t%0,%2
ng\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ni"
......@@ -4580,10 +4580,10 @@
switch (part)
{
case 0: return "nihh\\t%0,%x2";
case 1: return "nihl\\t%0,%x2";
case 2: return "nilh\\t%0,%x2";
case 3: return "nill\\t%0,%x2";
case 0: return "nihh\t%0,%x2";
case 1: return "nihl\t%0,%x2";
case 2: return "nilh\t%0,%x2";
case 3: return "nill\t%0,%x2";
default: abort ();
}
}
......@@ -4596,8 +4596,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
ngr\\t%0,%2
ng\\t%0,%2"
ngr\t%0,%2
ng\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ss"
......@@ -4606,7 +4606,7 @@
(match_operand:DI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
"nc\t%O0(8,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*anddi3_ss_inv"
......@@ -4615,7 +4615,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
"nc\t%O0(8,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -4631,9 +4631,9 @@
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
n\\t%0,%2
ny\\t%0,%2"
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_cconly"
......@@ -4644,9 +4644,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
nr\\t%0,%2
n\\t%0,%2
ny\\t%0,%2"
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ni"
......@@ -4661,8 +4661,8 @@
switch (part)
{
case 0: return "nilh\\t%0,%x2";
case 1: return "nill\\t%0,%x2";
case 0: return "nilh\t%0,%x2";
case 1: return "nill\t%0,%x2";
default: abort ();
}
}
......@@ -4675,9 +4675,9 @@
(clobber (reg:CC 33))]
""
"@
nr\\t%0,%2
n\\t%0,%2
ny\\t%0,%2"
nr\t%0,%2
n\t%0,%2
ny\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ss"
......@@ -4686,7 +4686,7 @@
(match_operand:SI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
"nc\t%O0(4,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*andsi3_ss_inv"
......@@ -4695,7 +4695,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
"nc\t%O0(4,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -4709,8 +4709,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
nr\\t%0,%2
nill\\t%0,%x2"
nr\t%0,%2
nill\t%0,%x2"
[(set_attr "op_type" "RR,RI")])
(define_insn "andhi3"
......@@ -4719,7 +4719,7 @@
(match_operand:HI 2 "nonmemory_operand" "d")))
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
"nr\t%0,%2"
[(set_attr "op_type" "RR")])
(define_insn "*andhi3_ss"
......@@ -4728,7 +4728,7 @@
(match_operand:HI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
"nc\t%O0(2,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*andhi3_ss_inv"
......@@ -4737,7 +4737,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
"nc\t%O0(2,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -4751,8 +4751,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
nr\\t%0,%2
nill\\t%0,%b2"
nr\t%0,%2
nill\t%0,%b2"
[(set_attr "op_type" "RR,RI")])
(define_insn "andqi3"
......@@ -4761,7 +4761,7 @@
(match_operand:QI 2 "nonmemory_operand" "d")))
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
"nr\t%0,%2"
[(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss"
......@@ -4771,9 +4771,9 @@
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
ni\t%0,%b1
niy\t%0,%b1
nc\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*andqi3_ss_inv"
......@@ -4783,9 +4783,9 @@
(clobber (reg:CC 33))]
""
"@
ni\\t%0,%b1
niy\\t%0,%b1
nc\\t%O0(1,%R0),%1"
ni\t%0,%b1
niy\t%0,%b1
nc\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SIY,SS")])
......@@ -4806,8 +4806,8 @@
(ior:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ogr\\t%0,%2
og\\t%0,%2"
ogr\t%0,%2
og\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_cconly"
......@@ -4818,8 +4818,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
ogr\\t%0,%2
og\\t%0,%2"
ogr\t%0,%2
og\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_oi"
......@@ -4834,10 +4834,10 @@
switch (part)
{
case 0: return "oihh\\t%0,%x2";
case 1: return "oihl\\t%0,%x2";
case 2: return "oilh\\t%0,%x2";
case 3: return "oill\\t%0,%x2";
case 0: return "oihh\t%0,%x2";
case 1: return "oihl\t%0,%x2";
case 2: return "oilh\t%0,%x2";
case 3: return "oill\t%0,%x2";
default: abort ();
}
}
......@@ -4850,8 +4850,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
ogr\\t%0,%2
og\\t%0,%2"
ogr\t%0,%2
og\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_ss"
......@@ -4860,7 +4860,7 @@
(match_operand:DI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
"oc\t%O0(8,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*iordi3_ss_inv"
......@@ -4869,7 +4869,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
"oc\t%O0(8,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -4885,9 +4885,9 @@
(ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
o\\t%0,%2
oy\\t%0,%2"
or\t%0,%2
o\t%0,%2
oy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_cconly"
......@@ -4898,9 +4898,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
or\\t%0,%2
o\\t%0,%2
oy\\t%0,%2"
or\t%0,%2
o\t%0,%2
oy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_oi"
......@@ -4915,8 +4915,8 @@
switch (part)
{
case 0: return "oilh\\t%0,%x2";
case 1: return "oill\\t%0,%x2";
case 0: return "oilh\t%0,%x2";
case 1: return "oill\t%0,%x2";
default: abort ();
}
}
......@@ -4929,9 +4929,9 @@
(clobber (reg:CC 33))]
""
"@
or\\t%0,%2
o\\t%0,%2
oy\\t%0,%2"
or\t%0,%2
o\t%0,%2
oy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_ss"
......@@ -4940,7 +4940,7 @@
(match_operand:SI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
"oc\t%O0(4,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*iorsi3_ss_inv"
......@@ -4949,7 +4949,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
"oc\t%O0(4,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -4963,8 +4963,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
or\\t%0,%2
oill\\t%0,%x2"
or\t%0,%2
oill\t%0,%x2"
[(set_attr "op_type" "RR,RI")])
(define_insn "iorhi3"
......@@ -4973,7 +4973,7 @@
(match_operand:HI 2 "nonmemory_operand" "d")))
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
"or\t%0,%2"
[(set_attr "op_type" "RR")])
(define_insn "*iorhi3_ss"
......@@ -4982,7 +4982,7 @@
(match_operand:HI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
"oc\t%O0(2,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*iorhi3_ss_inv"
......@@ -4991,7 +4991,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
"oc\t%O0(2,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -5005,8 +5005,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
or\\t%0,%2
oill\\t%0,%b2"
or\t%0,%2
oill\t%0,%b2"
[(set_attr "op_type" "RR,RI")])
(define_insn "iorqi3"
......@@ -5015,7 +5015,7 @@
(match_operand:QI 2 "nonmemory_operand" "d")))
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
"or\t%0,%2"
[(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss"
......@@ -5025,9 +5025,9 @@
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
oi\t%0,%b1
oiy\t%0,%b1
oc\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*iorqi3_ss_inv"
......@@ -5037,9 +5037,9 @@
(clobber (reg:CC 33))]
""
"@
oi\\t%0,%b1
oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1"
oi\t%0,%b1
oiy\t%0,%b1
oc\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SIY,SS")])
......@@ -5060,8 +5060,8 @@
(xor:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
xgr\\t%0,%2
xg\\t%0,%2"
xgr\t%0,%2
xg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_cconly"
......@@ -5072,8 +5072,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
"@
xgr\\t%0,%2
xr\\t%0,%2"
xgr\t%0,%2
xr\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "xordi3"
......@@ -5083,8 +5083,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
xgr\\t%0,%2
xg\\t%0,%2"
xgr\t%0,%2
xg\t%0,%2"
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_ss"
......@@ -5093,7 +5093,7 @@
(match_operand:DI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
"xc\t%O0(8,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*xordi3_ss_inv"
......@@ -5102,7 +5102,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
"xc\t%O0(8,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -5118,9 +5118,9 @@
(xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
x\\t%0,%2
xy\\t%0,%2"
xr\t%0,%2
x\t%0,%2
xy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_cconly"
......@@ -5131,9 +5131,9 @@
(clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
xr\\t%0,%2
x\\t%0,%2
xy\\t%0,%2"
xr\t%0,%2
x\t%0,%2
xy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "xorsi3"
......@@ -5143,9 +5143,9 @@
(clobber (reg:CC 33))]
""
"@
xr\\t%0,%2
x\\t%0,%2
xy\\t%0,%2"
xr\t%0,%2
x\t%0,%2
xy\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_ss"
......@@ -5154,7 +5154,7 @@
(match_operand:SI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
"xc\t%O0(4,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*xorsi3_ss_inv"
......@@ -5163,7 +5163,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
"xc\t%O0(4,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -5176,7 +5176,7 @@
(match_operand:HI 2 "nonmemory_operand" "d")))
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
"xr\t%0,%2"
[(set_attr "op_type" "RR")])
(define_insn "*xorhi3_ss"
......@@ -5185,7 +5185,7 @@
(match_operand:HI 1 "s_imm_operand" "Q")))
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
"xc\t%O0(2,%R0),%1"
[(set_attr "op_type" "SS")])
(define_insn "*xorhi3_ss_inv"
......@@ -5194,7 +5194,7 @@
(match_dup 0)))
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
"xc\t%O0(2,%R0),%1"
[(set_attr "op_type" "SS")])
;
......@@ -5207,7 +5207,7 @@
(match_operand:QI 2 "nonmemory_operand" "d")))
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
"xr\t%0,%2"
[(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss"
......@@ -5217,9 +5217,9 @@
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
xi\t%0,%b1
xiy\t%0,%b1
xc\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*xorqi3_ss_inv"
......@@ -5229,9 +5229,9 @@
(clobber (reg:CC 33))]
""
"@
xi\\t%0,%b1
xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1"
xi\t%0,%b1
xiy\t%0,%b1
xc\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SIY,SS")])
......@@ -5256,7 +5256,7 @@
(neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"lcgr\\t%0,%1"
"lcgr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "*negdi2_31"
......@@ -5267,10 +5267,10 @@
{
rtx xop[1];
xop[0] = gen_label_rtx ();
output_asm_insn ("lcr\\t%0,%1", operands);
output_asm_insn ("lcr\\t%N0,%N1", operands);
output_asm_insn ("je\\t%l0", xop);
output_asm_insn ("bctr\\t%0,0", operands);
output_asm_insn ("lcr\t%0,%1", operands);
output_asm_insn ("lcr\t%N0,%N1", operands);
output_asm_insn ("je\t%l0", xop);
output_asm_insn ("bctr\t%0,0", operands);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (xop[0]));
return "";
......@@ -5288,7 +5288,7 @@
(neg:SI (match_operand:SI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
""
"lcr\\t%0,%1"
"lcr\t%0,%1"
[(set_attr "op_type" "RR")])
;
......@@ -5308,7 +5308,7 @@
(neg:DF (match_operand:DF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\\t%0,%1"
"lcdbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
......@@ -5317,7 +5317,7 @@
(neg:DF (match_operand:DF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcdr\\t%0,%1"
"lcdr\t%0,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "fsimpd")])
......@@ -5338,7 +5338,7 @@
(neg:SF (match_operand:SF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\\t%0,%1"
"lcebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
......@@ -5347,7 +5347,7 @@
(neg:SF (match_operand:SF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcer\\t%0,%1"
"lcer\t%0,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "fsimps")])
......@@ -5365,7 +5365,7 @@
(abs:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"lpgr\\t%0,%1"
"lpgr\t%0,%1"
[(set_attr "op_type" "RRE")])
;
......@@ -5377,7 +5377,7 @@
(abs:SI (match_operand:SI 1 "register_operand" "d")))
(clobber (reg:CC 33))]
""
"lpr\\t%0,%1"
"lpr\t%0,%1"
[(set_attr "op_type" "RR")])
;
......@@ -5397,7 +5397,7 @@
(abs:DF (match_operand:DF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\\t%0,%1"
"lpdbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
......@@ -5406,7 +5406,7 @@
(abs:DF (match_operand:DF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lpdr\\t%0,%1"
"lpdr\t%0,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "fsimpd")])
......@@ -5427,7 +5427,7 @@
(abs:SF (match_operand:SF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\\t%0,%1"
"lpebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
......@@ -5436,7 +5436,7 @@
(abs:SF (match_operand:SF 1 "register_operand" "f")))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lper\\t%0,%1"
"lper\t%0,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "fsimps")])
......@@ -5453,7 +5453,7 @@
(neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC 33))]
""
"lnr\\t%0,%1"
"lnr\t%0,%1"
[(set_attr "op_type" "RR")])
(define_insn "*negabsdi2"
......@@ -5461,7 +5461,7 @@
(neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
(clobber (reg:CC 33))]
"TARGET_64BIT"
"lngr\\t%0,%1"
"lngr\t%0,%1"
[(set_attr "op_type" "RRE")])
;
......@@ -5473,7 +5473,7 @@
(neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lnebr\\t%0,%1"
"lnebr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimps")])
......@@ -5482,7 +5482,7 @@
(neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lndbr\\t%0,%1"
"lndbr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimpd")])
......@@ -5499,8 +5499,8 @@
(sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
sqdbr\t%0,%1
sqdb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")])
;
......@@ -5512,8 +5512,8 @@
(sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
sqebr\t%0,%1
sqeb\t%0,%1"
[(set_attr "op_type" "RRE,RXE")])
;;
......@@ -5587,8 +5587,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_64BIT"
"@
rllg\\t%0,%1,%c2
rllg\\t%0,%1,0(%2)"
rllg\t%0,%1,%c2
rllg\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
......@@ -5602,8 +5602,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_64BIT"
"@
rll\\t%0,%1,%c2
rll\\t%0,%1,0(%2)"
rll\t%0,%1,%c2
rll\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
......@@ -5629,8 +5629,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
"!TARGET_64BIT"
"@
sldl\\t%0,%c2
sldl\\t%0,0(%2)"
sldl\t%0,%c2
sldl\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5640,8 +5640,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_64BIT"
"@
sllg\\t%0,%1,%2
sllg\\t%0,%1,0(%2)"
sllg\t%0,%1,%2
sllg\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
......@@ -5667,8 +5667,8 @@
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
srda\t%0,%c2
srda\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5680,8 +5680,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
srda\t%0,%c2
srda\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5692,8 +5692,8 @@
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
srda\t%0,%c2
srda\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5706,8 +5706,8 @@
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
srag\t%0,%1,%c2
srag\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
......@@ -5719,8 +5719,8 @@
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
srag\t%0,%1,%c2
srag\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
......@@ -5731,8 +5731,8 @@
(clobber (reg:CC 33))]
"TARGET_64BIT"
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
srag\t%0,%1,%c2
srag\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")])
......@@ -5747,8 +5747,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
""
"@
sll\\t%0,%c2
sll\\t%0,0(%2)"
sll\t%0,%c2
sll\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5765,8 +5765,8 @@
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode)"
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
sra\t%0,%c2
sra\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5779,8 +5779,8 @@
(clobber (match_scratch:SI 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
sra\t%0,%c2
sra\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5791,8 +5791,8 @@
(clobber (reg:CC 33))]
""
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
sra\t%0,%c2
sra\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -5818,8 +5818,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
"!TARGET_64BIT"
"@
srdl\\t%0,%c2
srdl\\t%0,0(%2)"
srdl\t%0,%c2
srdl\t%0,0(%2)"
[(set_attr "op_type" "RS,RS")
(set_attr "atype" "reg")])
......@@ -5829,8 +5829,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
"TARGET_64BIT"
"@
srlg\\t%0,%1,%c2
srlg\\t%0,%1,0(%2)"
srlg\t%0,%1,%c2
srlg\t%0,%1,0(%2)"
[(set_attr "op_type" "RSE,RSE")
(set_attr "atype" "reg")])
......@@ -5844,8 +5844,8 @@
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
""
"@
srl\\t%0,%c2
srl\\t%0,0(%2)"
srl\t%0,%c2
srl\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
......@@ -6030,9 +6030,9 @@
""
{
if (get_attr_length (insn) == 4)
return "j%C1\\t%l0";
return "j%C1\t%l0";
else if (TARGET_64BIT)
return "jg%C1\\t%l0";
return "jg%C1\t%l0";
else
abort ();
}
......@@ -6055,9 +6055,9 @@
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "b%C1r\\t%0";
return "b%C1r\t%0";
else
return "b%C1\\t%a0";
return "b%C1\t%a0";
}
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
......@@ -6079,9 +6079,9 @@
""
{
if (get_attr_length (insn) == 4)
return "j%D1\\t%l0";
return "j%D1\t%l0";
else if (TARGET_64BIT)
return "jg%D1\\t%l0";
return "jg%D1\t%l0";
else
abort ();
}
......@@ -6104,9 +6104,9 @@
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "b%D1r\\t%0";
return "b%D1r\t%0";
else
return "b%D1\\t%a0";
return "b%D1\t%a0";
}
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
......@@ -6121,7 +6121,7 @@
(define_insn "trap"
[(trap_if (const_int 1) (const_int 0))]
""
"j\\t.+2"
"j\t.+2"
[(set_attr "op_type" "RX")
(set_attr "type" "branch")])
......@@ -6146,7 +6146,7 @@
[(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
(const_int 0))]
""
"j%C0\\t.+2";
"j%C0\t.+2";
[(set_attr "op_type" "RI")
(set_attr "type" "branch")])
......@@ -6190,7 +6190,7 @@
if (which_alternative != 0)
return "#";
else if (get_attr_length (insn) == 4)
return "brct\\t%1,%l0";
return "brct\t%1,%l0";
else
abort ();
}
......@@ -6218,9 +6218,9 @@
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "bctr\\t%1,%0";
return "bctr\t%1,%0";
else
return "bct\\t%1,%a0";
return "bct\t%1,%a0";
}
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
......@@ -6268,7 +6268,7 @@
if (which_alternative != 0)
return "#";
else if (get_attr_length (insn) == 4)
return "brctg\\t%1,%l0";
return "brctg\t%1,%l0";
else
abort ();
}
......@@ -6292,9 +6292,9 @@
""
{
if (get_attr_op_type (insn) == OP_TYPE_RRE)
return "bctgr\\t%1,%0";
return "bctgr\t%1,%0";
else
return "bctg\\t%1,%a0";
return "bctg\t%1,%a0";
}
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
......@@ -6339,9 +6339,9 @@
""
{
if (get_attr_length (insn) == 4)
return "j\\t%l0";
return "j\t%l0";
else if (TARGET_64BIT)
return "jg\\t%l0";
return "jg\t%l0";
else
abort ();
}
......@@ -6364,9 +6364,9 @@
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "br\\t%0";
return "br\t%0";
else
return "b\\t%a0";
return "b\t%a0";
}
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
......@@ -6384,9 +6384,9 @@
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "br\\t%0";
return "br\t%0";
else
return "b\\t%a0";
return "b\t%a0";
}
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
......@@ -6538,7 +6538,7 @@
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT"
"brasl\\t%2,%0"
"brasl\t%2,%0"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
......@@ -6547,7 +6547,7 @@
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"TARGET_SMALL_EXEC"
"bras\\t%2,%0"
"bras\t%2,%0"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
......@@ -6556,7 +6556,7 @@
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT"
"basr\\t%2,%0"
"basr\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -6566,7 +6566,7 @@
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"!TARGET_64BIT"
"basr\\t%2,%0"
"basr\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -6576,7 +6576,7 @@
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT"
"bas\\t%2,%a0"
"bas\t%2,%a0"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")])
......@@ -6585,7 +6585,7 @@
(match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))]
"!TARGET_64BIT"
"bas\\t%2,%a0"
"bas\t%2,%a0"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")])
......@@ -6650,7 +6650,7 @@
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT"
"brasl\\t%3,%1"
"brasl\t%3,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
......@@ -6660,7 +6660,7 @@
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"TARGET_SMALL_EXEC"
"bras\\t%3,%1"
"bras\t%3,%1"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
......@@ -6670,7 +6670,7 @@
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT"
"basr\\t%3,%1"
"basr\t%3,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -6681,7 +6681,7 @@
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"!TARGET_64BIT"
"basr\\t%3,%1"
"basr\t%3,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -6692,7 +6692,7 @@
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT"
"bas\\t%3,%a1"
"bas\t%3,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")])
......@@ -6702,7 +6702,7 @@
(match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))]
"!TARGET_64BIT"
"bas\\t%3,%a1"
"bas\t%3,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")])
......@@ -6716,8 +6716,8 @@
(unspec:DI [(const_int 0)] UNSPEC_TP))]
"TARGET_64BIT"
"@
ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1
stam\\t%%a0,%%a1,%0"
ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1
stam\t%%a0,%%a1,%0"
[(set_attr "op_type" "NN,RS")
(set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
......@@ -6728,8 +6728,8 @@
(unspec:SI [(const_int 0)] UNSPEC_TP))]
"!TARGET_64BIT"
"@
ear\\t%0,%%a0
stam\\t%%a0,%%a0,%0"
ear\t%0,%%a0
stam\t%%a0,%%a0,%0"
[(set_attr "op_type" "RRE,RS")])
(define_insn "set_tp_64"
......@@ -6737,8 +6737,8 @@
(clobber (match_scratch:SI 1 "=d,X"))]
"TARGET_64BIT"
"@
sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1
lam\\t%%a0,%%a1,%0"
sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1
lam\t%%a0,%%a1,%0"
[(set_attr "op_type" "NN,RS")
(set_attr "atype" "reg,*")
(set_attr "type" "o3,*")
......@@ -6748,8 +6748,8 @@
[(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
"!TARGET_64BIT"
"@
sar\\t%%a0,%0
lam\\t%%a0,%%a0,%0"
sar\t%%a0,%0
lam\t%%a0,%%a0,%0"
[(set_attr "op_type" "RRE,RS")])
(define_insn "*tls_load_64"
......@@ -6758,7 +6758,7 @@
(match_operand:DI 2 "" "")]
UNSPEC_TLS_LOAD))]
"TARGET_64BIT"
"lg\\t%0,%1%J2"
"lg\t%0,%1%J2"
[(set_attr "op_type" "RXE")])
(define_insn "*tls_load_31"
......@@ -6768,8 +6768,8 @@
UNSPEC_TLS_LOAD))]
"!TARGET_64BIT"
"@
l\\t%0,%1%J2
ly\\t%0,%1%J2"
l\t%0,%1%J2
ly\t%0,%1%J2"
[(set_attr "op_type" "RX,RXY")])
(define_expand "call_value_tls"
......@@ -6830,7 +6830,7 @@
(clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))]
"TARGET_64BIT"
"brasl\\t%3,%1%J4"
"brasl\t%3,%1%J4"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
......@@ -6841,7 +6841,7 @@
(clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))]
"TARGET_SMALL_EXEC"
"bras\\t%3,%1%J4"
"bras\t%3,%1%J4"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
......@@ -6852,7 +6852,7 @@
(clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))]
"TARGET_64BIT"
"basr\\t%3,%1%J4"
"basr\t%3,%1%J4"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")])
......@@ -6863,7 +6863,7 @@
(clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))]
"!TARGET_64BIT"
"basr\\t%3,%1%J4"
"basr\t%3,%1%J4"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -6875,7 +6875,7 @@
(clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))]
"TARGET_64BIT"
"bas\\t%3,%a1%J4"
"bas\t%3,%a1%J4"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -6887,7 +6887,7 @@
(clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))]
"!TARGET_64BIT"
"bas\\t%3,%a1%J4"
"bas\t%3,%a1%J4"
[(set_attr "op_type" "RX")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -7050,7 +7050,7 @@
(define_insn "nop"
[(const_int 0)]
""
"lr\\t0,0"
"lr\t0,0"
[(set_attr "op_type" "RR")])
......@@ -7144,21 +7144,21 @@
(define_insn "pool_start_31"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
"!TARGET_64BIT"
".align\\t4"
".align\t4"
[(set_attr "op_type" "NN")
(set_attr "length" "2")])
(define_insn "pool_end_31"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
"!TARGET_64BIT"
".align\\t2"
".align\t2"
[(set_attr "op_type" "NN")
(set_attr "length" "2")])
(define_insn "pool_start_64"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
"TARGET_64BIT"
".section\\t.rodata\;.align\\t8"
".section\t.rodata\;.align\t8"
[(set_attr "op_type" "NN")
(set_attr "length" "0")])
......@@ -7173,7 +7173,7 @@
[(set (match_operand:SI 0 "register_operand" "=a")
(unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
"!TARGET_64BIT"
"basr\\t%0,0\;la\\t%0,%1-.(%0)"
"basr\t%0,0\;la\t%0,%1-.(%0)"
[(set_attr "op_type" "NN")
(set_attr "type" "la")
(set_attr "length" "6")])
......@@ -7182,7 +7182,7 @@
[(set (match_operand:DI 0 "register_operand" "=a")
(unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
"TARGET_64BIT"
"larl\\t%0,%1"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")])
......@@ -7213,7 +7213,7 @@
[(return)
(use (match_operand:SI 0 "register_operand" "a"))]
"!TARGET_64BIT"
"br\\t%0"
"br\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -7222,7 +7222,7 @@
[(return)
(use (match_operand:DI 0 "register_operand" "a"))]
"TARGET_64BIT"
"br\\t%0"
"br\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
......@@ -7236,7 +7236,7 @@
{
if (s390_nr_constants)
{
output_asm_insn ("bras\\t%0,%2", operands);
output_asm_insn ("bras\t%0,%2", operands);
s390_output_constant_pool (operands[1], operands[2]);
}
else if (flag_pic)
......@@ -7260,7 +7260,7 @@
{
if (s390_nr_constants)
{
output_asm_insn ("larl\\t%0,%1", operands);
output_asm_insn ("larl\t%0,%1", operands);
s390_output_constant_pool (operands[1], operands[2]);
}
......
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