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riscv-gcc-1
Commit d3632d41 by Ulrich Weigand Committed by Ulrich Weigand
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s390.c (s390_extra_constraint): New function. 

	* config/s390/s390.c (s390_extra_constraint): New function.
	* config/s390/s390-protos.h (s390_extra_constraint): Declare it.
	* config/s390/s390.h (EXTRA_CONSTRAINT): Use it.
	* config/s390/s390.c (q_constraint): Remove.
	* config/s390/s390-protos.h (q_constraint): Likewise.
	* config/s390/s390.h (EXTRA_MEMORY_CONSTRAINT): Add 'R', 'S', 'T'.
	(EXTRA_ADDRESS_CONSTRAINT): Define.

	* config/s390/s390.c (larl_operand): Refuse out-of-range operands.
	(DISP_IN_RANGE, s390_short_displacement): New.
	(legitimate_reload_operand_p): Support long displacements.
	(s390_decompose_address): Likewise.
	(legitimize_pic_address): Likewise.
	(legitimize_address): Likewise.
	(s390_fixup_clobbered_return_reg): Likewise.
	(s390_emit_prologue, s390_emit_epilogue): Likewise.
	(s390_output_mi_thunk): Likewise.

	* config/s390/s390.md (attr "op_type"): Add "RXY", "RSY", "SIY".
	(attr "atype", attr "length"): Add defaults for new op_types.
	(all insns): Change op_type attribute where appropriate.

	("*movdi_lay", "*movsi_lay", "*extendqidi2", "*extendqisi2"): New insns.
	("*tmqi_ext", "*tmdi_mem", "*tmsi_mem", "*tmhi_mem", *tmqi_mem",
	"*tstsi", "*tstsi_cconly", "*tsthiCCT", "*tsthiCCT_cconly",
	"*tsthi", "*tsthi_cconly", "*tstqiCCT", "*tstqiCCT_cconly",
	"*tstqi", "*tstqi_cconly", "*cmpsi_ccs_sign", "*cmpsi_ccs",
	"*cmpsi_ccu", "*cmphi_ccu", "*cmpqi_ccu", "*cli",
	"movti", "*movdi_64", "*movdi_31", "*movsi", "movhi", "movqi_64",
	"movqi", "*movstrictqi", "*movstricthi", "movstrictsi",
	"*movdf_64", "*movdf_31", "*movsf",
	"*load_multiple_si", "*store_multiple_di",
	"*sethighqisi", "*sethighhisi", "*sethighqidi_31", "*extendhisi2",
	"*la_64", "*la_31", "*la_31_and", "force_la_31",
	"*addsi3_carry1_cc", *addsi3_carry1_cconly",
	"*addsi3_carry2_cc", *addsi3_carry2_cconly",
	"*addsi3_cc", "*addsi3_cconly", "*addsi3_cconly2",
	"*addsi3_sign", "*addsi3_sub", "addsi3",
	"*subsi3_borrow_cc", "*subsi3_borrow_cconly", "*subsi3_cc",
	"*subsi3_cconly", "*subsi3_sign", "*subsi3_sub", "subsi3",
	"mulsi3"
	"*andsi3_cc", "*andsi3_cconly", "andsi3",
	"*andqi3_ss", "*andqi3_ss_inv",
	"*iorsi3_cc", "*iorsi3_cconly", "iorsi3",
	"*iorqi3_ss", "*iorqi3_ss_inv",
	"*xorsi3_cc", "*xorsi3_cconly", "xorsi3",
	"*xorqi3_ss", "*xorqi3_ss_inv",
	"*tls_load_31"): Add alternatives for long-displacement instructions.

	("*cmpdf_ccs", "*cmpdf_ccs_ibm", "*cmpsf_ccs", "*cmpsf_ccs_ibm",
	"*load_multiple_di", "*store_multiple_di",
	"*sethighqidi_64", "*zero_extendhisi2_31",
	"truncdfsf2_ibm", "extendsfdf2_ieee", "extendsfdf2_ibm",
	"adddf3", "*adddf3", "*adddf3_ibm",
	"addsf3", "*addsf3", "*addsf3_ibm",
	"subdf3", "*subdf3", "*subdf3_ibm",
	"subsf3", "*subsf3", "*subsf3_ibm",
	"mulsi_6432", "divmoddisi3",
	"muldf3", "*muldf3", "*muldf3_ibm",
	"mulsf3", "*mulsf3", "*mulsf3_ibm",
	"divdf3", "*divdf3", "*divdf3_ibm",
	"divsf3", "div*sf3", "*divsf3_ibm",
	"sqrtdf2", "sqrtsf2",
	"*cjump_long", "*icjump_long", "indirect_jump", "casesi_jump",
	"*doloop_si_long", "*doloop_di_long", "bas_64", "bas_31",
	"bas_r_64", "bas_r_31", "bas_tls_31", "bas_tls_64"): Adapt memory
	and address constraints for instructions that do not accept long
	displacements.

From-SVN: r68744
parent 52609473
Showing with 838 additions and 491 deletions
gcc/ChangeLog
2003-06-30 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.c (s390_extra_constraint): New function.
* config/s390/s390-protos.h (s390_extra_constraint): Declare it.
* config/s390/s390.h (EXTRA_CONSTRAINT): Use it.
* config/s390/s390.c (q_constraint): Remove.
* config/s390/s390-protos.h (q_constraint): Likewise.
* config/s390/s390.h (EXTRA_MEMORY_CONSTRAINT): Add 'R', 'S', 'T'.
(EXTRA_ADDRESS_CONSTRAINT): Define.
* config/s390/s390.c (larl_operand): Refuse out-of-range operands.
(DISP_IN_RANGE, s390_short_displacement): New.
(legitimate_reload_operand_p): Support long displacements.
(s390_decompose_address): Likewise.
(legitimize_pic_address): Likewise.
(legitimize_address): Likewise.
(s390_fixup_clobbered_return_reg): Likewise.
(s390_emit_prologue, s390_emit_epilogue): Likewise.
(s390_output_mi_thunk): Likewise.
* config/s390/s390.md (attr "op_type"): Add "RXY", "RSY", "SIY".
(attr "atype", attr "length"): Add defaults for new op_types.
(all insns): Change op_type attribute where appropriate.
("*movdi_lay", "*movsi_lay", "*extendqidi2", "*extendqisi2"): New insns.
("*tmqi_ext", "*tmdi_mem", "*tmsi_mem", "*tmhi_mem", *tmqi_mem",
"*tstsi", "*tstsi_cconly", "*tsthiCCT", "*tsthiCCT_cconly",
"*tsthi", "*tsthi_cconly", "*tstqiCCT", "*tstqiCCT_cconly",
"*tstqi", "*tstqi_cconly", "*cmpsi_ccs_sign", "*cmpsi_ccs",
"*cmpsi_ccu", "*cmphi_ccu", "*cmpqi_ccu", "*cli",
"movti", "*movdi_64", "*movdi_31", "*movsi", "movhi", "movqi_64",
"movqi", "*movstrictqi", "*movstricthi", "movstrictsi",
"*movdf_64", "*movdf_31", "*movsf",
"*load_multiple_si", "*store_multiple_di",
"*sethighqisi", "*sethighhisi", "*sethighqidi_31", "*extendhisi2",
"*la_64", "*la_31", "*la_31_and", "force_la_31",
"*addsi3_carry1_cc", *addsi3_carry1_cconly",
"*addsi3_carry2_cc", *addsi3_carry2_cconly",
"*addsi3_cc", "*addsi3_cconly", "*addsi3_cconly2",
"*addsi3_sign", "*addsi3_sub", "addsi3",
"*subsi3_borrow_cc", "*subsi3_borrow_cconly", "*subsi3_cc",
"*subsi3_cconly", "*subsi3_sign", "*subsi3_sub", "subsi3",
"mulsi3"
"*andsi3_cc", "*andsi3_cconly", "andsi3",
"*andqi3_ss", "*andqi3_ss_inv",
"*iorsi3_cc", "*iorsi3_cconly", "iorsi3",
"*iorqi3_ss", "*iorqi3_ss_inv",
"*xorsi3_cc", "*xorsi3_cconly", "xorsi3",
"*xorqi3_ss", "*xorqi3_ss_inv",
"*tls_load_31"): Add alternatives for long-displacement instructions.
("*cmpdf_ccs", "*cmpdf_ccs_ibm", "*cmpsf_ccs", "*cmpsf_ccs_ibm",
"*load_multiple_di", "*store_multiple_di",
"*sethighqidi_64", "*zero_extendhisi2_31",
"truncdfsf2_ibm", "extendsfdf2_ieee", "extendsfdf2_ibm",
"adddf3", "*adddf3", "*adddf3_ibm",
"addsf3", "*addsf3", "*addsf3_ibm",
"subdf3", "*subdf3", "*subdf3_ibm",
"subsf3", "*subsf3", "*subsf3_ibm",
"mulsi_6432", "divmoddisi3",
"muldf3", "*muldf3", "*muldf3_ibm",
"mulsf3", "*mulsf3", "*mulsf3_ibm",
"divdf3", "*divdf3", "*divdf3_ibm",
"divsf3", "div*sf3", "*divsf3_ibm",
"sqrtdf2", "sqrtsf2",
"*cjump_long", "*icjump_long", "indirect_jump", "casesi_jump",
"*doloop_si_long", "*doloop_di_long", "bas_64", "bas_31",
"bas_r_64", "bas_r_31", "bas_tls_31", "bas_tls_64"): Adapt memory
and address constraints for instructions that do not accept long
displacements.
2003-06-30 Hartmut Penner <hpenner@de.ibm.com> 2003-06-30 Hartmut Penner <hpenner@de.ibm.com>
Ulrich Weigand <uweigand@de.ibm.com> Ulrich Weigand <uweigand@de.ibm.com>
......
gcc/config/s390/s390-protos.h
...@@ -29,7 +29,7 @@ extern void s390_emit_epilogue PARAMS ((void)); ...@@ -29,7 +29,7 @@ extern void s390_emit_epilogue PARAMS ((void));
extern void s390_function_profiler PARAMS ((FILE *, int)); extern void s390_function_profiler PARAMS ((FILE *, int));
#ifdef RTX_CODE #ifdef RTX_CODE
extern int q_constraint PARAMS ((rtx)); extern int s390_extra_constraint PARAMS ((rtx, int));
extern int const0_operand PARAMS ((rtx, enum machine_mode)); extern int const0_operand PARAMS ((rtx, enum machine_mode));
extern int consttable_operand PARAMS ((rtx, enum machine_mode)); extern int consttable_operand PARAMS ((rtx, enum machine_mode));
extern int larl_operand PARAMS ((rtx, enum machine_mode)); extern int larl_operand PARAMS ((rtx, enum machine_mode));
......
gcc/config/s390/s390.c
...@@ -204,6 +204,7 @@ static int s390_branch_condition_mask PARAMS ((rtx)); ...@@ -204,6 +204,7 @@ static int s390_branch_condition_mask PARAMS ((rtx));
static const char *s390_branch_condition_mnemonic PARAMS ((rtx, int)); static const char *s390_branch_condition_mnemonic PARAMS ((rtx, int));
static int check_mode PARAMS ((rtx, enum machine_mode *)); static int check_mode PARAMS ((rtx, enum machine_mode *));
static int general_s_operand PARAMS ((rtx, enum machine_mode, int)); static int general_s_operand PARAMS ((rtx, enum machine_mode, int));
static int s390_short_displacement PARAMS ((rtx));
static int s390_decompose_address PARAMS ((rtx, struct s390_address *)); static int s390_decompose_address PARAMS ((rtx, struct s390_address *));
static rtx get_thread_pointer PARAMS ((void)); static rtx get_thread_pointer PARAMS ((void));
static rtx legitimize_tls_address PARAMS ((rtx, rtx)); static rtx legitimize_tls_address PARAMS ((rtx, rtx));
...@@ -228,6 +229,11 @@ static rtx restore_gprs PARAMS ((rtx, int, int, int)); ...@@ -228,6 +229,11 @@ static rtx restore_gprs PARAMS ((rtx, int, int, int));
static int s390_function_arg_size PARAMS ((enum machine_mode, tree)); static int s390_function_arg_size PARAMS ((enum machine_mode, tree));
static bool s390_function_arg_float PARAMS ((enum machine_mode, tree)); static bool s390_function_arg_float PARAMS ((enum machine_mode, tree));
static struct machine_function * s390_init_machine_status PARAMS ((void)); static struct machine_function * s390_init_machine_status PARAMS ((void));
/* Check whether integer displacement is in range. */
#define DISP_IN_RANGE(d) \
(TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
: ((d) >= 0 && (d) <= 4095))
/* Return true if SET either doesn't set the CC register, or else /* Return true if SET either doesn't set the CC register, or else
the source and destination have matching CC modes and that the source and destination have matching CC modes and that
...@@ -1103,12 +1109,17 @@ larl_operand (op, mode) ...@@ -1103,12 +1109,17 @@ larl_operand (op, mode)
return 0; return 0;
op = XEXP (op, 0); op = XEXP (op, 0);
/* Allow adding *even* constants. */ /* Allow adding *even* in-range constants. */
if (GET_CODE (op) == PLUS) if (GET_CODE (op) == PLUS)
{ {
if (GET_CODE (XEXP (op, 1)) != CONST_INT if (GET_CODE (XEXP (op, 1)) != CONST_INT
|| (INTVAL (XEXP (op, 1)) & 1) != 0) || (INTVAL (XEXP (op, 1)) & 1) != 0)
return 0; return 0;
#if HOST_BITS_PER_WIDE_INT > 32
if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
|| INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
return 0;
#endif
op = XEXP (op, 0); op = XEXP (op, 0);
} }
...@@ -1221,24 +1232,121 @@ s_imm_operand (op, mode) ...@@ -1221,24 +1232,121 @@ s_imm_operand (op, mode)
return general_s_operand (op, mode, 1); return general_s_operand (op, mode, 1);
} }
/* Return true if OP is a valid operand for a 'Q' constraint. /* Return true if DISP is a valid short displacement. */
This differs from s_operand in that only memory operands
without index register are accepted, nothing else. */ static int
s390_short_displacement (disp)
rtx disp;
{
/* No displacement is OK. */
if (!disp)
return 1;
/* Integer displacement in range. */
if (GET_CODE (disp) == CONST_INT)
return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
/* GOT offset is not OK, the GOT can be large. */
if (GET_CODE (disp) == CONST
&& GET_CODE (XEXP (disp, 0)) == UNSPEC
&& XINT (XEXP (disp, 0), 1) == 110)
return 0;
/* All other symbolic constants are literal pool references,
which are OK as the literal pool must be small. */
if (GET_CODE (disp) == CONST)
return 1;
return 0;
}
/* Return true if OP is a valid operand for a C constraint. */
int int
q_constraint (op) s390_extra_constraint (op, c)
register rtx op; rtx op;
int c;
{ {
struct s390_address addr; struct s390_address addr;
if (GET_CODE (op) != MEM) switch (c)
return 0; {
case 'Q':
if (GET_CODE (op) != MEM)
return 0;
if (!s390_decompose_address (XEXP (op, 0), &addr))
return 0;
if (addr.indx)
return 0;
if (!s390_decompose_address (XEXP (op, 0), &addr)) if (TARGET_LONG_DISPLACEMENT)
return 0; {
if (!s390_short_displacement (addr.disp))
return 0;
}
break;
if (addr.indx) case 'R':
return 0; if (GET_CODE (op) != MEM)
return 0;
if (TARGET_LONG_DISPLACEMENT)
{
if (!s390_decompose_address (XEXP (op, 0), &addr))
return 0;
if (!s390_short_displacement (addr.disp))
return 0;
}
break;
case 'S':
if (!TARGET_LONG_DISPLACEMENT)
return 0;
if (GET_CODE (op) != MEM)
return 0;
if (!s390_decompose_address (XEXP (op, 0), &addr))
return 0;
if (addr.indx)
return 0;
if (s390_short_displacement (addr.disp))
return 0;
break;
case 'T':
if (!TARGET_LONG_DISPLACEMENT)
return 0;
if (GET_CODE (op) != MEM)
return 0;
/* Any invalid address here will be fixed up by reload,
so accept it for the most generic constraint. */
if (s390_decompose_address (XEXP (op, 0), &addr)
&& s390_short_displacement (addr.disp))
return 0;
break;
case 'U':
if (TARGET_LONG_DISPLACEMENT)
{
if (!s390_decompose_address (op, &addr))
return 0;
if (!s390_short_displacement (addr.disp))
return 0;
}
break;
case 'W':
if (!TARGET_LONG_DISPLACEMENT)
return 0;
/* Any invalid address here will be fixed up by reload,
so accept it for the most generic constraint. */
if (s390_decompose_address (op, &addr)
&& s390_short_displacement (addr.disp))
return 0;
break;
default:
return 0;
}
return 1; return 1;
} }
...@@ -1673,6 +1781,11 @@ int ...@@ -1673,6 +1781,11 @@ int
legitimate_reload_constant_p (op) legitimate_reload_constant_p (op)
register rtx op; register rtx op;
{ {
/* Accept la(y) operands. */
if (GET_CODE (op) == CONST_INT
&& DISP_IN_RANGE (INTVAL (op)))
return 1;
/* Accept l(g)hi operands. */ /* Accept l(g)hi operands. */
if (GET_CODE (op) == CONST_INT if (GET_CODE (op) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')) && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
...@@ -2016,7 +2129,7 @@ s390_decompose_address (addr, out) ...@@ -2016,7 +2129,7 @@ s390_decompose_address (addr, out)
this is fixed up by reload in any case. */ this is fixed up by reload in any case. */
if (base != arg_pointer_rtx && indx != arg_pointer_rtx) if (base != arg_pointer_rtx && indx != arg_pointer_rtx)
{ {
if (INTVAL (disp) < 0 || INTVAL (disp) >= 4096) if (!DISP_IN_RANGE (INTVAL (disp)))
return FALSE; return FALSE;
} }
} }
...@@ -2395,7 +2508,7 @@ legitimize_pic_address (orig, reg) ...@@ -2395,7 +2508,7 @@ legitimize_pic_address (orig, reg)
pair of LARL and LA. */ pair of LARL and LA. */
rtx temp = reg? reg : gen_reg_rtx (Pmode); rtx temp = reg? reg : gen_reg_rtx (Pmode);
if (INTVAL (op1) < 0 || INTVAL (op1) >= 4096) if (!DISP_IN_RANGE (INTVAL (op1)))
{ {
int even = INTVAL (op1) - 1; int even = INTVAL (op1) - 1;
op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even)); op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
...@@ -2766,8 +2879,8 @@ legitimize_address (x, oldx, mode) ...@@ -2766,8 +2879,8 @@ legitimize_address (x, oldx, mode)
change later anyway. */ change later anyway. */
if (GET_CODE (constant_term) == CONST_INT if (GET_CODE (constant_term) == CONST_INT
&& (INTVAL (constant_term) < 0 && !TARGET_LONG_DISPLACEMENT
|| INTVAL (constant_term) >= 4096) && !DISP_IN_RANGE (INTVAL (constant_term))
&& !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x)))) && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
{ {
HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff; HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
...@@ -5050,7 +5163,7 @@ s390_fixup_clobbered_return_reg (return_reg) ...@@ -5050,7 +5163,7 @@ s390_fixup_clobbered_return_reg (return_reg)
reg = stack_pointer_rtx; reg = stack_pointer_rtx;
off = GEN_INT (cfun->machine->frame_size + REGNO (return_reg) * UNITS_PER_WORD); off = GEN_INT (cfun->machine->frame_size + REGNO (return_reg) * UNITS_PER_WORD);
if (INTVAL (off) >= 4096) if (!DISP_IN_RANGE (INTVAL (off)))
{ {
off = force_const_mem (Pmode, off); off = force_const_mem (Pmode, off);
new_insn = gen_rtx_SET (Pmode, return_reg, off); new_insn = gen_rtx_SET (Pmode, return_reg, off);
...@@ -5534,11 +5647,21 @@ s390_emit_prologue () ...@@ -5534,11 +5647,21 @@ s390_emit_prologue ()
/* Substract frame size from stack pointer. */ /* Substract frame size from stack pointer. */
frame_off = GEN_INT (-cfun->machine->frame_size); if (DISP_IN_RANGE (INTVAL (frame_off)))
if (!CONST_OK_FOR_LETTER_P (-cfun->machine->frame_size, 'K')) {
frame_off = force_const_mem (Pmode, frame_off); insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
gen_rtx_PLUS (Pmode, stack_pointer_rtx,
frame_off));
insn = emit_insn (insn);
}
else
{
if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
frame_off = force_const_mem (Pmode, frame_off);
insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
}
insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
RTX_FRAME_RELATED_P (insn) = 1; RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
...@@ -5697,8 +5820,8 @@ s390_emit_epilogue () ...@@ -5697,8 +5820,8 @@ s390_emit_epilogue ()
{ {
/* Nothing to restore. */ /* Nothing to restore. */
} }
else if (cfun->machine->frame_size + area_bottom >= 0 else if (DISP_IN_RANGE (cfun->machine->frame_size + area_bottom)
&& cfun->machine->frame_size + area_top <= 4096) && DISP_IN_RANGE (cfun->machine->frame_size + area_top-1))
{ {
/* Area is in range. */ /* Area is in range. */
offset = cfun->machine->frame_size; offset = cfun->machine->frame_size;
...@@ -5710,10 +5833,19 @@ s390_emit_epilogue () ...@@ -5710,10 +5833,19 @@ s390_emit_epilogue ()
offset = area_bottom < 0 ? -area_bottom : 0; offset = area_bottom < 0 ? -area_bottom : 0;
frame_off = GEN_INT (cfun->machine->frame_size - offset); frame_off = GEN_INT (cfun->machine->frame_size - offset);
if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K')) if (DISP_IN_RANGE (INTVAL (frame_off)))
frame_off = force_const_mem (Pmode, frame_off); {
insn = gen_rtx_SET (VOIDmode, frame_pointer,
gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
insn = emit_insn (insn);
}
else
{
if (!CONST_OK_FOR_LETTER_P (INTVAL (frame_off), 'K'))
frame_off = force_const_mem (Pmode, frame_off);
insn = emit_insn (gen_add2_insn (frame_pointer, frame_off)); insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
}
} }
/* Restore call saved fprs. */ /* Restore call saved fprs. */
...@@ -6649,8 +6781,10 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6649,8 +6781,10 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
if (TARGET_64BIT) if (TARGET_64BIT)
{ {
/* Setup literal pool pointer if required. */ /* Setup literal pool pointer if required. */
if (!CONST_OK_FOR_LETTER_P (delta, 'K') if ((!DISP_IN_RANGE (delta)
|| !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')) && !CONST_OK_FOR_LETTER_P (delta, 'K'))
|| (!DISP_IN_RANGE (vcall_offset)
&& !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{ {
op[5] = gen_label_rtx (); op[5] = gen_label_rtx ();
output_asm_insn ("larl\t%4,%5", op); output_asm_insn ("larl\t%4,%5", op);
...@@ -6661,6 +6795,8 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6661,6 +6795,8 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
{ {
if (CONST_OK_FOR_LETTER_P (delta, 'J')) if (CONST_OK_FOR_LETTER_P (delta, 'J'))
output_asm_insn ("la\t%1,%2(%1)", op); output_asm_insn ("la\t%1,%2(%1)", op);
else if (DISP_IN_RANGE (delta))
output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_LETTER_P (delta, 'K')) else if (CONST_OK_FOR_LETTER_P (delta, 'K'))
output_asm_insn ("aghi\t%1,%2", op); output_asm_insn ("aghi\t%1,%2", op);
else else
...@@ -6673,7 +6809,7 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6673,7 +6809,7 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
/* Perform vcall adjustment. */ /* Perform vcall adjustment. */
if (vcall_offset) if (vcall_offset)
{ {
if (CONST_OK_FOR_LETTER_P (vcall_offset, 'J')) if (DISP_IN_RANGE (vcall_offset))
{ {
output_asm_insn ("lg\t%4,0(%1)", op); output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("ag\t%1,%3(%4)", op); output_asm_insn ("ag\t%1,%3(%4)", op);
...@@ -6720,8 +6856,10 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6720,8 +6856,10 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
{ {
/* Setup base pointer if required. */ /* Setup base pointer if required. */
if (!vcall_offset if (!vcall_offset
|| !CONST_OK_FOR_LETTER_P (delta, 'K') || (!DISP_IN_RANGE (delta)
|| !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')) && !CONST_OK_FOR_LETTER_P (delta, 'K'))
|| (!DISP_IN_RANGE (delta)
&& !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{ {
op[5] = gen_label_rtx (); op[5] = gen_label_rtx ();
output_asm_insn ("basr\t%4,0", op); output_asm_insn ("basr\t%4,0", op);
...@@ -6734,6 +6872,8 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6734,6 +6872,8 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
{ {
if (CONST_OK_FOR_LETTER_P (delta, 'J')) if (CONST_OK_FOR_LETTER_P (delta, 'J'))
output_asm_insn ("la\t%1,%2(%1)", op); output_asm_insn ("la\t%1,%2(%1)", op);
else if (DISP_IN_RANGE (delta))
output_asm_insn ("lay\t%1,%2(%1)", op);
else if (CONST_OK_FOR_LETTER_P (delta, 'K')) else if (CONST_OK_FOR_LETTER_P (delta, 'K'))
output_asm_insn ("ahi\t%1,%2", op); output_asm_insn ("ahi\t%1,%2", op);
else else
...@@ -6751,6 +6891,11 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6751,6 +6891,11 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
output_asm_insn ("lg\t%4,0(%1)", op); output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("a\t%1,%3(%4)", op); output_asm_insn ("a\t%1,%3(%4)", op);
} }
else if (DISP_IN_RANGE (vcall_offset))
{
output_asm_insn ("lg\t%4,0(%1)", op);
output_asm_insn ("ay\t%1,%3(%4)", op);
}
else if (CONST_OK_FOR_LETTER_P (vcall_offset, 'K')) else if (CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))
{ {
output_asm_insn ("lhi\t%4,%3", op); output_asm_insn ("lhi\t%4,%3", op);
......
gcc/config/s390/s390.h
...@@ -530,10 +530,11 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; ...@@ -530,10 +530,11 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
#define EXTRA_CONSTRAINT(OP, C) \ #define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? q_constraint (OP) : \ s390_extra_constraint ((OP), (C))
(C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0) #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T')
#define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'Q') #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
((C) == 'U' || (C) == 'W')
/* Stack layout and calling conventions. */ /* Stack layout and calling conventions. */
......
gcc/config/s390/s390.md
...@@ -94,7 +94,7 @@ ...@@ -94,7 +94,7 @@
;; Operand type. Used to default length attribute values ;; Operand type. Used to default length attribute values
(define_attr "op_type" (define_attr "op_type"
"NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE" "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
(const_string "RX")) (const_string "RX"))
;; Insn are devide in two classes: ;; Insn are devide in two classes:
...@@ -115,7 +115,10 @@ ...@@ -115,7 +115,10 @@
(eq_attr "op_type" "SSE") (const_string "agen") (eq_attr "op_type" "SSE") (const_string "agen")
(eq_attr "op_type" "RXE") (const_string "agen") (eq_attr "op_type" "RXE") (const_string "agen")
(eq_attr "op_type" "RSE") (const_string "agen") (eq_attr "op_type" "RSE") (const_string "agen")
(eq_attr "op_type" "RIL") (const_string "agen")] (eq_attr "op_type" "RIL") (const_string "agen")
(eq_attr "op_type" "RXY") (const_string "agen")
(eq_attr "op_type" "RSY") (const_string "agen")
(eq_attr "op_type" "SIY") (const_string "agen")]
(const_string "reg"))) (const_string "reg")))
;; Generic pipeline function unit. ;; Generic pipeline function unit.
...@@ -237,7 +240,10 @@ ...@@ -237,7 +240,10 @@
(eq_attr "op_type" "SSE") (const_int 6) (eq_attr "op_type" "SSE") (const_int 6)
(eq_attr "op_type" "RXE") (const_int 6) (eq_attr "op_type" "RXE") (const_int 6)
(eq_attr "op_type" "RSE") (const_int 6) (eq_attr "op_type" "RSE") (const_int 6)
(eq_attr "op_type" "RIL") (const_int 6)] (eq_attr "op_type" "RIL") (const_int 6)
(eq_attr "op_type" "RXY") (const_int 6)
(eq_attr "op_type" "RSY") (const_int 6)
(eq_attr "op_type" "SIY") (const_int 6)]
(const_int 4))) (const_int 4)))
;; Define attributes for `asm' insns. ;; Define attributes for `asm' insns.
...@@ -378,9 +384,9 @@ ...@@ -378,9 +384,9 @@
(define_insn "*tmqi_ext" (define_insn "*tmqi_ext"
[(set (reg 33) [(set (reg 33)
(compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q") (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
(match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 1 "const_int_operand" "n,n")
(match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))] (const_int 0)))]
"s390_match_ccmode(insn, CCTmode) "s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
...@@ -391,17 +397,17 @@ ...@@ -391,17 +397,17 @@
int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
operands[2] = GEN_INT (block << shift); operands[2] = GEN_INT (block << shift);
return \"tm\\t%0,%b2\"; return which_alternative == 0 ? \"tm\\t%0,%b2\" : \"tmy\\t%0,%b2\";
}" }"
[(set_attr "op_type" "SI")]) [(set_attr "op_type" "SI,SIY")])
; Test-under-Mask instructions ; Test-under-Mask instructions
(define_insn "*tmdi_mem" (define_insn "*tmdi_mem"
[(set (reg 33) [(set (reg 33)
(compare (and:DI (match_operand:DI 0 "memory_operand" "Q") (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
(match_operand:DI 1 "immediate_operand" "n")) (match_operand:DI 1 "immediate_operand" "n,n"))
(match_operand:DI 2 "immediate_operand" "n")))] (match_operand:DI 2 "immediate_operand" "n,n")))]
"TARGET_64BIT "TARGET_64BIT
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], DImode, 0) >= 0" && s390_single_qi (operands[1], DImode, 0) >= 0"
...@@ -412,15 +418,15 @@ ...@@ -412,15 +418,15 @@
operands[0] = gen_rtx_MEM (QImode, operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part)); plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\"; return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}" }"
[(set_attr "op_type" "SI")]) [(set_attr "op_type" "SI,SIY")])
(define_insn "*tmsi_mem" (define_insn "*tmsi_mem"
[(set (reg 33) [(set (reg 33)
(compare (and:SI (match_operand:SI 0 "memory_operand" "Q") (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S")
(match_operand:SI 1 "immediate_operand" "n")) (match_operand:SI 1 "immediate_operand" "n,n"))
(match_operand:SI 2 "immediate_operand" "n")))] (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], SImode, 0) >= 0" && s390_single_qi (operands[1], SImode, 0) >= 0"
"* "*
...@@ -430,15 +436,15 @@ ...@@ -430,15 +436,15 @@
operands[0] = gen_rtx_MEM (QImode, operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part)); plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\"; return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}" }"
[(set_attr "op_type" "SI")]) [(set_attr "op_type" "SI")])
(define_insn "*tmhi_mem" (define_insn "*tmhi_mem"
[(set (reg 33) [(set (reg 33)
(compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0) (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0)
(match_operand:SI 1 "immediate_operand" "n")) (match_operand:SI 1 "immediate_operand" "n,n"))
(match_operand:SI 2 "immediate_operand" "n")))] (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], HImode, 0) >= 0" && s390_single_qi (operands[1], HImode, 0) >= 0"
"* "*
...@@ -448,18 +454,20 @@ ...@@ -448,18 +454,20 @@
operands[0] = gen_rtx_MEM (QImode, operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part)); plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\"; return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}" }"
[(set_attr "op_type" "SI")]) [(set_attr "op_type" "SI")])
(define_insn "*tmqi_mem" (define_insn "*tmqi_mem"
[(set (reg 33) [(set (reg 33)
(compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0) (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0)
(match_operand:SI 1 "immediate_operand" "n")) (match_operand:SI 1 "immediate_operand" "n,n"))
(match_operand:SI 2 "immediate_operand" "n")))] (match_operand:SI 2 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"tm\\t%0,%b1" "@
[(set_attr "op_type" "SI")]) tm\\t%0,%b1
tmy\\t%0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*tmdi_reg" (define_insn "*tmdi_reg"
[(set (reg 33) [(set (reg 33)
...@@ -566,26 +574,28 @@ ...@@ -566,26 +574,28 @@
(define_insn "*tstsi" (define_insn "*tstsi"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q") (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" ""))) (match_operand:SI 1 "const0_operand" "")))
(set (match_operand:SI 2 "register_operand" "=d,d") (set (match_operand:SI 2 "register_operand" "=d,d,d")
(match_dup 0))] (match_dup 0))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"@ "@
ltr\\t%2,%0 ltr\\t%2,%0
icm\\t%2,15,%0" icm\\t%2,15,%0
[(set_attr "op_type" "RR,RS")]) icmy\\t%2,15,%0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly" (define_insn "*tstsi_cconly"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SI 0 "nonimmediate_operand" "d,Q") (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
(match_operand:SI 1 "const0_operand" ""))) (match_operand:SI 1 "const0_operand" "")))
(clobber (match_scratch:SI 2 "=X,d"))] (clobber (match_scratch:SI 2 "=X,d,d"))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"@ "@
ltr\\t%0,%0 ltr\\t%0,%0
icm\\t%2,15,%0" icm\\t%2,15,%0
[(set_attr "op_type" "RR,RS")]) icmy\\t%2,15,%0"
[(set_attr "op_type" "RR,RS,RSY")])
(define_insn "*tstsi_cconly2" (define_insn "*tstsi_cconly2"
[(set (reg 33) [(set (reg 33)
...@@ -597,86 +607,99 @@ ...@@ -597,86 +607,99 @@
(define_insn "*tsthiCCT" (define_insn "*tsthiCCT"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d") (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:HI 1 "const0_operand" ""))) (match_operand:HI 1 "const0_operand" "")))
(set (match_operand:HI 2 "register_operand" "=d,0") (set (match_operand:HI 2 "register_operand" "=d,d,0")
(match_dup 0))] (match_dup 0))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
icm\\t%2,3,%0 icm\\t%2,3,%0
icmy\\t%2,3,%0
tml\\t%0,65535" tml\\t%0,65535"
[(set_attr "op_type" "RS,RI")]) [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthiCCT_cconly" (define_insn "*tsthiCCT_cconly"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:HI 0 "nonimmediate_operand" "Q,d") (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
(match_operand:HI 1 "const0_operand" ""))) (match_operand:HI 1 "const0_operand" "")))
(clobber (match_scratch:HI 2 "=d,X"))] (clobber (match_scratch:HI 2 "=d,d,X"))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
icm\\t%2,3,%0 icm\\t%2,3,%0
icmy\\t%2,3,%0
tml\\t%0,65535" tml\\t%0,65535"
[(set_attr "op_type" "RS,RI")]) [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tsthi" (define_insn "*tsthi"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:HI 0 "s_operand" "Q") (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" ""))) (match_operand:HI 1 "const0_operand" "")))
(set (match_operand:HI 2 "register_operand" "=d") (set (match_operand:HI 2 "register_operand" "=d,d")
(match_dup 0))] (match_dup 0))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0" "@
[(set_attr "op_type" "RS")]) icm\\t%2,3,%0
icmy\\t%2,3,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tsthi_cconly" (define_insn "*tsthi_cconly"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:HI 0 "s_operand" "Q") (compare (match_operand:HI 0 "s_operand" "Q,S")
(match_operand:HI 1 "const0_operand" ""))) (match_operand:HI 1 "const0_operand" "")))
(clobber (match_scratch:HI 2 "=d"))] (clobber (match_scratch:HI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0" "@
[(set_attr "op_type" "RS")]) icm\\t%2,3,%0
icmy\\t%2,3,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqiCCT" (define_insn "*tstqiCCT"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d") (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" ""))) (match_operand:QI 1 "const0_operand" "")))
(set (match_operand:QI 2 "register_operand" "=d,0") (set (match_operand:QI 2 "register_operand" "=d,d,0")
(match_dup 0))] (match_dup 0))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
icm\\t%2,1,%0 icm\\t%2,1,%0
icmy\\t%2,1,%0
tml\\t%0,255" tml\\t%0,255"
[(set_attr "op_type" "RS,RI")]) [(set_attr "op_type" "RS,RSY,RI")])
(define_insn "*tstqiCCT_cconly" (define_insn "*tstqiCCT_cconly"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d") (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
(match_operand:QI 1 "const0_operand" "")))] (match_operand:QI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
cli\\t%0,0 cli\\t%0,0
cliy\\t%0,0
tml\\t%0,255" tml\\t%0,255"
[(set_attr "op_type" "SI,RI")]) [(set_attr "op_type" "SI,SIY,RI")])
(define_insn "*tstqi" (define_insn "*tstqi"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:QI 0 "s_operand" "Q") (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" ""))) (match_operand:QI 1 "const0_operand" "")))
(set (match_operand:QI 2 "register_operand" "=d") (set (match_operand:QI 2 "register_operand" "=d,d")
(match_dup 0))] (match_dup 0))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0" "@
[(set_attr "op_type" "RS")]) icm\\t%2,1,%0
icmy\\t%2,1,%0"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*tstqi_cconly" (define_insn "*tstqi_cconly"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:QI 0 "s_operand" "Q") (compare (match_operand:QI 0 "s_operand" "Q,S")
(match_operand:QI 1 "const0_operand" ""))) (match_operand:QI 1 "const0_operand" "")))
(clobber (match_scratch:QI 2 "=d"))] (clobber (match_scratch:QI 2 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0" "@
[(set_attr "op_type" "RS")]) icm\\t%2,1,%0
icmy\\t%2,1,%0"
[(set_attr "op_type" "RS,RSY")])
; Compare (signed) instructions ; Compare (signed) instructions
...@@ -688,7 +711,7 @@ ...@@ -688,7 +711,7 @@
"@ "@
cgfr\\t%0,%1 cgfr\\t%0,%1
cgf\\t%0,%1" cgf\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccs" (define_insn "*cmpdi_ccs"
[(set (reg 33) [(set (reg 33)
...@@ -699,26 +722,29 @@ ...@@ -699,26 +722,29 @@
cgr\\t%0,%1 cgr\\t%0,%1
cghi\\t%0,%c1 cghi\\t%0,%c1
cg\\t%0,%1" cg\\t%0,%1"
[(set_attr "op_type" "RRE,RI,RXE")]) [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign" (define_insn "*cmpsi_ccs_sign"
[(set (reg 33) [(set (reg 33)
(compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
(match_operand:SI 0 "register_operand" "d")))] (match_operand:SI 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode)" "s390_match_ccmode(insn, CCSRmode)"
"ch\\t%0,%1" "@
[(set_attr "op_type" "RX")]) ch\\t%0,%1
chy\\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*cmpsi_ccs" (define_insn "*cmpsi_ccs"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SI 0 "register_operand" "d,d,d") (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
(match_operand:SI 1 "general_operand" "d,K,m")))] (match_operand:SI 1 "general_operand" "d,K,R,T")))]
"s390_match_ccmode(insn, CCSmode)" "s390_match_ccmode(insn, CCSmode)"
"@ "@
cr\\t%0,%1 cr\\t%0,%1
chi\\t%0,%c1 chi\\t%0,%c1
c\\t%0,%1" c\\t%0,%1
[(set_attr "op_type" "RR,RI,RX")]) cy\\t%0,%1"
[(set_attr "op_type" "RR,RI,RX,RXY")])
; Compare (unsigned) instructions ; Compare (unsigned) instructions
...@@ -731,7 +757,7 @@ ...@@ -731,7 +757,7 @@
"@ "@
clgfr\\t%0,%1 clgfr\\t%0,%1
clgf\\t%0,%1" clgf\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpdi_ccu" (define_insn "*cmpdi_ccu"
[(set (reg 33) [(set (reg 33)
...@@ -741,41 +767,48 @@ ...@@ -741,41 +767,48 @@
"@ "@
clgr\\t%0,%1 clgr\\t%0,%1
clg\\t%0,%1" clg\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*cmpsi_ccu" (define_insn "*cmpsi_ccu"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SI 0 "register_operand" "d,d") (compare (match_operand:SI 0 "register_operand" "d,d,d")
(match_operand:SI 1 "general_operand" "d,m")))] (match_operand:SI 1 "general_operand" "d,R,T")))]
"s390_match_ccmode(insn, CCUmode)" "s390_match_ccmode(insn, CCUmode)"
"@ "@
clr\\t%0,%1 clr\\t%0,%1
cl\\t%0,%1" cl\\t%0,%1
[(set_attr "op_type" "RR,RX")]) cly\\t%0,%1"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*cmphi_ccu" (define_insn "*cmphi_ccu"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:HI 0 "register_operand" "d") (compare (match_operand:HI 0 "register_operand" "d,d")
(match_operand:HI 1 "s_imm_operand" "Q")))] (match_operand:HI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)" "s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,3,%1" "@
[(set_attr "op_type" "RS")]) clm\\t%0,3,%1
clmy\\t%0,3,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*cmpqi_ccu" (define_insn "*cmpqi_ccu"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:QI 0 "register_operand" "d") (compare (match_operand:QI 0 "register_operand" "d,d")
(match_operand:QI 1 "s_imm_operand" "Q")))] (match_operand:QI 1 "s_imm_operand" "Q,S")))]
"s390_match_ccmode(insn, CCUmode)" "s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,1,%1" "@
[(set_attr "op_type" "RS")]) clm\\t%0,1,%1
clmy\\t%0,1,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*cli" (define_insn "*cli"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:QI 0 "memory_operand" "Q") (compare (match_operand:QI 0 "memory_operand" "Q,S")
(match_operand:QI 1 "immediate_operand" "n")))] (match_operand:QI 1 "immediate_operand" "n,n")))]
"s390_match_ccmode (insn, CCUmode)" "s390_match_ccmode (insn, CCUmode)"
"cli\\t%0,%b1" "@
[(set_attr "op_type" "SI")]) cli\\t%0,%b1
cliy\\t%0,%b1"
[(set_attr "op_type" "SI,SIY")])
(define_insn "*cmpdi_ccu_mem" (define_insn "*cmpdi_ccu_mem"
[(set (reg 33) [(set (reg 33)
...@@ -833,7 +866,7 @@ ...@@ -833,7 +866,7 @@
(define_insn "*cmpdf_ccs" (define_insn "*cmpdf_ccs"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f") (compare (match_operand:DF 0 "register_operand" "f,f")
(match_operand:DF 1 "general_operand" "f,m")))] (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
cdbr\\t%0,%1 cdbr\\t%0,%1
...@@ -844,7 +877,7 @@ ...@@ -844,7 +877,7 @@
(define_insn "*cmpdf_ccs_ibm" (define_insn "*cmpdf_ccs_ibm"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:DF 0 "register_operand" "f,f") (compare (match_operand:DF 0 "register_operand" "f,f")
(match_operand:DF 1 "general_operand" "f,m")))] (match_operand:DF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
cdr\\t%0,%1 cdr\\t%0,%1
...@@ -876,7 +909,7 @@ ...@@ -876,7 +909,7 @@
(define_insn "*cmpsf_ccs" (define_insn "*cmpsf_ccs"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f") (compare (match_operand:SF 0 "register_operand" "f,f")
(match_operand:SF 1 "general_operand" "f,m")))] (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
cebr\\t%0,%1 cebr\\t%0,%1
...@@ -887,7 +920,7 @@ ...@@ -887,7 +920,7 @@
(define_insn "*cmpsf_ccs" (define_insn "*cmpsf_ccs"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SF 0 "register_operand" "f,f") (compare (match_operand:SF 0 "register_operand" "f,f")
(match_operand:SF 1 "general_operand" "f,m")))] (match_operand:SF 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
cer\\t%0,%1 cer\\t%0,%1
...@@ -905,8 +938,8 @@ ...@@ -905,8 +938,8 @@
; ;
(define_insn "movti" (define_insn "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,o,Q") [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
(match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))] (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
lmg\\t%0,%N0,%1 lmg\\t%0,%N0,%1
...@@ -914,7 +947,7 @@ ...@@ -914,7 +947,7 @@
# #
# #
mvc\\t%O0(16,%R0),%1" mvc\\t%O0(16,%R0),%1"
[(set_attr "op_type" "RSE,RSE,NN,NN,SS") [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
(set_attr "type" "lm,stm,*,*,cs")]) (set_attr "type" "lm,stm,*,*,cs")])
(define_split (define_split
...@@ -1023,6 +1056,17 @@ ...@@ -1023,6 +1056,17 @@
}" }"
[(set_attr "op_type" "RI")]) [(set_attr "op_type" "RI")])
(define_insn "*movdi_lay"
[(set (match_operand:DI 0 "register_operand" "=d")
(match_operand:DI 1 "address_operand" "p"))]
"TARGET_64BIT
&& TARGET_LONG_DISPLACEMENT
&& GET_CODE (operands[1]) == CONST_INT
&& !FP_REG_P (operands[0])"
"lay\\t%0,%a1"
[(set_attr "op_type" "RXY")
(set_attr "type" "la")])
(define_insn "*movdi_larl" (define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(match_operand:DI 1 "larl_operand" "X"))] (match_operand:DI 1 "larl_operand" "X"))]
...@@ -1033,8 +1077,8 @@ ...@@ -1033,8 +1077,8 @@
(set_attr "type" "larl")]) (set_attr "type" "larl")])
(define_insn "*movdi_64" (define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q") [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!*f,!R,!T,?Q")
(match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))] (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
lgr\\t%0,%1 lgr\\t%0,%1
...@@ -1042,14 +1086,16 @@ ...@@ -1042,14 +1086,16 @@
stg\\t%1,%0 stg\\t%1,%0
ldr\\t%0,%1 ldr\\t%0,%1
ld\\t%0,%1 ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0 std\\t%1,%0
stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1" mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS") [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")]) (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")])
(define_insn "*movdi_31" (define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!m,Q") [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
(match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))] (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
lm\\t%0,%N0,%1 lm\\t%0,%N0,%1
...@@ -1058,10 +1104,12 @@ ...@@ -1058,10 +1104,12 @@
# #
ldr\\t%0,%1 ldr\\t%0,%1
ld\\t%0,%1 ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0 std\\t%1,%0
stdy\\t%1,%0
mvc\\t%O0(8,%R0),%1" mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS") [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")]) (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
(define_split (define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "") [(set (match_operand:DI 0 "nonimmediate_operand" "")
...@@ -1192,20 +1240,34 @@ ...@@ -1192,20 +1240,34 @@
}" }"
[(set_attr "op_type" "RI")]) [(set_attr "op_type" "RI")])
(define_insn "*movsi_lay"
[(set (match_operand:SI 0 "register_operand" "=d")
(match_operand:SI 1 "address_operand" "p"))]
"TARGET_LONG_DISPLACEMENT
&& GET_CODE (operands[1]) == CONST_INT
&& !FP_REG_P (operands[0])"
"lay\\t%0,%a1"
[(set_attr "op_type" "RXY")
(set_attr "type" "la")])
(define_insn "*movsi" (define_insn "*movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,?Q") [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
(match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,?Q"))] (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
"" ""
"@ "@
lr\\t%0,%1 lr\\t%0,%1
l\\t%0,%1 l\\t%0,%1
ly\\t%0,%1
st\\t%1,%0 st\\t%1,%0
sty\\t%1,%0
ler\\t%0,%1 ler\\t%0,%1
le\\t%0,%1 le\\t%0,%1
ley\\t%0,%1
ste\\t%1,%0 ste\\t%1,%0
stey\\t%1,%0
mvc\\t%O0(4,%R0),%1" mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "lr,load,store,floads,floads,fstores,cs")]) (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
(define_peephole2 (define_peephole2
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -1223,17 +1285,19 @@ ...@@ -1223,17 +1285,19 @@
; ;
(define_insn "movhi" (define_insn "movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,?Q") [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
(match_operand:HI 1 "general_operand" "d,n,m,d,?Q"))] (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
"" ""
"@ "@
lr\\t%0,%1 lr\\t%0,%1
lhi\\t%0,%h1 lhi\\t%0,%h1
lh\\t%0,%1 lh\\t%0,%1
lhy\\t%0,%1
sth\\t%1,%0 sth\\t%1,%0
sthy\\t%1,%0
mvc\\t%O0(2,%R0),%1" mvc\\t%O0(2,%R0),%1"
[(set_attr "op_type" "RR,RI,RX,RX,SS") [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
(set_attr "type" "lr,*,*,store,cs")]) (set_attr "type" "lr,*,*,*,store,store,cs")])
(define_peephole2 (define_peephole2
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -1250,32 +1314,37 @@ ...@@ -1250,32 +1314,37 @@
; ;
(define_insn "movqi_64" (define_insn "movqi_64"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q")
(match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))] (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
lr\\t%0,%1 lr\\t%0,%1
lhi\\t%0,%b1 lhi\\t%0,%b1
llgc\\t%0,%1 llgc\\t%0,%1
stc\\t%1,%0 stc\\t%1,%0
stcy\\t%1,%0
mvi\\t%0,%b1 mvi\\t%0,%b1
mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1" mvc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "RR,RI,RXE,RX,SI,SS") [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
(set_attr "type" "lr,*,*,store,store,cs")]) (set_attr "type" "lr,*,*,store,store,store,store,cs")])
(define_insn "movqi" (define_insn "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,?Q") [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
(match_operand:QI 1 "general_operand" "d,n,m,d,n,?Q"))] (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
"" ""
"@ "@
lr\\t%0,%1 lr\\t%0,%1
lhi\\t%0,%b1 lhi\\t%0,%b1
ic\\t%0,%1 ic\\t%0,%1
icy\\t%0,%1
stc\\t%1,%0 stc\\t%1,%0
stcy\\t%1,%0
mvi\\t%0,%b1 mvi\\t%0,%b1
mviy\\t%0,%b1
mvc\\t%O0(1,%R0),%1" mvc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "RR,RI,RX,RX,SI,SS") [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
(set_attr "type" "lr,*,*,store,store,cs")]) (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
(define_peephole2 (define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "") [(set (match_operand:QI 0 "nonimmediate_operand" "")
...@@ -1292,39 +1361,42 @@ ...@@ -1292,39 +1361,42 @@
; ;
(define_insn "*movstrictqi" (define_insn "*movstrictqi"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
(match_operand:QI 1 "memory_operand" "m"))] (match_operand:QI 1 "memory_operand" "R,T"))]
"" ""
"ic\\t%0,%1" "@
[(set_attr "op_type" "RX")]) ic\\t%0,%1
icy\\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
; ;
; movstricthi instruction pattern(s). ; movstricthi instruction pattern(s).
; ;
(define_insn "*movstricthi" (define_insn "*movstricthi"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
(match_operand:HI 1 "s_imm_operand" "Q")) (match_operand:HI 1 "s_imm_operand" "Q,S"))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"icm\\t%0,3,%1" "@
[(set_attr "op_type" "RS")]) icm\\t%0,3,%1
icmy\\t%0,3,%1"
[(set_attr "op_type" "RS,RSY")])
; ;
; movstrictsi instruction pattern(s). ; movstrictsi instruction pattern(s).
; ;
(define_insn "movstrictsi" (define_insn "movstrictsi"
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d")) [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d"))
(match_operand:SI 1 "general_operand" "d,m"))] (match_operand:SI 1 "general_operand" "d,R,T"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
lr\\t%0,%1 lr\\t%0,%1
l\\t%0,%1" l\\t%0,%1
[(set_attr "op_type" "RR,RS") ly\\t%0,%1"
(set_attr "type" "lr,load")]) [(set_attr "op_type" "RR,RX,RXY")
(set_attr "type" "lr,load,load")])
; ;
; movdf instruction pattern(s). ; movdf instruction pattern(s).
...@@ -1344,35 +1416,39 @@ ...@@ -1344,35 +1416,39 @@
}") }")
(define_insn "*movdf_64" (define_insn "*movdf_64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q") [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
(match_operand:DF 1 "general_operand" "f,m,f,d,m,d,?Q"))] (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
"TARGET_64BIT" "TARGET_64BIT"
"@ "@
ldr\\t%0,%1 ldr\\t%0,%1
ld\\t%0,%1 ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0 std\\t%1,%0
stdy\\t%1,%0
lgr\\t%0,%1 lgr\\t%0,%1
lg\\t%0,%1 lg\\t%0,%1
stg\\t%1,%0 stg\\t%1,%0
mvc\\t%O0(8,%R0),%1" mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
(set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")]) (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
(define_insn "*movdf_31" (define_insn "*movdf_31"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,o,Q") [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
(match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))] (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
ldr\\t%0,%1 ldr\\t%0,%1
ld\\t%0,%1 ld\\t%0,%1
ldy\\t%0,%1
std\\t%1,%0 std\\t%1,%0
stdy\\t%1,%0
lm\\t%0,%N0,%1 lm\\t%0,%N0,%1
stm\\t%1,%N1,%0 stm\\t%1,%N1,%0
# #
# #
mvc\\t%O0(8,%R0),%1" mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
(set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")]) (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
(define_split (define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "") [(set (match_operand:DF 0 "nonimmediate_operand" "")
...@@ -1445,19 +1521,23 @@ ...@@ -1445,19 +1521,23 @@
}") }")
(define_insn "*movsf" (define_insn "*movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,?Q") [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
(match_operand:SF 1 "general_operand" "f,m,f,d,m,d,?Q"))] (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
"" ""
"@ "@
ler\\t%0,%1 ler\\t%0,%1
le\\t%0,%1 le\\t%0,%1
ley\\t%0,%1
ste\\t%1,%0 ste\\t%1,%0
stey\\t%1,%0
lr\\t%0,%1 lr\\t%0,%1
l\\t%0,%1 l\\t%0,%1
ly\\t%0,%1
st\\t%1,%0 st\\t%1,%0
sty\\t%1,%0
mvc\\t%O0(4,%R0),%1" mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
(set_attr "type" "floads,floads,fstores,lr,load,store,cs")]) (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
; ;
; load_multiple pattern(s). ; load_multiple pattern(s).
...@@ -1526,37 +1606,29 @@ ...@@ -1526,37 +1606,29 @@
(define_insn "*load_multiple_di" (define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r") [(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "Q"))])] (match_operand:DI 2 "s_operand" "QS"))])]
"" ""
"* "*
{ {
int words = XVECLEN (operands[0], 0); int words = XVECLEN (operands[0], 0);
if (XVECLEN (operands[0], 0) == 1)
return \"lg\\t%1,0(%2)\";
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
return \"lmg\\t%1,%0,%2\"; return \"lmg\\t%1,%0,%2\";
}" }"
[(set_attr "op_type" "RXE") [(set_attr "op_type" "RSY")
(set_attr "type" "lm")]) (set_attr "type" "lm")])
(define_insn "*load_multiple_si" (define_insn "*load_multiple_si"
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "register_operand" "=r") [(set (match_operand:SI 1 "register_operand" "=r,r")
(match_operand:SI 2 "s_operand" "Q"))])] (match_operand:SI 2 "s_operand" "Q,S"))])]
"" ""
"* "*
{ {
int words = XVECLEN (operands[0], 0); int words = XVECLEN (operands[0], 0);
if (XVECLEN (operands[0], 0) == 1)
return \"l\\t%1,0(%2)\";
operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
return \"lm\\t%1,%0,%2\"; return which_alternative == 0 ? \"lm\\t%1,%0,%2\" : \"lmy\\t%1,%0,%2\";
}" }"
[(set_attr "op_type" "RXE") [(set_attr "op_type" "RS,RSY")
(set_attr "type" "lm")]) (set_attr "type" "lm")])
; ;
...@@ -1627,39 +1699,31 @@ ...@@ -1627,39 +1699,31 @@
(define_insn "*store_multiple_di" (define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=Q") [(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])] (match_operand:DI 2 "register_operand" "r"))])]
"" ""
"* "*
{ {
int words = XVECLEN (operands[0], 0); int words = XVECLEN (operands[0], 0);
if (XVECLEN (operands[0], 0) == 1)
return \"stg\\t%1,0(%2)\";
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
return \"stmg\\t%2,%0,%1\"; return \"stmg\\t%2,%0,%1\";
}" }"
[(set_attr "op_type" "RXE") [(set_attr "op_type" "RSY")
(set_attr "type" "stm")]) (set_attr "type" "stm")])
(define_insn "*store_multiple_si" (define_insn "*store_multiple_si"
[(match_parallel 0 "store_multiple_operation" [(match_parallel 0 "store_multiple_operation"
[(set (match_operand:SI 1 "s_operand" "=Q") [(set (match_operand:SI 1 "s_operand" "=Q,S")
(match_operand:SI 2 "register_operand" "r"))])] (match_operand:SI 2 "register_operand" "r,r"))])]
"" ""
"* "*
{ {
int words = XVECLEN (operands[0], 0); int words = XVECLEN (operands[0], 0);
if (XVECLEN (operands[0], 0) == 1)
return \"st\\t%1,0(%2)\";
operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
return \"stm\\t%2,%0,%1\"; return which_alternative == 0 ? \"stm\\t%2,%0,%1\" : \"stmy\\t%2,%0,%1\";
}" }"
[(set_attr "op_type" "RXE") [(set_attr "op_type" "RS,RSY")
(set_attr "type" "stm")]) (set_attr "type" "stm")])
;; ;;
...@@ -2043,36 +2107,42 @@ ...@@ -2043,36 +2107,42 @@
;; ;;
(define_insn "*sethighqisi" (define_insn "*sethighqisi"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10)) (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"icm\\t%0,8,%1" "@
[(set_attr "op_type" "RS")]) icm\\t%0,8,%1
icmy\\t%0,8,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighhisi" (define_insn "*sethighhisi"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10)) (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"icm\\t%0,12,%1" "@
[(set_attr "op_type" "RS")]) icm\\t%0,12,%1
icmy\\t%0,12,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn "*sethighqidi_64" (define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10)) (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] 10))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_64BIT" "TARGET_64BIT"
"icmh\\t%0,8,%1" "icmh\\t%0,8,%1"
[(set_attr "op_type" "RSE")]) [(set_attr "op_type" "RSY")])
(define_insn "*sethighqidi_31" (define_insn "*sethighqidi_31"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10)) (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"!TARGET_64BIT" "!TARGET_64BIT"
"icm\\t%0,8,%1" "@
[(set_attr "op_type" "RS")]) icm\\t%0,8,%1
icmy\\t%0,8,%1"
[(set_attr "op_type" "RS,RSY")])
(define_insn_and_split "*extractqi" (define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
...@@ -2144,7 +2214,7 @@ ...@@ -2144,7 +2214,7 @@
"@ "@
lgfr\\t%0,%1 lgfr\\t%0,%1
lgf\\t%0,%1" lgf\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
; ;
; extendhidi2 instruction pattern(s). ; extendhidi2 instruction pattern(s).
...@@ -2178,7 +2248,7 @@ ...@@ -2178,7 +2248,7 @@
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_64BIT"
"lgh\\t%0,%1" "lgh\\t%0,%1"
[(set_attr "op_type" "RXE")]) [(set_attr "op_type" "RXY")])
; ;
; extendqidi2 instruction pattern(s). ; extendqidi2 instruction pattern(s).
...@@ -2207,10 +2277,17 @@ ...@@ -2207,10 +2277,17 @@
} }
") ")
(define_insn "*extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
"lgb\\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_split (define_split
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "s_operand" "")))] (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
"TARGET_64BIT && !reload_completed" "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed"
[(parallel [(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] 10)) [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
(clobber (reg:CC 33))]) (clobber (reg:CC 33))])
...@@ -2237,11 +2314,13 @@ ...@@ -2237,11 +2314,13 @@
") ")
(define_insn "*extendhisi2" (define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
"" ""
"lh\\t%0,%1" "@
[(set_attr "op_type" "RX")]) lh\\t%0,%1
lhy\\t%0,%1"
[(set_attr "op_type" "RX,RXY")])
; ;
; extendqisi2 instruction pattern(s). ; extendqisi2 instruction pattern(s).
...@@ -2260,10 +2339,17 @@ ...@@ -2260,10 +2339,17 @@
} }
") ")
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
"lb\\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_split (define_split
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))] (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
"!reload_completed" "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed"
[(parallel [(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
(clobber (reg:CC 33))]) (clobber (reg:CC 33))])
...@@ -2304,7 +2390,7 @@ ...@@ -2304,7 +2390,7 @@
"@ "@
llgfr\\t%0,%1 llgfr\\t%0,%1
llgf\\t%0,%1" llgf\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
; ;
; zero_extendhidi2 instruction pattern(s). ; zero_extendhidi2 instruction pattern(s).
...@@ -2338,7 +2424,7 @@ ...@@ -2338,7 +2424,7 @@
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_64BIT"
"llgh\\t%0,%1" "llgh\\t%0,%1"
[(set_attr "op_type" "RXE")]) [(set_attr "op_type" "RXY")])
; ;
; zero_extendqidi2 instruction pattern(s) ; zero_extendqidi2 instruction pattern(s)
...@@ -2372,7 +2458,7 @@ ...@@ -2372,7 +2458,7 @@
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_64BIT"
"llgc\\t%0,%1" "llgc\\t%0,%1"
[(set_attr "op_type" "RXE")]) [(set_attr "op_type" "RXY")])
; ;
; zero_extendhisi2 instruction pattern(s). ; zero_extendhisi2 instruction pattern(s).
...@@ -2395,11 +2481,11 @@ ...@@ -2395,11 +2481,11 @@
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_64BIT"
"llgh\\t%0,%1" "llgh\\t%0,%1"
[(set_attr "op_type" "RXE")]) [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendhisi2_31" (define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d") [(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:HI 1 "memory_operand" "Q"))) (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"!TARGET_64BIT" "!TARGET_64BIT"
"#" "#"
...@@ -2432,7 +2518,7 @@ ...@@ -2432,7 +2518,7 @@
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_64BIT"
"llgc\\t%0,%1" "llgc\\t%0,%1"
[(set_attr "op_type" "RXE")]) [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqisi2_31" (define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d") [(set (match_operand:SI 0 "register_operand" "=&d")
...@@ -2466,7 +2552,7 @@ ...@@ -2466,7 +2552,7 @@
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT" "TARGET_64BIT"
"llgc\\t%0,%1" "llgc\\t%0,%1"
[(set_attr "op_type" "RXE")]) [(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqihi2_31" (define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d") [(set (match_operand:HI 0 "register_operand" "=&d")
...@@ -2866,7 +2952,7 @@ ...@@ -2866,7 +2952,7 @@
(define_insn "truncdfsf2_ibm" (define_insn "truncdfsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))] (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
lrer\\t%0,%1 lrer\\t%0,%1
...@@ -2893,7 +2979,7 @@ ...@@ -2893,7 +2979,7 @@
(define_insn "extendsfdf2_ieee" (define_insn "extendsfdf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))] (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
ldebr\\t%0,%1 ldebr\\t%0,%1
...@@ -2903,7 +2989,7 @@ ...@@ -2903,7 +2989,7 @@
(define_insn "extendsfdf2_ibm" (define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m"))) (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -2939,7 +3025,7 @@ ...@@ -2939,7 +3025,7 @@
"@ "@
agfr\\t%0,%2 agfr\\t%0,%2
agf\\t%0,%2" agf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc" (define_insn "*adddi3_zero_cc"
[(set (reg 33) [(set (reg 33)
...@@ -2952,7 +3038,7 @@ ...@@ -2952,7 +3038,7 @@
"@ "@
algfr\\t%0,%2 algfr\\t%0,%2
algf\\t%0,%2" algf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly" (define_insn "*adddi3_zero_cconly"
[(set (reg 33) [(set (reg 33)
...@@ -2964,7 +3050,7 @@ ...@@ -2964,7 +3050,7 @@
"@ "@
algfr\\t%0,%2 algfr\\t%0,%2
algf\\t%0,%2" algf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero" (define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
...@@ -2975,7 +3061,7 @@ ...@@ -2975,7 +3061,7 @@
"@ "@
algfr\\t%0,%2 algfr\\t%0,%2
algf\\t%0,%2" algf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc" (define_insn "*adddi3_imm_cc"
[(set (reg 33) [(set (reg 33)
...@@ -3001,7 +3087,7 @@ ...@@ -3001,7 +3087,7 @@
"@ "@
algr\\t%0,%2 algr\\t%0,%2
alg\\t%0,%2" alg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly" (define_insn "*adddi3_cconly"
[(set (reg 33) [(set (reg 33)
...@@ -3013,7 +3099,7 @@ ...@@ -3013,7 +3099,7 @@
"@ "@
algr\\t%0,%2 algr\\t%0,%2
alg\\t%0,%2" alg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2" (define_insn "*adddi3_cconly2"
[(set (reg 33) [(set (reg 33)
...@@ -3024,7 +3110,7 @@ ...@@ -3024,7 +3110,7 @@
"@ "@
algr\\t%0,%2 algr\\t%0,%2
alg\\t%0,%2" alg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_64" (define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d") [(set (match_operand:DI 0 "register_operand" "=d,d,d")
...@@ -3036,7 +3122,7 @@ ...@@ -3036,7 +3122,7 @@
agr\\t%0,%2 agr\\t%0,%2
aghi\\t%0,%h2 aghi\\t%0,%h2
ag\\t%0,%2" ag\\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXE")]) [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn_and_split "*adddi3_31" (define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d") [(set (match_operand:DI 0 "register_operand" "=&d")
...@@ -3081,11 +3167,13 @@ ...@@ -3081,11 +3167,13 @@
"") "")
(define_insn "*la_64" (define_insn "*la_64"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(match_operand:QI 1 "address_operand" "p"))] (match_operand:QI 1 "address_operand" "U,W"))]
"TARGET_64BIT" "TARGET_64BIT"
"la\\t%0,%a1" "@
[(set_attr "op_type" "RX") la\\t%0,%a1
lay\\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")]) (set_attr "type" "la")])
(define_peephole2 (define_peephole2
...@@ -3144,126 +3232,140 @@ ...@@ -3144,126 +3232,140 @@
(define_insn "*addsi3_carry1_cc" (define_insn "*addsi3_carry1_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1))) (match_dup 1)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2" al\\t%0,%2
[(set_attr "op_type" "RR,RX")]) aly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly" (define_insn "*addsi3_carry1_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1))) (match_dup 1)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2" al\\t%0,%2
[(set_attr "op_type" "RR,RX")]) aly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc" (define_insn "*addsi3_carry2_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2))) (match_dup 2)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2" al\\t%0,%2
[(set_attr "op_type" "RR,RX")]) aly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly" (define_insn "*addsi3_carry2_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2))) (match_dup 2)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2" al\\t%0,%2
[(set_attr "op_type" "RR,RX")]) aly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc" (define_insn "*addsi3_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2" al\\t%0,%2
[(set_attr "op_type" "RR,RX")]) aly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly" (define_insn "*addsi3_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2" al\\t%0,%2
[(set_attr "op_type" "RR,RX")]) aly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2" (define_insn "*addsi3_cconly2"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(neg:SI (match_operand:SI 2 "general_operand" "d,m")))) (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)" "s390_match_ccmode(insn, CCLmode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2" al\\t%0,%2
[(set_attr "op_type" "RR,RX")]) aly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_sign" (define_insn "*addsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_operand:SI 1 "register_operand" "0") (plus:SI (match_operand:SI 1 "register_operand" "0,0")
(sign_extend:SI (match_operand:HI 2 "memory_operand" "m")))) (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"ah\\t%0,%2" "@
[(set_attr "op_type" "RX")]) ah\\t%0,%2
ahy\\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*addsi3_sub" (define_insn "*addsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(plus:SI (match_operand:SI 1 "register_operand" "0") (plus:SI (match_operand:SI 1 "register_operand" "0,0")
(subreg:SI (match_operand:HI 2 "memory_operand" "m") 0))) (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"ah\\t%0,%2" "@
[(set_attr "op_type" "RX")]) ah\\t%0,%2
ahy\\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "addsi3" (define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d") [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,K,m"))) (match_operand:SI 2 "general_operand" "d,K,R,T")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
ar\\t%0,%2 ar\\t%0,%2
ahi\\t%0,%h2 ahi\\t%0,%h2
a\\t%0,%2" a\\t%0,%2
[(set_attr "op_type" "RR,RI,RX")]) ay\\t%0,%2"
[(set_attr "op_type" "RR,RI,RX,RXY")])
(define_insn "*la_31" (define_insn "*la_31"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:QI 1 "address_operand" "p"))] (match_operand:QI 1 "address_operand" "U,W"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])" "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
"la\\t%0,%a1" "@
[(set_attr "op_type" "RX") la\\t%0,%a1
lay\\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")]) (set_attr "type" "la")])
(define_peephole2 (define_peephole2
...@@ -3293,12 +3395,14 @@ ...@@ -3293,12 +3395,14 @@
"") "")
(define_insn "*la_31_and" (define_insn "*la_31_and"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(and:SI (match_operand:QI 1 "address_operand" "p") (and:SI (match_operand:QI 1 "address_operand" "U,W")
(const_int 2147483647)))] (const_int 2147483647)))]
"!TARGET_64BIT" "!TARGET_64BIT"
"la\\t%0,%a1" "@
[(set_attr "op_type" "RX") la\\t%0,%a1
lay\\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")]) (set_attr "type" "la")])
(define_insn_and_split "*la_31_and_cc" (define_insn_and_split "*la_31_and_cc"
...@@ -3316,11 +3420,13 @@ ...@@ -3316,11 +3420,13 @@
(set_attr "type" "la")]) (set_attr "type" "la")])
(define_insn "force_la_31" (define_insn "force_la_31"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:QI 1 "address_operand" "p")) (match_operand:QI 1 "address_operand" "U,W"))
(use (const_int 0))] (use (const_int 0))]
"!TARGET_64BIT" "!TARGET_64BIT"
"la\\t%0,%a1" "@
la\\t%0,%a1
lay\\t%0,%a1"
[(set_attr "op_type" "RX") [(set_attr "op_type" "RX")
(set_attr "type" "la")]) (set_attr "type" "la")])
...@@ -3344,7 +3450,7 @@ ...@@ -3344,7 +3450,7 @@
[(parallel [(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -3352,7 +3458,7 @@ ...@@ -3352,7 +3458,7 @@
(define_insn "*adddf3" (define_insn "*adddf3"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -3364,7 +3470,7 @@ ...@@ -3364,7 +3470,7 @@
(define_insn "*adddf3_ibm" (define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -3381,7 +3487,7 @@ ...@@ -3381,7 +3487,7 @@
[(parallel [(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -3389,7 +3495,7 @@ ...@@ -3389,7 +3495,7 @@
(define_insn "*addsf3" (define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -3401,7 +3507,7 @@ ...@@ -3401,7 +3507,7 @@
(define_insn "*addsf3" (define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -3428,7 +3534,7 @@ ...@@ -3428,7 +3534,7 @@
"@ "@
sgfr\\t%0,%2 sgfr\\t%0,%2
sgf\\t%0,%2" sgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc" (define_insn "*subdi3_zero_cc"
[(set (reg 33) [(set (reg 33)
...@@ -3441,7 +3547,7 @@ ...@@ -3441,7 +3547,7 @@
"@ "@
slgfr\\t%0,%2 slgfr\\t%0,%2
slgf\\t%0,%2" slgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly" (define_insn "*subdi3_zero_cconly"
[(set (reg 33) [(set (reg 33)
...@@ -3453,7 +3559,7 @@ ...@@ -3453,7 +3559,7 @@
"@ "@
slgfr\\t%0,%2 slgfr\\t%0,%2
slgf\\t%0,%2" slgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero" (define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
...@@ -3464,7 +3570,7 @@ ...@@ -3464,7 +3570,7 @@
"@ "@
slgfr\\t%0,%2 slgfr\\t%0,%2
slgf\\t%0,%2" slgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cc" (define_insn "*subdi3_cc"
[(set (reg 33) [(set (reg 33)
...@@ -3477,7 +3583,7 @@ ...@@ -3477,7 +3583,7 @@
"@ "@
slgr\\t%0,%2 slgr\\t%0,%2
slg\\t%0,%2" slg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_cconly" (define_insn "*subdi3_cconly"
[(set (reg 33) [(set (reg 33)
...@@ -3489,7 +3595,7 @@ ...@@ -3489,7 +3595,7 @@
"@ "@
slgr\\t%0,%2 slgr\\t%0,%2
slg\\t%0,%2" slg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_64" (define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
...@@ -3550,82 +3656,91 @@ ...@@ -3550,82 +3656,91 @@
(define_insn "*subsi3_borrow_cc" (define_insn "*subsi3_borrow_cc"
[(set (reg 33) [(set (reg 33)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1))) (match_dup 1)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))] (minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCL2mode)" "s390_match_ccmode(insn, CCL2mode)"
"@ "@
slr\\t%0,%2 slr\\t%0,%2
sl\\t%0,%2" sl\\t%0,%2
[(set_attr "op_type" "RR,RX")]) sly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_borrow_cconly" (define_insn "*subsi3_borrow_cconly"
[(set (reg 33) [(set (reg 33)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1))) (match_dup 1)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCL2mode)" "s390_match_ccmode(insn, CCL2mode)"
"@ "@
slr\\t%0,%2 slr\\t%0,%2
sl\\t%0,%2" sl\\t%0,%2
[(set_attr "op_type" "RR,RX")]) sly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXE")])
(define_insn "*subsi3_cc" (define_insn "*subsi3_cc"
[(set (reg 33) [(set (reg 33)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_dup 1) (match_dup 2)))] (minus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCLmode)" "s390_match_ccmode(insn, CCLmode)"
"@ "@
slr\\t%0,%2 slr\\t%0,%2
sl\\t%0,%2" sl\\t%0,%2
[(set_attr "op_type" "RR,RX")]) sly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_cconly" (define_insn "*subsi3_cconly"
[(set (reg 33) [(set (reg 33)
(compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCLmode)" "s390_match_ccmode(insn, CCLmode)"
"@ "@
slr\\t%0,%2 slr\\t%0,%2
sl\\t%0,%2" sl\\t%0,%2
[(set_attr "op_type" "RR,RX")]) sly\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*subsi3_sign" (define_insn "*subsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0") (minus:SI (match_operand:SI 1 "register_operand" "0,0")
(sign_extend:SI (match_operand:HI 2 "memory_operand" "m")))) (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"sh\\t%0,%2" "@
[(set_attr "op_type" "RX")]) sh\\t%0,%2
shy\\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "*subsi3_sub" (define_insn "*subsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0") (minus:SI (match_operand:SI 1 "register_operand" "0,0")
(subreg:SI (match_operand:HI 2 "memory_operand" "m") 0))) (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0)))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"sh\\t%0,%2" "@
[(set_attr "op_type" "RX")]) sh\\t%0,%2
shy\\t%0,%2"
[(set_attr "op_type" "RX,RXY")])
(define_insn "subsi3" (define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d,d")
(minus:SI (match_operand:SI 1 "register_operand" "0,0") (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
(match_operand:SI 2 "general_operand" "d,m"))) (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
sr\\t%0,%2 sr\\t%0,%2
s\\t%0,%2" s\\t%0,%2
[(set_attr "op_type" "RR,RX")]) sy\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
; ;
...@@ -3636,7 +3751,7 @@ ...@@ -3636,7 +3751,7 @@
[(parallel [(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0") (minus:DF (match_operand:DF 1 "register_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -3644,7 +3759,7 @@ ...@@ -3644,7 +3759,7 @@
(define_insn "*subdf3" (define_insn "*subdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0") (minus:DF (match_operand:DF 1 "register_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -3656,7 +3771,7 @@ ...@@ -3656,7 +3771,7 @@
(define_insn "*subdf3_ibm" (define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(minus:DF (match_operand:DF 1 "register_operand" "0,0") (minus:DF (match_operand:DF 1 "register_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -3673,7 +3788,7 @@ ...@@ -3673,7 +3788,7 @@
[(parallel [(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0") (minus:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -3681,7 +3796,7 @@ ...@@ -3681,7 +3796,7 @@
(define_insn "*subsf3" (define_insn "*subsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0") (minus:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -3693,7 +3808,7 @@ ...@@ -3693,7 +3808,7 @@
(define_insn "*subsf3_ibm" (define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(minus:SF (match_operand:SF 1 "register_operand" "0,0") (minus:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -3719,7 +3834,7 @@ ...@@ -3719,7 +3834,7 @@
"@ "@
msgfr\\t%0,%2 msgfr\\t%0,%2
msgf\\t%0,%2" msgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")]) (set_attr "type" "imul")])
...@@ -3732,7 +3847,7 @@ ...@@ -3732,7 +3847,7 @@
msgr\\t%0,%2 msgr\\t%0,%2
mghi\\t%0,%h2 mghi\\t%0,%h2
msg\\t%0,%2" msg\\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXE") [(set_attr "op_type" "RRE,RI,RXY")
(set_attr "type" "imul")]) (set_attr "type" "imul")])
; ;
...@@ -3740,15 +3855,16 @@ ...@@ -3740,15 +3855,16 @@
; ;
(define_insn "mulsi3" (define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d") [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:SI 2 "general_operand" "d,K,m")))] (match_operand:SI 2 "general_operand" "d,K,R,T")))]
"" ""
"@ "@
msr\\t%0,%2 msr\\t%0,%2
mhi\\t%0,%h2 mhi\\t%0,%h2
ms\\t%0,%2" ms\\t%0,%2
[(set_attr "op_type" "RRE,RI,RX") msy\\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX,RXY")
(set_attr "type" "imul")]) (set_attr "type" "imul")])
; ;
...@@ -3781,7 +3897,7 @@ ...@@ -3781,7 +3897,7 @@
(mult:DI (sign_extend:DI (mult:DI (sign_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,m"))))] (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
mr\\t%0,%2 mr\\t%0,%2
...@@ -3797,7 +3913,7 @@ ...@@ -3797,7 +3913,7 @@
[(parallel [(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -3805,7 +3921,7 @@ ...@@ -3805,7 +3921,7 @@
(define_insn "*muldf3" (define_insn "*muldf3"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -3817,7 +3933,7 @@ ...@@ -3817,7 +3933,7 @@
(define_insn "*muldf3_ibm" (define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -3834,7 +3950,7 @@ ...@@ -3834,7 +3950,7 @@
[(parallel [(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -3842,7 +3958,7 @@ ...@@ -3842,7 +3958,7 @@
(define_insn "*mulsf3" (define_insn "*mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -3854,7 +3970,7 @@ ...@@ -3854,7 +3970,7 @@
(define_insn "*mulsf3_ibm" (define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -3926,7 +4042,7 @@ ...@@ -3926,7 +4042,7 @@
"@ "@
dsgr\\t%0,%2 dsgr\\t%0,%2
dsg\\t%0,%2" dsg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")]) (set_attr "type" "idiv")])
(define_insn "divmodtisi3" (define_insn "divmodtisi3"
...@@ -3944,7 +4060,7 @@ ...@@ -3944,7 +4060,7 @@
"@ "@
dsgfr\\t%0,%2 dsgfr\\t%0,%2
dsgf\\t%0,%2" dsgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")]) (set_attr "type" "idiv")])
; ;
...@@ -4006,7 +4122,7 @@ ...@@ -4006,7 +4122,7 @@
"@ "@
dlgr\\t%0,%2 dlgr\\t%0,%2
dlg\\t%0,%2" dlg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE") [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")]) (set_attr "type" "idiv")])
; ;
...@@ -4056,7 +4172,7 @@ ...@@ -4056,7 +4172,7 @@
(truncate:SI (truncate:SI
(div:DI (match_operand:DI 1 "register_operand" "0,0") (div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,m"))))) (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
(ashift:DI (ashift:DI
(zero_extend:DI (zero_extend:DI
(truncate:SI (truncate:SI
...@@ -4266,7 +4382,7 @@ ...@@ -4266,7 +4382,7 @@
[(parallel [(parallel
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0") (div:DF (match_operand:DF 1 "register_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -4274,7 +4390,7 @@ ...@@ -4274,7 +4390,7 @@
(define_insn "*divdf3" (define_insn "*divdf3"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0") (div:DF (match_operand:DF 1 "register_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -4286,7 +4402,7 @@ ...@@ -4286,7 +4402,7 @@
(define_insn "*divdf3_ibm" (define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(div:DF (match_operand:DF 1 "register_operand" "0,0") (div:DF (match_operand:DF 1 "register_operand" "0,0")
(match_operand:DF 2 "general_operand" "f,m"))) (match_operand:DF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -4303,7 +4419,7 @@ ...@@ -4303,7 +4419,7 @@
[(parallel [(parallel
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0") (div:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
"") "")
...@@ -4311,7 +4427,7 @@ ...@@ -4311,7 +4427,7 @@
(define_insn "*divsf3" (define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0") (div:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
...@@ -4323,7 +4439,7 @@ ...@@ -4323,7 +4439,7 @@
(define_insn "*divsf3" (define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(div:SF (match_operand:SF 1 "register_operand" "0,0") (div:SF (match_operand:SF 1 "register_operand" "0,0")
(match_operand:SF 2 "general_operand" "f,m"))) (match_operand:SF 2 "general_operand" "f,R")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@ "@
...@@ -4352,7 +4468,7 @@ ...@@ -4352,7 +4468,7 @@
"@ "@
ngr\\t%0,%2 ngr\\t%0,%2
ng\\t%0,%2" ng\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_cconly" (define_insn "*anddi3_cconly"
[(set (reg 33) [(set (reg 33)
...@@ -4364,7 +4480,7 @@ ...@@ -4364,7 +4480,7 @@
"@ "@
ngr\\t%0,%2 ngr\\t%0,%2
ng\\t%0,%2" ng\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ni" (define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
...@@ -4397,7 +4513,7 @@ ...@@ -4397,7 +4513,7 @@
"@ "@
ngr\\t%0,%2 ngr\\t%0,%2
ng\\t%0,%2" ng\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*anddi3_ss" (define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q") [(set (match_operand:DI 0 "s_operand" "=Q")
...@@ -4423,28 +4539,30 @@ ...@@ -4423,28 +4539,30 @@
(define_insn "*andsi3_cc" (define_insn "*andsi3_cc"
[(set (reg 33) [(set (reg 33)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(and:SI (match_dup 1) (match_dup 2)))] (and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
nr\\t%0,%2 nr\\t%0,%2
n\\t%0,%2" n\\t%0,%2
[(set_attr "op_type" "RR,RX")]) ny\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_cconly" (define_insn "*andsi3_cconly"
[(set (reg 33) [(set (reg 33)
(compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
nr\\t%0,%2 nr\\t%0,%2
n\\t%0,%2" n\\t%0,%2
[(set_attr "op_type" "RR,RX")]) ny\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ni" (define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
...@@ -4467,15 +4585,16 @@ ...@@ -4467,15 +4585,16 @@
[(set_attr "op_type" "RI")]) [(set_attr "op_type" "RI")])
(define_insn "andsi3" (define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d,d")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m"))) (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
nr\\t%0,%2 nr\\t%0,%2
n\\t%0,%2" n\\t%0,%2
[(set_attr "op_type" "RR,RX")]) ny\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*andsi3_ss" (define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q") [(set (match_operand:SI 0 "s_operand" "=Q")
...@@ -4562,26 +4681,28 @@ ...@@ -4562,26 +4681,28 @@
[(set_attr "op_type" "RR")]) [(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss" (define_insn "*andqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q") [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(and:QI (match_dup 0) (and:QI (match_dup 0)
(match_operand:QI 1 "s_imm_operand" "n,Q"))) (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
ni\\t%0,%b1 ni\\t%0,%b1
niy\\t%0,%b1
nc\\t%O0(1,%R0),%1" nc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SS")]) [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*andqi3_ss_inv" (define_insn "*andqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q") [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(and:QI (match_operand:QI 1 "s_imm_operand" "n,Q") (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0))) (match_dup 0)))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
ni\\t%0,%b1 ni\\t%0,%b1
niy\\t%0,%b1
nc\\t%O0(1,%R0),%1" nc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SS")]) [(set_attr "op_type" "SI,SIY,SS")])
;; ;;
...@@ -4603,7 +4724,7 @@ ...@@ -4603,7 +4724,7 @@
"@ "@
ogr\\t%0,%2 ogr\\t%0,%2
og\\t%0,%2" og\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_cconly" (define_insn "*iordi3_cconly"
[(set (reg 33) [(set (reg 33)
...@@ -4615,7 +4736,7 @@ ...@@ -4615,7 +4736,7 @@
"@ "@
ogr\\t%0,%2 ogr\\t%0,%2
og\\t%0,%2" og\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_oi" (define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
...@@ -4648,7 +4769,7 @@ ...@@ -4648,7 +4769,7 @@
"@ "@
ogr\\t%0,%2 ogr\\t%0,%2
og\\t%0,%2" og\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*iordi3_ss" (define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q") [(set (match_operand:DI 0 "s_operand" "=Q")
...@@ -4674,28 +4795,30 @@ ...@@ -4674,28 +4795,30 @@
(define_insn "*iorsi3_cc" (define_insn "*iorsi3_cc"
[(set (reg 33) [(set (reg 33)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(ior:SI (match_dup 1) (match_dup 2)))] (ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
or\\t%0,%2 or\\t%0,%2
o\\t%0,%2" o\\t%0,%2
[(set_attr "op_type" "RR,RX")]) oy\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_cconly" (define_insn "*iorsi3_cconly"
[(set (reg 33) [(set (reg 33)
(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
or\\t%0,%2 or\\t%0,%2
o\\t%0,%2" o\\t%0,%2
[(set_attr "op_type" "RR,RX")]) oy\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_oi" (define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d")
...@@ -4718,15 +4841,16 @@ ...@@ -4718,15 +4841,16 @@
[(set_attr "op_type" "RI")]) [(set_attr "op_type" "RI")])
(define_insn "iorsi3" (define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d,d")
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m"))) (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
or\\t%0,%2 or\\t%0,%2
o\\t%0,%2" o\\t%0,%2
[(set_attr "op_type" "RR,RX")]) oy\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*iorsi3_ss" (define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q") [(set (match_operand:SI 0 "s_operand" "=Q")
...@@ -4813,26 +4937,28 @@ ...@@ -4813,26 +4937,28 @@
[(set_attr "op_type" "RR")]) [(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss" (define_insn "*iorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q") [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(ior:QI (match_dup 0) (ior:QI (match_dup 0)
(match_operand:QI 1 "s_imm_operand" "n,Q"))) (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
oi\\t%0,%b1 oi\\t%0,%b1
oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1" oc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SS")]) [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*iorqi3_ss_inv" (define_insn "*iorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q") [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q") (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0))) (match_dup 0)))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
oi\\t%0,%b1 oi\\t%0,%b1
oiy\\t%0,%b1
oc\\t%O0(1,%R0),%1" oc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SS")]) [(set_attr "op_type" "SI,SIY,SS")])
;; ;;
...@@ -4854,7 +4980,7 @@ ...@@ -4854,7 +4980,7 @@
"@ "@
xgr\\t%0,%2 xgr\\t%0,%2
xg\\t%0,%2" xg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_cconly" (define_insn "*xordi3_cconly"
[(set (reg 33) [(set (reg 33)
...@@ -4866,7 +4992,7 @@ ...@@ -4866,7 +4992,7 @@
"@ "@
xgr\\t%0,%2 xgr\\t%0,%2
xr\\t%0,%2" xr\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "xordi3" (define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
...@@ -4877,7 +5003,7 @@ ...@@ -4877,7 +5003,7 @@
"@ "@
xgr\\t%0,%2 xgr\\t%0,%2
xg\\t%0,%2" xg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*xordi3_ss" (define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q") [(set (match_operand:DI 0 "s_operand" "=Q")
...@@ -4903,39 +5029,42 @@ ...@@ -4903,39 +5029,42 @@
(define_insn "*xorsi3_cc" (define_insn "*xorsi3_cc"
[(set (reg 33) [(set (reg 33)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(xor:SI (match_dup 1) (match_dup 2)))] (xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
xr\\t%0,%2 xr\\t%0,%2
x\\t%0,%2" x\\t%0,%2
[(set_attr "op_type" "RR,RX")]) xy\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_cconly" (define_insn "*xorsi3_cconly"
[(set (reg 33) [(set (reg 33)
(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode)" "s390_match_ccmode(insn, CCTmode)"
"@ "@
xr\\t%0,%2 xr\\t%0,%2
x\\t%0,%2" x\\t%0,%2
[(set_attr "op_type" "RR,RX")]) xy\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "xorsi3" (define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d") [(set (match_operand:SI 0 "register_operand" "=d,d,d")
(xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,m"))) (match_operand:SI 2 "general_operand" "d,R,T")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
xr\\t%0,%2 xr\\t%0,%2
x\\t%0,%2" x\\t%0,%2
[(set_attr "op_type" "RR,RX")]) xy\\t%0,%2"
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*xorsi3_ss" (define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q") [(set (match_operand:SI 0 "s_operand" "=Q")
...@@ -4966,8 +5095,7 @@ ...@@ -4966,8 +5095,7 @@
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"xr\\t%0,%2" "xr\\t%0,%2"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")])
(set_attr "atype" "reg")])
(define_insn "*xorhi3_ss" (define_insn "*xorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q") [(set (match_operand:HI 0 "s_operand" "=Q")
...@@ -5001,26 +5129,28 @@ ...@@ -5001,26 +5129,28 @@
[(set_attr "op_type" "RR")]) [(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss" (define_insn "*xorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q") [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(xor:QI (match_dup 0) (xor:QI (match_dup 0)
(match_operand:QI 1 "s_imm_operand" "n,Q"))) (match_operand:QI 1 "s_imm_operand" "n,n,Q")))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
xi\\t%0,%b1 xi\\t%0,%b1
xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1" xc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SS")]) [(set_attr "op_type" "SI,SIY,SS")])
(define_insn "*xorqi3_ss_inv" (define_insn "*xorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q") [(set (match_operand:QI 0 "s_operand" "=Q,S,Q")
(xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q") (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q")
(match_dup 0))) (match_dup 0)))
(clobber (reg:CC 33))] (clobber (reg:CC 33))]
"" ""
"@ "@
xi\\t%0,%b1 xi\\t%0,%b1
xiy\\t%0,%b1
xc\\t%O0(1,%R0),%1" xc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "SI,SS")]) [(set_attr "op_type" "SI,SIY,SS")])
;; ;;
...@@ -5239,13 +5369,12 @@ ...@@ -5239,13 +5369,12 @@
(define_insn "sqrtdf2" (define_insn "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "=f,f") [(set (match_operand:DF 0 "register_operand" "=f,f")
(sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))] (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
sqdbr\\t%0,%1 sqdbr\\t%0,%1
sqdb\\t%0,%1" sqdb\\t%0,%1"
[(set_attr "op_type" "RRE,RSE") [(set_attr "op_type" "RRE,RXE")])
(set_attr "type" "fsqrtd")])
; ;
; sqrtsf2 instruction pattern(s). ; sqrtsf2 instruction pattern(s).
...@@ -5253,13 +5382,12 @@ ...@@ -5253,13 +5382,12 @@
(define_insn "sqrtsf2" (define_insn "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "=f,f") [(set (match_operand:SF 0 "register_operand" "=f,f")
(sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))] (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"@ "@
sqebr\\t%0,%1 sqebr\\t%0,%1
sqeb\\t%0,%1" sqeb\\t%0,%1"
[(set_attr "op_type" "RRE,RSE") [(set_attr "op_type" "RRE,RXE")])
(set_attr "type" "fsqrts")])
;; ;;
;;- One complement instructions. ;;- One complement instructions.
...@@ -5796,7 +5924,7 @@ ...@@ -5796,7 +5924,7 @@
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(match_operand 0 "address_operand" "p") (match_operand 0 "address_operand" "U")
(pc)))] (pc)))]
"" ""
"* "*
...@@ -5848,7 +5976,7 @@ ...@@ -5848,7 +5976,7 @@
(if_then_else (if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(pc) (pc)
(match_operand 0 "address_operand" "p")))] (match_operand 0 "address_operand" "U")))]
"" ""
"* "*
{ {
...@@ -5961,7 +6089,7 @@ ...@@ -5961,7 +6089,7 @@
(if_then_else (if_then_else
(ne (match_operand:SI 1 "register_operand" "d,d") (ne (match_operand:SI 1 "register_operand" "d,d")
(const_int 1)) (const_int 1))
(match_operand 0 "address_operand" "p,p") (match_operand 0 "address_operand" "U,U")
(pc))) (pc)))
(set (match_operand:SI 2 "register_operand" "=1,?*m*d") (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
(plus:SI (match_dup 1) (const_int -1))) (plus:SI (match_dup 1) (const_int -1)))
...@@ -6037,7 +6165,7 @@ ...@@ -6037,7 +6165,7 @@
(if_then_else (if_then_else
(ne (match_operand:DI 1 "register_operand" "d,d") (ne (match_operand:DI 1 "register_operand" "d,d")
(const_int 1)) (const_int 1))
(match_operand 0 "address_operand" "p,p") (match_operand 0 "address_operand" "U,U")
(pc))) (pc)))
(set (match_operand:DI 2 "register_operand" "=1,?*m*d") (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
(plus:DI (match_dup 1) (const_int -1))) (plus:DI (match_dup 1) (const_int -1)))
...@@ -6116,7 +6244,7 @@ ...@@ -6116,7 +6244,7 @@
; ;
(define_insn "indirect_jump" (define_insn "indirect_jump"
[(set (pc) (match_operand 0 "address_operand" "p"))] [(set (pc) (match_operand 0 "address_operand" "U"))]
"" ""
"* "*
{ {
...@@ -6136,7 +6264,7 @@ ...@@ -6136,7 +6264,7 @@
; ;
(define_insn "casesi_jump" (define_insn "casesi_jump"
[(set (pc) (match_operand 0 "address_operand" "p")) [(set (pc) (match_operand 0 "address_operand" "U"))
(use (label_ref (match_operand 1 "" "")))] (use (label_ref (match_operand 1 "" "")))]
"" ""
"* "*
...@@ -6342,7 +6470,7 @@ ...@@ -6342,7 +6470,7 @@
(set_attr "atype" "agen")]) (set_attr "atype" "agen")])
(define_insn "bas_64" (define_insn "bas_64"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p")) [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n")) (match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:DI 2 "register_operand" "=r"))] (clobber (match_operand:DI 2 "register_operand" "=r"))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -6351,7 +6479,7 @@ ...@@ -6351,7 +6479,7 @@
(set_attr "type" "jsr")]) (set_attr "type" "jsr")])
(define_insn "bas_31" (define_insn "bas_31"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p")) [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
(match_operand:SI 1 "const_int_operand" "n")) (match_operand:SI 1 "const_int_operand" "n"))
(clobber (match_operand:SI 2 "register_operand" "=r"))] (clobber (match_operand:SI 2 "register_operand" "=r"))]
"!TARGET_64BIT" "!TARGET_64BIT"
...@@ -6468,7 +6596,7 @@ ...@@ -6468,7 +6596,7 @@
(define_insn "bas_r_64" (define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df") [(set (match_operand 0 "register_operand" "=df")
(call (mem:QI (match_operand:QI 1 "address_operand" "p")) (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n"))) (match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r"))] (clobber (match_operand:DI 3 "register_operand" "=r"))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -6478,7 +6606,7 @@ ...@@ -6478,7 +6606,7 @@
(define_insn "bas_r_31" (define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df") [(set (match_operand 0 "register_operand" "=df")
(call (mem:QI (match_operand:QI 1 "address_operand" "p")) (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n"))) (match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r"))] (clobber (match_operand:SI 3 "register_operand" "=r"))]
"!TARGET_64BIT" "!TARGET_64BIT"
...@@ -6542,13 +6670,15 @@ ...@@ -6542,13 +6670,15 @@
[(set_attr "op_type" "RXE")]) [(set_attr "op_type" "RXE")])
(define_insn "*tls_load_31" (define_insn "*tls_load_31"
[(set (match_operand:SI 0 "register_operand" "=d") [(set (match_operand:SI 0 "register_operand" "=d,d")
(unspec:SI [(match_operand:SI 1 "memory_operand" "m") (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
(match_operand:SI 2 "" "")] (match_operand:SI 2 "" "")]
UNSPEC_TLS_LOAD))] UNSPEC_TLS_LOAD))]
"!TARGET_64BIT" "!TARGET_64BIT"
"l\\t%0,%1%J2" "@
[(set_attr "op_type" "RX")]) l\\t%0,%1%J2
ly\\t%0,%1%J2"
[(set_attr "op_type" "RX,RXY")])
(define_expand "call_value_tls" (define_expand "call_value_tls"
[(set (match_operand 0 "" "") [(set (match_operand 0 "" "")
...@@ -6648,7 +6778,7 @@ ...@@ -6648,7 +6778,7 @@
(define_insn "bas_tls_64" (define_insn "bas_tls_64"
[(set (match_operand 0 "register_operand" "=df") [(set (match_operand 0 "register_operand" "=df")
(call (mem:QI (match_operand:QI 1 "address_operand" "p")) (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n"))) (match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:DI 3 "register_operand" "=r")) (clobber (match_operand:DI 3 "register_operand" "=r"))
(use (match_operand:DI 4 "" ""))] (use (match_operand:DI 4 "" ""))]
...@@ -6660,7 +6790,7 @@ ...@@ -6660,7 +6790,7 @@
(define_insn "bas_tls_31" (define_insn "bas_tls_31"
[(set (match_operand 0 "register_operand" "=df") [(set (match_operand 0 "register_operand" "=df")
(call (mem:QI (match_operand:QI 1 "address_operand" "p")) (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
(match_operand:SI 2 "const_int_operand" "n"))) (match_operand:SI 2 "const_int_operand" "n")))
(clobber (match_operand:SI 3 "register_operand" "=r")) (clobber (match_operand:SI 3 "register_operand" "=r"))
(use (match_operand:SI 4 "" ""))] (use (match_operand:SI 4 "" ""))]
......
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