Commit d1fe6168 by Peter Barada Committed by Bernardo Innocenti

m68k.h (EXTRA_CONSTRAINT): add 'U' for register offset addressing.

	* config/m68k/m68k.h(EXTRA_CONSTRAINT): add 'U' for register offset
	addressing.
	* config/m68k/m68k.md: Add 'U,U' alternative to ColdFire variants of
	movsi,movhi,movqi insn patterns.

From-SVN: r82420
parent 803cb0b5
2004-05-29 Peter Barada <peter@the-baradas.com>
* config/m68k/m68k.h(EXTRA_CONSTRAINT): add 'U' for register offset
addressing.
* config/m68k/m68k.md: Add 'U,U' alternative to ColdFire variants of
movsi,movhi,movqi insn patterns.
2005-05-28 Andrew Pinski <pinskia@physics.uc.edu> 2005-05-28 Andrew Pinski <pinskia@physics.uc.edu>
* c-semantics.c (emit_local_var): Remove code for DECL_INITIAL. * c-semantics.c (emit_local_var): Remove code for DECL_INITIAL.
......
...@@ -735,7 +735,8 @@ extern enum reg_class regno_reg_class[]; ...@@ -735,7 +735,8 @@ extern enum reg_class regno_reg_class[];
`Q' means address register indirect addressing mode. `Q' means address register indirect addressing mode.
`S' is for operands that satisfy 'm' when -mpcrel is in effect. `S' is for operands that satisfy 'm' when -mpcrel is in effect.
`T' is for operands that satisfy 's' when -mpcrel is not in effect. */ `T' is for operands that satisfy 's' when -mpcrel is not in effect.
`U' is for register offset addressing. */
#define EXTRA_CONSTRAINT(OP,CODE) \ #define EXTRA_CONSTRAINT(OP,CODE) \
(((CODE) == 'S') \ (((CODE) == 'S') \
...@@ -755,7 +756,13 @@ extern enum reg_class regno_reg_class[]; ...@@ -755,7 +756,13 @@ extern enum reg_class regno_reg_class[];
? (GET_CODE (OP) == MEM \ ? (GET_CODE (OP) == MEM \
&& GET_CODE (XEXP (OP, 0)) == REG) \ && GET_CODE (XEXP (OP, 0)) == REG) \
: \ : \
0))) (((CODE) == 'U') \
? (GET_CODE (OP) == MEM \
&& GET_CODE (XEXP (OP, 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
&& GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
: \
0))))
/* Given an rtx X being reloaded into a reg required to be /* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use. in class CLASS, return the class of reg to actually use.
......
...@@ -676,8 +676,8 @@ ...@@ -676,8 +676,8 @@
}) })
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g") [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:SI 1 "general_operand" "g,r<Q>"))] (match_operand:SI 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE" "TARGET_COLDFIRE"
"* return output_move_simode (operands);") "* return output_move_simode (operands);")
...@@ -706,8 +706,8 @@ ...@@ -706,8 +706,8 @@
"* return output_move_himode (operands);") "* return output_move_himode (operands);")
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g") [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:HI 1 "general_operand" "g,r<Q>"))] (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE" "TARGET_COLDFIRE"
"* return output_move_himode (operands);") "* return output_move_himode (operands);")
...@@ -742,8 +742,8 @@ ...@@ -742,8 +742,8 @@
"* return output_move_qimode (operands);") "* return output_move_qimode (operands);")
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a") [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
(match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))] (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
"TARGET_COLDFIRE" "TARGET_COLDFIRE"
"* return output_move_qimode (operands);") "* return output_move_qimode (operands);")
......
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