Skip to content

R
riscv-gcc-1
Commit d19fb8e3 by Nick Clifton Committed by Nick Clifton
Options

Add support for XScale target 

Add support for StrongARM target

From-SVN: r37984
parent accc8668
Showing with 516 additions and 11 deletions
gcc/ChangeLog
2000-12-03 Nick Clifton <nickc@redhat.com>
* config.gcc: Add support for StrongARM targets.
* config/arm/t-strongarm-elf: New file.
* config/arm/t-strongarm-coff: New file.
* config/arm/t-strongarm-pe: New file.
* config/arm/strongarm-pe.h: New file.
2000-12-03 Nick Clifton <nickc@redhat.com>
* NEWS: Mention XScale has been added.
* config.gcc: Add support for XScale targets.
* config/arm/arm.h: Add support for XScale processor.
* config/arm/arm.c: Add support for XScale processor.
* config/arm/arm.md: Add support for XScale processor.
* config/arm/t-xscale-elf: New file.
* config/arm/t-xscale-coff: New file.
* config/arm/xscale-elf.h: New file.
* config/arm/xscale-coff.h: New file.
2000-12-03 Richard Henderson <rth@redhat.com>
* bb-reorder.c (reorder_basic_blocks): Don't check for EH edges
......
gcc/config.gcc
......@@ -213,6 +213,9 @@ strongarm*-*-*)
arm*-*-*)
cpu_type=arm
;;
xscale-*-*)
cpu_type=arm
;;
c*-convex-*)
cpu_type=convex
;;
......@@ -3114,6 +3117,28 @@ sparc64-*-linux*) # 64-bit Sparc's running GNU/Linux
fi
float_format=sparc
;;
strongarm-*-elf*)
tm_file=arm/strongarm-elf.h
tmake_file=arm/t-strongarm-elf
out_file=arm/arm.c
xm_file=arm/xm-arm.h
md_file=arm/arm.md
;;
strongarm-*-coff*)
tm_file=arm/strongarm-coff.h
tmake_file=arm/t-strongarm-coff
out_file=arm/arm.c
xm_file=arm/xm-arm.h
md_file=arm/arm.md
;;
strongarm-*-pe)
tm_file=arm/strongarm-pe.h
tmake_file=arm/t-strongarm-pe
out_file=arm/arm.c
xm_file=arm/xm-arm.h
md_file=arm/arm.md
extra_objs=pe.o
;;
thumb*-*-*)
{ echo "config.gcc: error:
*** The Thumb targets have been deprecated. The equivalent
......@@ -3185,6 +3210,20 @@ we32k-att-sysv*)
xm_file="${xm_file} xm-svr3"
use_collect2=yes
;;
xscale-*-elf)
tm_file=arm/xscale-elf.h
tmake_file=arm/t-xscale-elf
out_file=arm/arm.c
xm_file=arm/xm-arm.h
md_file=arm/arm.md
;;
xscale-*-coff)
tm_file=arm/xscale-coff.h
tmake_file=arm/t-xscale-coff
out_file=arm/arm.c
xm_file=arm/xm-arm.h
md_file=arm/arm.md
;;
*)
echo "Configuration $machine not supported" 1>&2
exit 1
......@@ -3280,6 +3319,7 @@ arm*-*-*)
xarm[236789] | xarm250 | xarm[67][01]0 \
| xarm7m | xarm7dm | xarm7dmi | xarm[79]tdmi \
| xarm7100 | xarm7500 | xarm7500fe | xarm810 \
| xxscale \
| xstrongarm | xstrongarm110 | xstrongarm1100)
target_cpu_default2="TARGET_CPU_$with_cpu"
;;
......
gcc/config/arm/arm-protos.h
......@@ -197,6 +197,12 @@ extern void arm_mark_dllexport PARAMS ((tree));
extern void arm_mark_dllimport PARAMS ((tree));
#endif
extern void arm_init_builtins PARAMS ((void));
#if defined (TREE_CODE) && defined (RTX_CODE)
extern rtx arm_expand_builtin PARAMS ((tree, rtx, rtx,
enum machine_mode, int));
#endif
#ifdef _C_PRAGMA_H /* included from code that cares about pragmas */
extern void arm_pr_long_calls PARAMS ((cpp_reader *));
extern void arm_pr_no_long_calls PARAMS ((cpp_reader *));
......
gcc/config/arm/arm.h
......@@ -48,6 +48,7 @@ Boston, MA 02111-1307, USA. */
#define TARGET_CPU_strongarm1100 0x0040
#define TARGET_CPU_arm9 0x0080
#define TARGET_CPU_arm9tdmi 0x0080
#define TARGET_CPU_xscale 0x0100
/* Configure didn't specify. */
#define TARGET_CPU_generic 0x8000
......@@ -115,12 +116,16 @@ extern int current_function_anonymous_args;
#if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
#else
#if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
#else
Unrecognized value in TARGET_CPU_DEFAULT.
#endif
#endif
#endif
#endif
#endif
#endif
#ifndef CPP_PREDEFINES
#define CPP_PREDEFINES "-Acpu=arm -Amachine=arm"
......@@ -161,6 +166,8 @@ Unrecognized value in TARGET_CPU_DEFAULT.
%{march=strongarm:-D__ARM_ARCH_4__} \
%{march=strongarm110:-D__ARM_ARCH_4__} \
%{march=strongarm1100:-D__ARM_ARCH_4__} \
%{march=xscale:-D__ARM_ARCH_5TE__} \
%{march=xscale:-D__XSCALE__} \
%{march=armv2:-D__ARM_ARCH_2__} \
%{march=armv2a:-D__ARM_ARCH_2__} \
%{march=armv3:-D__ARM_ARCH_3__} \
......@@ -198,6 +205,8 @@ Unrecognized value in TARGET_CPU_DEFAULT.
%{mcpu=strongarm:-D__ARM_ARCH_4__} \
%{mcpu=strongarm110:-D__ARM_ARCH_4__} \
%{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
%{mcpu=xscale:-D__ARM_ARCH_5TE__} \
%{mcpu=xscale:-D__XSCALE__} \
%{!mcpu*:%(cpp_cpu_arch_default)}} \
"
......@@ -560,6 +569,9 @@ extern int thumb_code;
/* Nonzero if this chip is a StrongARM. */
extern int arm_is_strong;
/* Nonzero if this chip is an XScale. */
extern int arm_is_xscale;
/* Nonzero if this chip is a an ARM6 or an ARM7. */
extern int arm_is_6_or_7;
......@@ -696,9 +708,12 @@ extern int arm_is_6_or_7;
#define BIGGEST_ALIGNMENT 32
/* Make strings word-aligned so strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
((TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
value set in previous versions of this toolchain was 8, which produces more
......@@ -2063,7 +2078,7 @@ typedef struct
|| (GET_CODE (X) == CONST \
&& GET_CODE (XEXP ((X), 0)) == PLUS \
&& GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
&& GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT))) \
&& GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
goto LABEL; \
else if ((MODE) == TImode) \
; \
......@@ -2355,6 +2370,9 @@ typedef struct
in one reasonably fast instruction. */
#define MOVE_MAX 4
#undef MOVE_RATIO
#define MOVE_RATIO (arm_is_xscale ? 4 : 2)
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
#define WORD_REGISTER_OPERATIONS
......@@ -2924,4 +2942,20 @@ extern int making_const_table;
#define SPECIAL_MODE_PREDICATES \
"cc_register", "dominant_cc_register",
enum arm_builtins
{
ARM_BUILTIN_CLZ,
ARM_BUILTIN_PREFETCH,
ARM_BUILTIN_MAX
};
#define MD_INIT_BUILTINS \
do \
{ \
arm_init_builtins (); \
} \
while (0)
#define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \
arm_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE))
#endif /* __ARM_H__ */
gcc/config/arm/arm.md
......@@ -69,6 +69,11 @@
; scheduling decisions for the load unit and the multiplier.
(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_is_strong")))
;; Operand number of an input operand that is shifted. Zero if the
;; given instruction does not shift one of its input operands.
(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_is_xscale")))
(define_attr "shift" "" (const_int 0))
; Floating Point Unit. If we only have floating point emulation, then there
; is no point in scheduling the floating point insns. (Well, for best
; performance we should try and group them together).
......@@ -291,6 +296,18 @@
(define_function_unit "core" 1 0
(and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) 2 1)
;; We do not need to conditionalize the define_function_unit immediately
;; above. This one will be ignored for anything other than xscale
;; compiles and for xscale compiles it provides a larger delay
;; and the scheduler will DTRT.
;; FIXME: this test needs to be revamped to not depend on this feature
;; of the scheduler.
(define_function_unit "core" 1 0
(and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load"))
(eq_attr "is_xscale" "yes"))
3 1)
(define_function_unit "core" 1 0
(and (eq_attr "ldsched" "!yes") (eq_attr "type" "load,store1")) 2 2)
......@@ -1121,7 +1138,7 @@
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
(mult:SI (match_dup 2) (match_dup 1)))]
"TARGET_ARM"
"TARGET_ARM && !arm_is_xscale"
"mul%?s\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
......@@ -1134,7 +1151,7 @@
(match_operand:SI 1 "s_register_operand" "%?r,0"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r"))]
"TARGET_ARM"
"TARGET_ARM && !arm_is_xscale"
"mul%?s\\t%0, %2, %1"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
......@@ -1165,7 +1182,7 @@
(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
(plus:SI (mult:SI (match_dup 2) (match_dup 1))
(match_dup 3)))]
"TARGET_ARM"
"TARGET_ARM && !arm_is_xscale"
"mla%?s\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
......@@ -1180,7 +1197,7 @@
(match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
"TARGET_ARM"
"TARGET_ARM && !arm_is_xscale"
"mla%?s\\t%0, %2, %1, %3"
[(set_attr "conds" "set")
(set_attr "type" "mult")]
......@@ -1226,7 +1243,7 @@
;; Unnamed template to match long long unsigned multiply-accumlate (umlal)
(define_insn "*umulsidi3adddi"
[(set (match_operand:DI 0 "s_register_operand" "=&r")
[(set (match_operand:DI 0 "s_register_operand" "+&r")
(plus:DI
(mult:DI
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
......@@ -1268,6 +1285,41 @@
(set_attr "predicable" "yes")]
)
(define_insn "mulhisi3"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(mult:SI (sign_extend:SI
(match_operand:HI 1 "s_register_operand" "%r"))
(sign_extend:SI
(match_operand:HI 2 "s_register_operand" "r"))))]
"TARGET_ARM && arm_is_xscale"
"smulbb%?\\t%0,%1,%2"
[(set_attr "type" "mult")]
)
(define_insn "*mulhisi3addsi"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_operand:SI 1 "s_register_operand" "r")
(mult:SI (sign_extend:SI
(match_operand:HI 2 "s_register_operand" "%r"))
(sign_extend:SI
(match_operand:HI 3 "s_register_operand" "r")))))]
"TARGET_ARM && arm_is_xscale"
"smlabb%?\\t%0,%2,%3,%1"
[(set_attr "type" "mult")]
)
(define_insn "*mulhidi3adddi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
(plus:DI
(match_operand:DI 1 "s_register_operand" "0")
(mult:DI (sign_extend:DI
(match_operand:HI 2 "s_register_operand" "%r"))
(sign_extend:DI
(match_operand:HI 3 "s_register_operand" "r")))))]
"TARGET_ARM && arm_is_xscale"
"smlalbb%?\\t%Q0, %R0, %2, %3"
[(set_attr "type" "mult")])
(define_insn "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(mult:SF (match_operand:SF 1 "s_register_operand" "f")
......@@ -2003,6 +2055,7 @@
"TARGET_ARM"
"bic%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
]
)
......@@ -2503,6 +2556,7 @@
"TARGET_ARM"
"mov%?\\t%0, %1%S3"
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
]
)
......@@ -2517,6 +2571,7 @@
"TARGET_ARM"
"mov%?s\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
]
)
......@@ -2530,6 +2585,7 @@
"TARGET_ARM"
"mov%?s\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
]
)
......@@ -2541,6 +2597,7 @@
"TARGET_ARM"
"mvn%?\\t%0, %1%S3"
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
]
)
......@@ -2555,6 +2612,7 @@
"TARGET_ARM"
"mvn%?s\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
]
)
......@@ -2568,6 +2626,7 @@
"TARGET_ARM"
"mvn%?s\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
]
)
......@@ -2713,6 +2772,7 @@
cmp\\t%0, #0\;rsblt\\t%0, %0, #0
eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
[(set_attr "conds" "clob,*")
(set_attr "shift" "1")
;; predicable can't be set based on the variant, so left as no
(set_attr "length" "8")]
)
......@@ -2726,6 +2786,7 @@
cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
[(set_attr "conds" "clob,*")
(set_attr "shift" "1")
;; predicable can't be set based on the variant, so left as no
(set_attr "length" "8")]
)
......@@ -3056,6 +3117,7 @@
return \"mov%?\\t%R0, %Q0, asr #31\";
"
[(set_attr "length" "8")
(set_attr "shift" "1")
(set_attr "predicable" "yes")]
)
......@@ -5471,6 +5533,7 @@
"TARGET_ARM"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
]
)
......@@ -5483,6 +5546,7 @@
"TARGET_ARM"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
]
)
......@@ -5495,6 +5559,7 @@
"TARGET_ARM"
"cmn%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
]
)
......@@ -6728,6 +6793,7 @@
"TARGET_ARM"
"%i1%?\\t%0, %2, %4%S3"
[(set_attr "predicable" "yes")
(set_attr "shift" "4")
]
)
......@@ -6745,6 +6811,7 @@
"TARGET_ARM"
"%i1%?s\\t%0, %2, %4%S3"
[(set_attr "conds" "set")
(set_attr "shift" "4")
]
)
......@@ -6760,6 +6827,7 @@
"TARGET_ARM"
"%i1%?s\\t%0, %2, %4%S3"
[(set_attr "conds" "set")
(set_attr "shift" "4")
]
)
......@@ -6772,6 +6840,7 @@
"TARGET_ARM"
"sub%?\\t%0, %1, %3%S2"
[(set_attr "predicable" "yes")
(set_attr "shift" "3")
]
)
......@@ -6789,6 +6858,7 @@
"TARGET_ARM"
"sub%?s\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
]
)
......@@ -6804,6 +6874,7 @@
"TARGET_ARM"
"sub%?s\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
]
)
......@@ -6848,12 +6919,13 @@
(plus:SI (plus:SI (match_op_dup 5 [(match_dup 3) (match_dup 4)])
(match_dup 1))
(match_dup 2)))]
"TARGET_ARM && reload_in_progress"
"TARGET_ARM && reload_in_progress && !arm_is_xscale"
"*
output_add_immediate (operands);
return \"add%?s\\t%0, %0, %3%S5\";
"
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "length" "20")]
)
......@@ -6868,12 +6940,13 @@
(match_operand:SI 2 "const_int_operand" "n"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=&r"))]
"TARGET_ARM && reload_in_progress"
"TARGET_ARM && reload_in_progress && !arm_is_xscale"
"*
output_add_immediate (operands);
return \"add%?s\\t%0, %0, %3%S5\";
"
[(set_attr "conds" "set")
(set_attr "shift" "3")
(set_attr "length" "20")]
)
......@@ -6908,7 +6981,7 @@
(set (match_operand:SI 0 "" "=&r")
(plus:SI (plus:SI (mult:SI (match_dup 3) (match_dup 4)) (match_dup 1))
(match_dup 2)))]
"TARGET_ARM && reload_in_progress"
"TARGET_ARM && reload_in_progress && !arm_is_xscale"
"*
output_add_immediate (operands);
output_asm_insn (\"mla%?s\\t%0, %3, %4, %0\", operands);
......@@ -7615,6 +7688,7 @@
mov%D5\\t%0, %1\;mov%d5\\t%0, %2%S4
mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4"
[(set_attr "conds" "use")
(set_attr "shift" "2")
(set_attr "length" "4,8,8")]
)
......@@ -7650,6 +7724,7 @@
mov%d5\\t%0, %1\;mov%D5\\t%0, %2%S4
mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4"
[(set_attr "conds" "use")
(set_attr "shift" "2")
(set_attr "length" "4,8,8")]
)
......@@ -7686,6 +7761,7 @@
"TARGET_ARM"
"mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7"
[(set_attr "conds" "use")
(set_attr "shift" "1")
(set_attr "length" "8")]
)
......@@ -8912,6 +8988,22 @@
[(set_attr "length" "2")]
)
;; V5 Instructions,
(define_insn "clz"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] 128))]
"TARGET_ARM"
"clz\\t%0,%1")
;; XScale instructions.
(define_insn "prefetch"
[(unspec_volatile
[(match_operand:SI 0 "offsettable_memory_operand" "o")] 129)]
"TARGET_ARM"
"pld\\t%0")
;; General predication pattern
(define_cond_exec
......
gcc/config/arm/strongarm-pe.h 0 → 100644
/* Definitions of target machine for GNU compiler, for ARM with PE obj format.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#include "arm/strongarm-coff.h"
#include "arm/pe.h"
#undef TARGET_VERSION
#define TARGET_VERSION fputs (" (StrongARM/PE)", stderr);
gcc/config/arm/t-strongarm-coff 0 → 100644
CROSS_LIBGCC1 = libgcc1-asm.a
LIB1ASMSRC = arm/lib1funcs.asm
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
echo '#ifndef __ARMEB__' >> fp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
echo '#endif' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
echo '#ifndef __ARMEB__' > dp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c
echo '#endif' >> dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
MULTILIB_OPTIONS = mlittle-endian/mbig-endian mhard-float/msoft-float
MULTILIB_DIRNAMES = le be fpu soft
MULTILIB_MATCHES =
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# Currently there is a bug somwehere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in libgcc1.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
gcc/config/arm/t-strongarm-elf 0 → 100644
CROSS_LIBGCC1 = libgcc1-asm.a
LIB1ASMSRC = arm/lib1funcs.asm
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
echo '#ifndef __ARMEB__' >> fp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
echo '#endif' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
echo '#ifndef __ARMEB__' > dp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c
echo '#endif' >> dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
MULTILIB_OPTIONS = mlittle-endian/mbig-endian mhard-float/msoft-float
MULTILIB_DIRNAMES = le be fpu soft
MULTILIB_EXCEPTIONS =
MULTILIB_MATCHES = mbig-endian=mbe mlittle-endian=mle
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
# If EXTRA_MULTILIB_PARTS is not defined above then define EXTRA_PARTS here
# EXTRA_PARTS = crtbegin.o crtend.o
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in libgcc1.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
gcc/config/arm/t-strongarm-pe 0 → 100644
CROSS_LIBGCC1 = libgcc1-asm.a
LIB1ASMSRC = arm/lib1funcs.asm
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
echo '#ifndef __ARMEB__' >> fp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
echo '#endif' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
echo '#ifndef __ARMEB__' > dp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c
echo '#endif' >> dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
pe.o: $(srcdir)/config/arm/pe.c
$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/arm/pe.c
MULTILIB_OPTIONS = mhard-float/msoft-float
MULTILIB_DIRNAMES = fpu soft
MULTILIB_MATCHES =
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# Currently there is a bug somwehere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in libgcc1.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
gcc/config/arm/t-xscale-coff 0 → 100644
CROSS_LIBGCC1 = libgcc1-asm.a
LIB1ASMSRC = arm/lib1funcs.asm
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func _call_via_rX _interwork_call_via_rX
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
echo '#ifndef __ARMEB__' >> fp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
echo '#endif' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
echo '#ifndef __ARMEB__' > dp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c
echo '#endif' >> dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
MULTILIB_OPTIONS = mlittle-endian/mbig-endian
MULTILIB_DIRNAMES = le be
MULTILIB_EXCEPTIONS =
MULTILIB_MATCHES = mbig-endian=mbe mlittle-endian=mle
# Note XScale does not support 26 bit APCS.
# Note XScale does not support hard FP
MULTILIB_OPTIONS += mno-thumb-interwork/mthumb-interwork
MULTILIB_DIRNAMES += normal interwork
MULTILIB_OPTIONS += marm/mthumb
MULTILIB_DIRNAMES += arm thumb
MULTILIB_EXCEPTIONS += *mhard-float/*mthumb*
# CYGNUS LOCAL nickc/redundant multilibs
MULTILIB_REDUNDANT_DIRS = interwork/thumb=thumb
# END CYGNUS LOCAL
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in libgcc1.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
gcc/config/arm/t-xscale-elf 0 → 100644
CROSS_LIBGCC1 = libgcc1-asm.a
LIB1ASMSRC = arm/lib1funcs.asm
LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func _call_via_rX _interwork_call_via_rX
# We want fine grained libraries, so use the new code to build the
# floating point emulation libraries.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
echo '#ifndef __ARMEB__' >> fp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
echo '#endif' >> fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
echo '#ifndef __ARMEB__' > dp-bit.c
echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c
echo '#endif' >> dp-bit.c
cat $(srcdir)/config/fp-bit.c >> dp-bit.c
MULTILIB_OPTIONS = mlittle-endian/mbig-endian
MULTILIB_DIRNAMES = le be
MULTILIB_EXCEPTIONS =
MULTILIB_MATCHES = mbig-endian=mbe mlittle-endian=mle
# Note XScale does not support 26 bit APCS.
# Note XScale does not support hard FP
MULTILIB_OPTIONS += mno-thumb-interwork/mthumb-interwork
MULTILIB_DIRNAMES += normal interwork
MULTILIB_OPTIONS += marm/mthumb
MULTILIB_DIRNAMES += arm thumb
MULTILIB_EXCEPTIONS += *mhard-float/*mthumb*
# CYGNUS LOCAL nickc/redundant multilibs
MULTILIB_REDUNDANT_DIRS = interwork/thumb=thumb
# END CYGNUS LOCAL
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
# Currently there is a bug somewhere in GCC's alias analysis
# or scheduling code that is breaking _fpmul_parts in libgcc1.c.
# Disabling function inlining is a workaround for this problem.
TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline
gcc/config/arm/xscale-coff.h 0 → 100644
/* Definitions for XScale systems using COFF
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
Contributed by Catherine Moore <clm@cygnus.com>
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* Run-time Target Specification. */
#ifndef SUBTARGET_CPU_DEFAULT
#define SUBTARGET_CPU_DEFAULT TARGET_CPU_xscale
#endif
#define SUBTARGET_EXTRA_ASM_SPEC "%{!mcpu=*:-mxscale}"
#define MULTILIB_DEFAULTS \
{ "mlittle-endian", "mno-thumb-interwork", "marm" }
#include "coff.h"
#undef TARGET_VERSION
#define TARGET_VERSION fputs (" (XScale/COFF)", stderr);
gcc/config/arm/xscale-elf.h 0 → 100644
/* Definitions for XScale architectures using ELF
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
Contributed by Catherine Moore <clm@cygnus.com>
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* Run-time Target Specification. */
#ifndef TARGET_VERSION
#define TARGET_VERSION fputs (" (XScale/ELF non-Linux)", stderr);
#endif
#ifndef SUBTARGET_CPU_DEFAULT
#define SUBTARGET_CPU_DEFAULT TARGET_CPU_xscale
#endif
#define SUBTARGET_EXTRA_ASM_SPEC "%{!mcpu=*:-mxscale}"
#ifndef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS \
{ "mlittle-endian", "mno-thumb-interwork", "marm" }
#endif
#include "unknown-elf.h"
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment