mips.h (PROCESSOR_R4130): New processor_type.

	* config/mips/mips.h (PROCESSOR_R4130): New processor_type.
	(TARGET_MIPS4130): New macro.
	(ISA_HAS_MACC): Return true if TARGET_MIPS4130 && !TARGET_MIPS16.
	* config/mips/mips.c (mips_cpu_info_table): Add a vr4130 entry.
	(override_options): Extend MIPS_MARCH_CONTROLS_SOFT_FLOAT to deal
	with PROCESSOR_R4130.
	* config/mips/mips.md (define_attr cpu): Add r4130.
	* doc/invoke.texi: Document vr4130 as a supported MIPS architecture.

From-SVN: r79904

gcc/ChangeLog

+2004-03-24  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/mips/mips.h (PROCESSOR_R4130): New processor_type.
+	(TARGET_MIPS4130): New macro.
+	(ISA_HAS_MACC): Return true if TARGET_MIPS4130 && !TARGET_MIPS16.
+	* config/mips/mips.c (mips_cpu_info_table): Add a vr4130 entry.
+	(override_options): Extend MIPS_MARCH_CONTROLS_SOFT_FLOAT to deal
+	with PROCESSOR_R4130.
+	* config/mips/mips.md (define_attr cpu): Add r4130.
+	* doc/invoke.texi: Document vr4130 as a supported MIPS architecture.
+
 2004-03-24  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 	    Richard Sandiford  <rsandifo@redhat.com>
 

gcc/config/mips/mips.c

@@ -646,6 +646,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
   { "vr4100", PROCESSOR_R4100, 3 },
   { "vr4111", PROCESSOR_R4111, 3 },
   { "vr4120", PROCESSOR_R4120, 3 },
+  { "vr4130", PROCESSOR_R4130, 3 },
   { "vr4300", PROCESSOR_R4300, 3 },
   { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
   { "r4600", PROCESSOR_R4600, 3 },
@@ -4657,6 +4658,7 @@ override_options (void)
 	case PROCESSOR_R4100:
 	case PROCESSOR_R4111:
 	case PROCESSOR_R4120:
+	case PROCESSOR_R4130:
 	  target_flags |= MASK_SOFT_FLOAT;
 	  break;
 

gcc/config/mips/mips.h

@@ -57,6 +57,7 @@ enum processor_type {
   PROCESSOR_R4100,
   PROCESSOR_R4111,
   PROCESSOR_R4120,
+  PROCESSOR_R4130,
   PROCESSOR_R4300,
   PROCESSOR_R4600,
   PROCESSOR_R4650,
@@ -321,6 +322,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
 #define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
 #define TARGET_MIPS4120             (mips_arch == PROCESSOR_R4120)
+#define TARGET_MIPS4130             (mips_arch == PROCESSOR_R4130)
 #define TARGET_MIPS5400             (mips_arch == PROCESSOR_R5400)
 #define TARGET_MIPS5500             (mips_arch == PROCESSOR_R5500)
 #define TARGET_MIPS7000             (mips_arch == PROCESSOR_R7000)
@@ -883,6 +885,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 /* ISA has three operand multiply instructions that  the result
    from a 4th operand and puts the result in an accumulator.  */
 #define ISA_HAS_MACC            ((TARGET_MIPS4120 && !TARGET_MIPS16)	\
+                                 || (TARGET_MIPS4130 && !TARGET_MIPS16)	\
                                  || TARGET_MIPS5400                     \
                                  || TARGET_MIPS5500                     \
                                  || TARGET_SR71K                        \

gcc/config/mips/mips.md

@@ -219,7 +219,7 @@
 ;; Attribute describing the processor.  This attribute must match exactly
 ;; with the processor_type enumeration in mips.h.
 (define_attr "cpu"
-  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
+  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
   (const (symbol_ref "mips_tune")))
 
 ;; The type of hardware hazard associated with this instruction.

gcc/doc/invoke.texi

@@ -7757,7 +7757,7 @@ The processor names are:
 @samp{rm9000},
 @samp{orion},
 @samp{sb1},
-@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4300},
+@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
 @samp{vr5000}, @samp{vr5400} and @samp{vr5500}.
 The special value @samp{from-abi} selects the
 most compatible architecture for the selected ABI (that is,