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re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to… 

re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv)

	PR target/83467
	* config/i386/i386.md (*ashl<mode>3_mask): Add operand
	constraints to operand 2.
	(*ashl<mode>3_mask_1): Ditto.
	(*<shift_insn><mode>3_mask): Ditto.
	(*<shift_insn><mode>3_mask_1): Ditto.
	(*<rotate_insn><mode>3_mask): Ditto.
	(*<rotate_insn><mode>3_mask_1): Ditto.

testsuite/ChangeLog:

	PR target/83467
	* gcc.target/i386/pr83467-1.c: New test.
	* gcc.target/i386/pr83467-2.c: Ditto.

From-SVN: r255949
parent 056cf434
Showing with 74 additions and 18 deletions
gcc/ChangeLog
2017-12-21 Uros Bizjak <ubizjak@gmail.com>
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*ashl<mode>3_mask_1): Ditto.
(*<shift_insn><mode>3_mask): Ditto.
(*<shift_insn><mode>3_mask_1): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask_1): Ditto.
2017-12-21 Alexandre Oliva <aoliva@redhat.com>
* reorg.c (make_return_insns): Reemit each insn with its own
location.
* reorg.c (make_return_insns): Reemit each insn with its own location.
2017-12-21 Alexandre Oliva <aoliva@redhat.com>
......@@ -1606,7 +1616,8 @@
2017-12-20 Tom de Vries <tom@codesourcery.com>
PR middle-end/83423
* config/i386/i386.c (ix86_static_chain): Move DECL_STATIC_CHAIN test ...
* config/i386/i386.c (ix86_static_chain): Move
DECL_STATIC_CHAIN test ...
* calls.c (rtx_for_static_chain): ... here. New function.
* calls.h (rtx_for_static_chain): Declare.
* builtins.c (expand_builtin_setjmp_receiver): Use rtx_for_static_chain
......@@ -1712,7 +1723,8 @@
* sched-rgn.c (sched_rgn_init): Likewise.
* diagnostic-show-locus.c (layout::show_ruler): Likewise.
* combine.c (find_split_point, simplify_if_then_else, force_to_mode,
if_then_else_cond, simplify_shift_const_1, simplify_comparison): Likewise.
if_then_else_cond, simplify_shift_const_1, simplify_comparison):
Likewise.
* explow.c (eliminate_constant_term): Likewise.
* final.c (leaf_renumber_regs_insn): Likewise.
* cfgrtl.c (print_rtl_with_bb): Likewise.
......@@ -2343,7 +2355,8 @@
2017-12-15 Julia Koval <julia.koval@intel.com>
* config/i386/i386-builtin.def (__builtin_ia32_vaesenclast_v16qi,
__builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi): New.
__builtin_ia32_vaesenclast_v32qi, __builtin_ia32_vaesenclast_v64qi):
New.
* config/i386/sse.md (vaesenclast_<mode>): New pattern.
* config/i386/vaesintrin.h (_mm256_aesenclast_epi128,
_mm512_aesenclast_epi128, _mm_aesenclast_epi128): New intrinsics.
......@@ -2359,7 +2372,8 @@
2017-12-15 Julia Koval <julia.koval@intel.com>
* config/i386/i386-builtin.def (__builtin_ia32_vaesdeclast_v16qi,
__builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi): New.
__builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi):
New.
* config/i386/sse.md (vaesdeclast_<mode>): New pattern.
* config/i386/vaesintrin.h (_mm256_aesdeclast_epi128,
_mm512_aesdeclast_epi128, _mm_aesdeclast_epi128): New intrinsics.
......@@ -2453,8 +2467,7 @@
PR tree-optimization/83418
* vr-values.c (vr_values::extract_range_for_var_from_comparison_expr):
Instead of asserting we don't get unfolded comparisons deal with
them.
Instead of asserting we don't get unfolded comparisons deal with them.
2017-12-14 Jakub Jelinek <jakub@redhat.com>
gcc/config/i386/i386.md
......@@ -10353,7 +10353,7 @@
(match_operand:SWI48 1 "nonimmediate_operand")
(subreg:QI
(and:SI
(match_operand:SI 2 "register_operand")
(match_operand:SI 2 "register_operand" "c,r")
(match_operand:SI 3 "const_int_operand")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
......@@ -10367,14 +10367,15 @@
(ashift:SWI48 (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = gen_lowpart (QImode, operands[2]);")
"operands[2] = gen_lowpart (QImode, operands[2]);"
[(set_attr "isa" "*,bmi2")])
(define_insn_and_split "*ashl<mode>3_mask_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand")
(ashift:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
(and:QI
(match_operand:QI 2 "register_operand")
(match_operand:QI 2 "register_operand" "c,r")
(match_operand:QI 3 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFT, <MODE>mode, operands)
......@@ -10387,7 +10388,9 @@
[(set (match_dup 0)
(ashift:SWI48 (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])])
(clobber (reg:CC FLAGS_REG))])]
""
[(set_attr "isa" "*,bmi2")])
(define_insn "*bmi2_ashl<mode>3_1"
[(set (match_operand:SWI48 0 "register_operand" "=r")
......@@ -10873,7 +10876,7 @@
(match_operand:SWI48 1 "nonimmediate_operand")
(subreg:QI
(and:SI
(match_operand:SI 2 "register_operand")
(match_operand:SI 2 "register_operand" "c,r")
(match_operand:SI 3 "const_int_operand")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
......@@ -10887,14 +10890,15 @@
(any_shiftrt:SWI48 (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"operands[2] = gen_lowpart (QImode, operands[2]);")
"operands[2] = gen_lowpart (QImode, operands[2]);"
[(set_attr "isa" "*,bmi2")])
(define_insn_and_split "*<shift_insn><mode>3_mask_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand")
(any_shiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
(and:QI
(match_operand:QI 2 "register_operand")
(match_operand:QI 2 "register_operand" "c,r")
(match_operand:QI 3 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
......@@ -10907,7 +10911,9 @@
[(set (match_dup 0)
(any_shiftrt:SWI48 (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])])
(clobber (reg:CC FLAGS_REG))])]
""
[(set_attr "isa" "*,bmi2")])
(define_insn_and_split "*<shift_insn><mode>3_doubleword"
[(set (match_operand:DWI 0 "register_operand" "=&r")
......@@ -11352,7 +11358,7 @@
(match_operand:SWI48 1 "nonimmediate_operand")
(subreg:QI
(and:SI
(match_operand:SI 2 "register_operand")
(match_operand:SI 2 "register_operand" "c")
(match_operand:SI 3 "const_int_operand")) 0)))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
......@@ -11373,7 +11379,7 @@
(any_rotate:SWI48
(match_operand:SWI48 1 "nonimmediate_operand")
(and:QI
(match_operand:QI 2 "register_operand")
(match_operand:QI 2 "register_operand" "c")
(match_operand:QI 3 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
......
gcc/testsuite/ChangeLog
2017-12-21 Uros Bizjak <ubizjak@gmail.com>
PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.
2017-12-21 Alexandre Oliva <aoliva@redhat.com>
PR debug/83419
......
gcc/testsuite/gcc.target/i386/pr83467-1.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -flive-range-shrinkage -m8bit-idiv" } */
/* { dg-require-effective-target int128 } */
unsigned a;
__int128
b (unsigned c, short d, int e, long f, unsigned __int128 g, char h,
int i, __int128 j)
{
j %= 5;
c *= i;
e = e >> (g & 31);
h &= e /= d;
g <<= 0 <= 0;
g &= h < j;
return c + d + f + g + h + i + a + j;
}
gcc/testsuite/gcc.target/i386/pr83467-2.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -flive-range-shrinkage" } */
/* { dg-require-effective-target int128 } */
int
a (int b, short c, int d, long e, __int128 f, short g, long h, __int128 i)
{
d <<= f & 31;
f >>= 127;
g *= d > c;
f >>= g;
return b + e + f + h + i;
}
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