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riscv-gcc-1
Commit ca7f5001 by Richard Kenner
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Update define_function_units. 

Put both old and new mnemonics in all templates.
Add target tests to pattern conditional field throughout.
(one_cmplsi2): Make POWER and PowerPC variants.
(mulsi3): Convert to define_expand which calls appropriate POWER or PowerPC
pattern.
(divsi3, udivsi3): Add patterns for PowerPC case.  Update divsi3 define_expand
for PowerPC case.
(ashlsi3, lshrsi3, ashrsi3, extendqisi2, extendqihi2): Convert to
define_expand which calls appropriate POWER or PowerPC pattern.
(floating-point): Add PowerPC single-precision FP, and SF/DF sqrt insns for
603, 604, 620.
(call insns): Use "nop" for magic TOC restore.
(move data, nop): Use PowerPC extended mnemonics.

From-SVN: r5748
parent 85638c0d
Showing with 914 additions and 408 deletions
gcc/config/rs6000/rs6000.md
...@@ -67,21 +67,31 @@ ...@@ -67,21 +67,31 @@
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "imul") (and (eq_attr "type" "imul")
(eq_attr "cpu" "rios1,rios2")) (eq_attr "cpu" "rios1"))
3 0) 3 0)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "imul") (and (eq_attr "type" "imul")
(eq_attr "cpu" "rios2"))
2 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "imul")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
5 0) 5 0)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv") (and (eq_attr "type" "idiv")
(eq_attr "cpu" "rios1,rios2")) (eq_attr "cpu" "rios1"))
19 0) 19 0)
(define_function_unit "iu" 1 0 (define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv") (and (eq_attr "type" "idiv")
(eq_attr "cpu" "rios2"))
13 0)
(define_function_unit "iu" 1 0
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620")) (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
36 0) 36 0)
...@@ -176,12 +186,22 @@ ...@@ -176,12 +186,22 @@
(define_function_unit "fpu2" 2 0 (define_function_unit "fpu2" 2 0
(and (eq_attr "type" "sdiv") (and (eq_attr "type" "sdiv")
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
19 0) 17 0)
(define_function_unit "fpu2" 2 0 (define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ddiv") (and (eq_attr "type" "ddiv")
(eq_attr "cpu" "rios2")) (eq_attr "cpu" "rios2"))
19 0) 17 0)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "ssqrt")
(eq_attr "cpu" "rios2"))
26 0)
(define_function_unit "fpu2" 2 0
(and (eq_attr "type" "dsqrt")
(eq_attr "cpu" "rios2"))
26 0)
;; Start with fixed-point load and store insns. Here we put only the more ;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later. ;; complex forms. Basic data transfer is done later.
...@@ -198,7 +218,7 @@ ...@@ -198,7 +218,7 @@
"" ""
"@ "@
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
rlinm %0,%1,0,0xff" {rlinm|rlwinm} %0,%1,0,0xff"
[(set_attr "type" "load,*")]) [(set_attr "type" "load,*")])
(define_insn "" (define_insn ""
...@@ -207,7 +227,7 @@ ...@@ -207,7 +227,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 2 "=r"))] (clobber (match_scratch:SI 2 "=r"))]
"" ""
"andil. %2,%1,0xff" "{andil.|andi.} %2,%1,0xff"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
...@@ -217,7 +237,7 @@ ...@@ -217,7 +237,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_dup 1)))] (zero_extend:SI (match_dup 1)))]
"" ""
"andil. %0,%1,0xff" "{andil.|andi.} %0,%1,0xff"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_expand "zero_extendqihi2" (define_expand "zero_extendqihi2"
...@@ -232,7 +252,7 @@ ...@@ -232,7 +252,7 @@
"" ""
"@ "@
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
rlinm %0,%1,0,0xff" {rlinm|rlwinm} %0,%1,0,0xff"
[(set_attr "type" "load,*")]) [(set_attr "type" "load,*")])
(define_expand "zero_extendhisi2" (define_expand "zero_extendhisi2"
...@@ -247,7 +267,7 @@ ...@@ -247,7 +267,7 @@
"" ""
"@ "@
lhz%U1%X1 %0,%1 lhz%U1%X1 %0,%1
rlinm %0,%1,0,0xffff" {rlinm|rlwinm} %0,%1,0,0xffff"
[(set_attr "type" "load,*")]) [(set_attr "type" "load,*")])
(define_insn "" (define_insn ""
...@@ -256,7 +276,7 @@ ...@@ -256,7 +276,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 2 "=r"))] (clobber (match_scratch:SI 2 "=r"))]
"" ""
"andil. %2,%1,0xffff" "{andil.|andi.} %2,%1,0xffff"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
...@@ -266,7 +286,7 @@ ...@@ -266,7 +286,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_dup 1)))] (zero_extend:SI (match_dup 1)))]
"" ""
"andil. %0,%1,0xffff" "{andil.|andi.} %0,%1,0xffff"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_expand "extendhisi2" (define_expand "extendhisi2"
...@@ -281,7 +301,7 @@ ...@@ -281,7 +301,7 @@
"" ""
"@ "@
lha%U1%X1 %0,%1 lha%U1%X1 %0,%1
exts %0,%1" {exts|extsh} %0,%1"
[(set_attr "type" "load,*")]) [(set_attr "type" "load,*")])
(define_insn "" (define_insn ""
...@@ -290,7 +310,7 @@ ...@@ -290,7 +310,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 2 "=r"))] (clobber (match_scratch:SI 2 "=r"))]
"" ""
"exts. %2,%1" "{exts.|extsh.} %2,%1"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
...@@ -300,7 +320,7 @@ ...@@ -300,7 +320,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(sign_extend:SI (match_dup 1)))] (sign_extend:SI (match_dup 1)))]
"" ""
"exts. %0,%1" "{exts.|extsh.} %0,%1"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
;; Fixed-point arithmetic insns. ;; Fixed-point arithmetic insns.
...@@ -310,8 +330,8 @@ ...@@ -310,8 +330,8 @@
(match_operand:SI 2 "add_operand" "rI,J")))] (match_operand:SI 2 "add_operand" "rI,J")))]
"" ""
"@ "@
a%I2 %0,%1,%2 {a%I2|add%I2c} %0,%1,%2
cau %0,%1,%u2") {cau|addis} %0,%1,%u2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -320,7 +340,7 @@ ...@@ -320,7 +340,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"a%I2. %3,%1,%2" "{a%I2.|add%I2c.} %3,%1,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
...@@ -331,7 +351,7 @@ ...@@ -331,7 +351,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"" ""
"a%I2. %0,%1,%2" "{a%I2.|add%I2c.} %0,%1,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
;; Split an add that we can't do in one insn into two insns, each of which ;; Split an add that we can't do in one insn into two insns, each of which
...@@ -357,18 +377,49 @@ ...@@ -357,18 +377,49 @@
operands[4] = gen_rtx (CONST_INT, VOIDmode, low); operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
}") }")
(define_insn "one_cmplsi2" (define_expand "one_cmplsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"" ""
"sfi %0,%1,-1") "")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_POWER"
"{sfi|subfic} %0,%1,-1")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"! TARGET_POWER"
"nor %0,%1,%1")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 2 "=r"))]
""
"nor. %2,%1,%1"
[(set_attr "type" "compare")])
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=-x")
(compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(not:SI (match_dup 1)))]
""
"nor. %0,%2,%1"
[(set_attr "type" "compare")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
(match_operand:SI 2 "gpc_reg_operand" "r")))] (match_operand:SI 2 "gpc_reg_operand" "r")))]
"" ""
"sf%I1 %0,%2,%1") "{sf%I1|subf%I1c} %0,%2,%1")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -377,7 +428,7 @@ ...@@ -377,7 +428,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"sf. %3,%2,%1" "{sf.|subfc.} %3,%2,%1"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_insn "" (define_insn ""
...@@ -388,7 +439,7 @@ ...@@ -388,7 +439,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))] (minus:SI (match_dup 1) (match_dup 2)))]
"" ""
"sf. %0,%2,%1" "{sf.|subfc.} %0,%2,%1"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_expand "subsi3" (define_expand "subsi3"
...@@ -419,7 +470,7 @@ ...@@ -419,7 +470,7 @@
(minus:SI (match_dup 2) (match_dup 1)))) (minus:SI (match_dup 2) (match_dup 1))))
(set (match_operand:SI 0 "gpc_reg_operand" "") (set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 3)))] (minus:SI (match_dup 2) (match_dup 3)))]
"" "TARGET_POWER"
" "
{ operands[3] = gen_reg_rtx (SImode); }") { operands[3] = gen_reg_rtx (SImode); }")
...@@ -428,7 +479,7 @@ ...@@ -428,7 +479,7 @@
(smin:SI (match_operand:SI 1 "gpc_reg_operand" "") (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))) (match_operand:SI 2 "reg_or_short_operand" "")))
(clobber (match_operand:SI 3 "gpc_reg_operand" ""))] (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
"" "TARGET_POWER"
[(set (match_dup 3) [(set (match_dup 3)
(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
(const_int 0) (const_int 0)
...@@ -444,7 +495,7 @@ ...@@ -444,7 +495,7 @@
(minus:SI (match_dup 2) (match_dup 1)))) (minus:SI (match_dup 2) (match_dup 1))))
(set (match_operand:SI 0 "gpc_reg_operand" "") (set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 3) (match_dup 1)))] (plus:SI (match_dup 3) (match_dup 1)))]
"" "TARGET_POWER"
" "
{ operands[3] = gen_reg_rtx (SImode); }") { operands[3] = gen_reg_rtx (SImode); }")
...@@ -453,7 +504,7 @@ ...@@ -453,7 +504,7 @@
(smax:SI (match_operand:SI 1 "gpc_reg_operand" "") (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_short_operand" ""))) (match_operand:SI 2 "reg_or_short_operand" "")))
(clobber (match_operand:SI 3 "gpc_reg_operand" ""))] (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
"" "TARGET_POWER"
[(set (match_dup 3) [(set (match_dup 3)
(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
(const_int 0) (const_int 0)
...@@ -471,7 +522,7 @@ ...@@ -471,7 +522,7 @@
(minus:SI (match_dup 4) (match_dup 3)))) (minus:SI (match_dup 4) (match_dup 3))))
(set (match_operand:SI 0 "gpc_reg_operand" "") (set (match_operand:SI 0 "gpc_reg_operand" "")
(minus:SI (match_dup 2) (match_dup 3)))] (minus:SI (match_dup 2) (match_dup 3)))]
"" "TARGET_POWER"
" "
{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
...@@ -485,7 +536,7 @@ ...@@ -485,7 +536,7 @@
(minus:SI (match_dup 4) (match_dup 3)))) (minus:SI (match_dup 4) (match_dup 3))))
(set (match_operand:SI 0 "gpc_reg_operand" "") (set (match_operand:SI 0 "gpc_reg_operand" "")
(plus:SI (match_dup 3) (match_dup 1)))] (plus:SI (match_dup 3) (match_dup 1)))]
"" "TARGET_POWER"
" "
{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
...@@ -495,7 +546,7 @@ ...@@ -495,7 +546,7 @@
(match_operand:SI 2 "reg_or_short_operand" "rI")) (match_operand:SI 2 "reg_or_short_operand" "rI"))
(const_int 0) (const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))] (minus:SI (match_dup 2) (match_dup 1))))]
"" "TARGET_POWER"
"doz%I2 %0,%1,%2") "doz%I2 %0,%1,%2")
(define_insn "" (define_insn ""
...@@ -507,7 +558,7 @@ ...@@ -507,7 +558,7 @@
(minus:SI (match_dup 2) (match_dup 1))) (minus:SI (match_dup 2) (match_dup 1)))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" "TARGET_POWER"
"doz%I2. %3,%1,%2" "doz%I2. %3,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
...@@ -523,7 +574,7 @@ ...@@ -523,7 +574,7 @@
(if_then_else:SI (gt (match_dup 1) (match_dup 2)) (if_then_else:SI (gt (match_dup 1) (match_dup 2))
(const_int 0) (const_int 0)
(minus:SI (match_dup 2) (match_dup 1))))] (minus:SI (match_dup 2) (match_dup 1))))]
"" "TARGET_POWER"
"doz%I2. %0,%1,%2" "doz%I2. %0,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
...@@ -532,13 +583,13 @@ ...@@ -532,13 +583,13 @@
(define_insn "abssi2" (define_insn "abssi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"" "TARGET_POWER"
"abs %0,%1") "abs %0,%1")
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
"" "TARGET_POWER"
"nabs %0,%1") "nabs %0,%1")
(define_insn "negsi2" (define_insn "negsi2"
...@@ -570,18 +621,42 @@ ...@@ -570,18 +621,42 @@
[(set (match_operand:SI 0 "register_operand" "=&r") [(set (match_operand:SI 0 "register_operand" "=&r")
(ffs:SI (match_operand:SI 1 "register_operand" "r")))] (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
"" ""
"neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32" "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;{sfi|subfic} %0,%0,32"
[(set_attr "length" "16")]) [(set_attr "length" "16")])
(define_insn "mulsi3" (define_expand "mulsi3"
[(use (match_operand:SI 0 "gpc_reg_operand" ""))
(use (match_operand:SI 1 "gpc_reg_operand" ""))
(use (match_operand:SI 2 "reg_or_short_operand" ""))]
""
"
{
if (TARGET_POWER)
emit_insn (gen_mulsi3_power (operands[0], operands[1], operands[2]));
else
emit_insn (gen_mulsi3_powerpc (operands[0], operands[1], operands[2]));
DONE;
}")
(define_insn "mulsi3_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I"))) (match_operand:SI 2 "reg_or_short_operand" "r,I")))
(clobber (match_scratch:SI 3 "=q,q"))] (clobber (match_scratch:SI 3 "=q,q"))]
"" "TARGET_POWER"
"@
{muls|mullw} %0,%1,%2
{muli|mulli} %0,%1,%2"
[(set_attr "type" "imul")])
(define_insn "mulsi3_powerpc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,I")))]
"TARGET_POWERPC"
"@ "@
muls %0,%1,%2 mullw %0,%1,%2
muli %0,%1,%2" mulli %0,%1,%2"
[(set_attr "type" "imul")]) [(set_attr "type" "imul")])
(define_insn "" (define_insn ""
...@@ -591,8 +666,18 @@ ...@@ -591,8 +666,18 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r")) (clobber (match_scratch:SI 3 "=r"))
(clobber (match_scratch:SI 4 "=q"))] (clobber (match_scratch:SI 4 "=q"))]
"" "TARGET_POWER"
"muls. %3,%1,%2" "{muls.|mullw.} %3,%1,%2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"TARGET_POWERPC"
"mullw. %3,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -603,8 +688,19 @@ ...@@ -603,8 +688,19 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(mult:SI (match_dup 1) (match_dup 2))) (mult:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q"))] (clobber (match_scratch:SI 4 "=q"))]
"" "TARGET_POWER"
"muls. %0,%1,%2" "{muls.|mullw.} %0,%1,%2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(mult:SI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC"
"mullw. %0,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
;; Operand 1 is divided by operand 2; quotient goes to operand ;; Operand 1 is divided by operand 2; quotient goes to operand
...@@ -617,12 +713,29 @@ ...@@ -617,12 +713,29 @@
(match_operand:SI 2 "gpc_reg_operand" "r"))) (match_operand:SI 2 "gpc_reg_operand" "r")))
(set (match_operand:SI 3 "gpc_reg_operand" "=q") (set (match_operand:SI 3 "gpc_reg_operand" "=q")
(mod:SI (match_dup 1) (match_dup 2)))] (mod:SI (match_dup 1) (match_dup 2)))]
"" "TARGET_POWER"
"divs %0,%1,%2" "divs %0,%1,%2"
[(set_attr "type" "idiv")]) [(set_attr "type" "idiv")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC"
"divw %0, %1, %2"
[(set_attr "type" "idiv")])
(define_insn "udivsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC"
"divwu %0, %1, %2"
[(set_attr "type" "idiv")])
;; For powers of two we can do srai/aze for divide and then adjust for ;; For powers of two we can do srai/aze for divide and then adjust for
;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used. ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
;; used; for PowerPC, force operands into register and do a normal divide.
(define_expand "divsi3" (define_expand "divsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "") [(set (match_operand:SI 0 "gpc_reg_operand" "")
(div:SI (match_operand:SI 1 "gpc_reg_operand" "") (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
...@@ -630,9 +743,15 @@ ...@@ -630,9 +743,15 @@
"" ""
" "
{ {
if (GET_CODE (operands[2]) != CONST_INT if (GET_CODE (operands[2]) == CONST_INT
|| exact_log2 (INTVAL (operands[2])) < 0) && exact_log2 (INTVAL (operands[2])) >= 0)
;
else if (TARGET_POWER)
FAIL; FAIL;
else if (TARGET_POWERPC)
operands[2] = force_reg (SImode, operands[2]);
}") }")
(define_expand "modsi3" (define_expand "modsi3"
...@@ -661,7 +780,7 @@ ...@@ -661,7 +780,7 @@
(div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "N")))] (match_operand:SI 2 "const_int_operand" "N")))]
"exact_log2 (INTVAL (operands[2])) >= 0" "exact_log2 (INTVAL (operands[2])) >= 0"
"srai %0,%1,%p2\;aze %0,%0" "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -670,7 +789,7 @@ ...@@ -670,7 +789,7 @@
(match_operand:SI 2 "const_int_operand" "N"))) (match_operand:SI 2 "const_int_operand" "N")))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"exact_log2 (INTVAL (operands[2])) >= 0" "exact_log2 (INTVAL (operands[2])) >= 0"
"srai %3,%1,%p2\;aze. %3,%3" "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -681,7 +800,7 @@ ...@@ -681,7 +800,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(div:SI (match_dup 1) (match_dup 2)))] (div:SI (match_dup 1) (match_dup 2)))]
"exact_log2 (INTVAL (operands[2])) >= 0" "exact_log2 (INTVAL (operands[2])) >= 0"
"srai %0,%1,%p2\;aze. %0,%0" "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -700,7 +819,7 @@ ...@@ -700,7 +819,7 @@
(zero_extend:DI (match_dup 4))) (zero_extend:DI (match_dup 4)))
(match_dup 3)))] (match_dup 3)))]
"" "TARGET_POWER"
"div %0,%1,%3" "div %0,%1,%3"
[(set_attr "type" "idiv")]) [(set_attr "type" "idiv")])
...@@ -721,7 +840,7 @@ ...@@ -721,7 +840,7 @@
(const_int 32)) (const_int 32))
(zero_extend:DI (match_dup 1))) (zero_extend:DI (match_dup 1)))
(match_dup 2)))])] (match_dup 2)))])]
"" "TARGET_POWER"
" "
{ operands[4] = gen_reg_rtx (SImode); }") { operands[4] = gen_reg_rtx (SImode); }")
...@@ -737,7 +856,7 @@ ...@@ -737,7 +856,7 @@
(set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
(set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
(label_ref (match_dup 4)) (pc)))] (label_ref (match_dup 4)) (pc)))]
"" "TARGET_POWER"
" "
{ operands[5] = gen_reg_rtx (CCUNSmode); { operands[5] = gen_reg_rtx (CCUNSmode);
operands[6] = gen_reg_rtx (CCmode); operands[6] = gen_reg_rtx (CCmode);
...@@ -749,7 +868,7 @@ ...@@ -749,7 +868,7 @@
(match_operand:SI 2 "reg_or_cint_operand" ""))) (match_operand:SI 2 "reg_or_cint_operand" "")))
(set (match_operand:SI 3 "gpc_reg_operand" "") (set (match_operand:SI 3 "gpc_reg_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])] (umod:SI (match_dup 1) (match_dup 2)))])]
"" "TARGET_POWER"
" "
{ {
rtx label = 0; rtx label = 0;
...@@ -780,9 +899,9 @@ ...@@ -780,9 +899,9 @@
"" ""
"@ "@
and %0,%1,%2 and %0,%1,%2
rlinm %0,%1,0,%m2,%M2 {rlinm|rlwinm} %0,%1,0,%m2,%M2
andil. %0,%1,%b2 {andil.|andi.} %0,%1,%b2
andiu. %0,%1,%u2") {andiu.|andis.} %0,%1,%u2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
...@@ -793,9 +912,9 @@ ...@@ -793,9 +912,9 @@
"" ""
"@ "@
and. %3,%1,%2 and. %3,%1,%2
andil. %3,%1,%b2 {andil.|andi.} %3,%1,%b2
andiu. %3,%1,%u2 {andiu.|andis.} %3,%1,%u2
rlinm. %3,%1,0,%m2,%M2" {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
[(set_attr "type" "compare,compare,compare,delayed_compare")]) [(set_attr "type" "compare,compare,compare,delayed_compare")])
(define_insn "" (define_insn ""
...@@ -808,9 +927,9 @@ ...@@ -808,9 +927,9 @@
"" ""
"@ "@
and. %0,%1,%2 and. %0,%1,%2
andil. %0,%1,%b2 {andil.|andi.} %0,%1,%b2
andiu. %0,%1,%u2 {andiu.|andis.} %0,%1,%u2
rlinm. %0,%1,0,%m2,%M2" {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
[(set_attr "type" "compare,compare,compare,delayed_compare")]) [(set_attr "type" "compare,compare,compare,delayed_compare")])
;; Take a AND with a constant that cannot be done in a single insn and try to ;; Take a AND with a constant that cannot be done in a single insn and try to
...@@ -860,8 +979,8 @@ ...@@ -860,8 +979,8 @@
"" ""
"@ "@
or %0,%1,%2 or %0,%1,%2
oril %0,%1,%b2 {oril|ori} %0,%1,%b2
oriu %0,%1,%u2") {oriu|oris} %0,%1,%u2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -908,8 +1027,8 @@ ...@@ -908,8 +1027,8 @@
"" ""
"@ "@
xor %0,%1,%2 xor %0,%1,%2
xoril %0,%1,%b2 {xoril|xori} %0,%1,%b2
xoriu %0,%1,%u2") {xoriu|xoris} %0,%1,%u2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1099,7 +1218,7 @@ ...@@ -1099,7 +1218,7 @@
(match_operand:SI 1 "gpc_reg_operand" "0")) (match_operand:SI 1 "gpc_reg_operand" "0"))
(and:SI (match_dup 2) (and:SI (match_dup 2)
(match_operand:SI 3 "gpc_reg_operand" "r"))))] (match_operand:SI 3 "gpc_reg_operand" "r"))))]
"" "TARGET_POWER"
"maskir %0,%3,%2") "maskir %0,%3,%2")
(define_insn "" (define_insn ""
...@@ -1108,7 +1227,7 @@ ...@@ -1108,7 +1227,7 @@
(match_operand:SI 1 "gpc_reg_operand" "0")) (match_operand:SI 1 "gpc_reg_operand" "0"))
(and:SI (match_operand:SI 3 "gpc_reg_operand" "r") (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
(match_dup 2))))] (match_dup 2))))]
"" "TARGET_POWER"
"maskir %0,%3,%2") "maskir %0,%3,%2")
(define_insn "" (define_insn ""
...@@ -1117,7 +1236,7 @@ ...@@ -1117,7 +1236,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r")) (match_operand:SI 3 "gpc_reg_operand" "r"))
(and:SI (not:SI (match_dup 2)) (and:SI (not:SI (match_dup 2))
(match_operand:SI 1 "gpc_reg_operand" "0"))))] (match_operand:SI 1 "gpc_reg_operand" "0"))))]
"" "TARGET_POWER"
"maskir %0,%3,%2") "maskir %0,%3,%2")
(define_insn "" (define_insn ""
...@@ -1126,7 +1245,7 @@ ...@@ -1126,7 +1245,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(and:SI (not:SI (match_dup 2)) (and:SI (not:SI (match_dup 2))
(match_operand:SI 1 "gpc_reg_operand" "0"))))] (match_operand:SI 1 "gpc_reg_operand" "0"))))]
"" "TARGET_POWER"
"maskir %0,%3,%2") "maskir %0,%3,%2")
(define_insn "" (define_insn ""
...@@ -1140,7 +1259,7 @@ ...@@ -1140,7 +1259,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
(and:SI (match_dup 2) (match_dup 3))))] (and:SI (match_dup 2) (match_dup 3))))]
"" "TARGET_POWER"
"maskir. %0,%3,%2" "maskir. %0,%3,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
...@@ -1155,7 +1274,7 @@ ...@@ -1155,7 +1274,7 @@
(set (match_operand:SI 0 "register_operand" "=r") (set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
(and:SI (match_dup 3) (match_dup 2))))] (and:SI (match_dup 3) (match_dup 2))))]
"" "TARGET_POWER"
"maskir. %0,%3,%2" "maskir. %0,%3,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
...@@ -1170,7 +1289,7 @@ ...@@ -1170,7 +1289,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (match_dup 2) (match_dup 3)) (ior:SI (and:SI (match_dup 2) (match_dup 3))
(and:SI (not:SI (match_dup 2)) (match_dup 1))))] (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
"" "TARGET_POWER"
"maskir. %0,%3,%2" "maskir. %0,%3,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
...@@ -1185,7 +1304,7 @@ ...@@ -1185,7 +1304,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ior:SI (and:SI (match_dup 3) (match_dup 2)) (ior:SI (and:SI (match_dup 3) (match_dup 2))
(and:SI (not:SI (match_dup 2)) (match_dup 1))))] (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
"" "TARGET_POWER"
"maskir. %0,%3,%2" "maskir. %0,%3,%2"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
...@@ -1204,7 +1323,7 @@ ...@@ -1204,7 +1323,7 @@
operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
return \"rlimi %0,%3,%4,%h2,%h1\"; return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
}") }")
(define_insn "extzv" (define_insn "extzv"
...@@ -1222,7 +1341,7 @@ ...@@ -1222,7 +1341,7 @@
operands[3] = const0_rtx; operands[3] = const0_rtx;
else else
operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
return \"rlinm %0,%1,%3,%s2,31\"; return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
}") }")
(define_insn "" (define_insn ""
...@@ -1250,16 +1369,16 @@ ...@@ -1250,16 +1369,16 @@
((1 << (16 - (start & 15))) ((1 << (16 - (start & 15)))
- (1 << (16 - (start & 15) - size)))); - (1 << (16 - (start & 15) - size))));
if (start < 16) if (start < 16)
return \"andiu. %4,%1,%3\"; return \"{andiu.|andis.} %4,%1,%3\";
else else
return \"andil. %4,%1,%3\"; return \"{andil.|andi.} %4,%1,%3\";
} }
if (start + size >= 32) if (start + size >= 32)
operands[3] = const0_rtx; operands[3] = const0_rtx;
else else
operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
return \"rlinm. %4,%1,%3,%s2,31\"; return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
}" }"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
...@@ -1280,14 +1399,14 @@ ...@@ -1280,14 +1399,14 @@
if (start >= 16 && start + size == 32) if (start >= 16 && start + size == 32)
{ {
operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
return \"andil. %0,%1,%3\"; return \"{andil.|andi.} %0,%1,%3\";
} }
if (start + size >= 32) if (start + size >= 32)
operands[3] = const0_rtx; operands[3] = const0_rtx;
else else
operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
return \"rlinm. %0,%1,%3,%s2,31\"; return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
}" }"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
...@@ -1296,7 +1415,7 @@ ...@@ -1296,7 +1415,7 @@
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))] (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"" ""
"rl%I2nm %0,%1,%h2,0xffffffff") "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1305,7 +1424,7 @@ ...@@ -1305,7 +1424,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"rl%I2nm. %3,%1,%h2,0xffffffff" "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1316,7 +1435,7 @@ ...@@ -1316,7 +1435,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(rotate:SI (match_dup 1) (match_dup 2)))] (rotate:SI (match_dup 1) (match_dup 2)))]
"" ""
"rl%I2nm. %0,%1,%h2,0xffffffff" "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1325,7 +1444,7 @@ ...@@ -1325,7 +1444,7 @@
(match_operand:SI 2 "reg_or_cint_operand" "ri")) (match_operand:SI 2 "reg_or_cint_operand" "ri"))
(match_operand:SI 3 "mask_operand" "L")))] (match_operand:SI 3 "mask_operand" "L")))]
"" ""
"rl%I2nm %0,%1,%h2,%m3,%M3") "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1336,7 +1455,7 @@ ...@@ -1336,7 +1455,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=r"))] (clobber (match_scratch:SI 4 "=r"))]
"" ""
"rl%I2nm. %4,%1,%h2,%m3,%M3" "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1349,7 +1468,7 @@ ...@@ -1349,7 +1468,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"" ""
"rl%I2nm. %0,%1,%h2,%m3,%M3" "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1359,7 +1478,7 @@ ...@@ -1359,7 +1478,7 @@
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
"" ""
"rl%I2nm %0,%1,%h2,0xff") "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1370,7 +1489,7 @@ ...@@ -1370,7 +1489,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"rl%I2nm. %3,%1,%h2,0xff" "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1383,7 +1502,7 @@ ...@@ -1383,7 +1502,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
"" ""
"rl%I2nm. %0,%1,%h2,0xff" "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1393,7 +1512,7 @@ ...@@ -1393,7 +1512,7 @@
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
"" ""
"rl%I2nm %0,%1,%h2,0xffff") "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1404,7 +1523,7 @@ ...@@ -1404,7 +1523,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" ""
"rl%I2nm. %3,%1,%h2,0xffff" "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1417,21 +1536,43 @@ ...@@ -1417,21 +1536,43 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
"" ""
"rl%I2nm. %0,%1,%h2,0xffff" "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
;; Note that we use "sle." instead of "sl." so that we can set ;; Note that we use "sle." instead of "sl." so that we can set
;; SHIFT_COUNT_TRUNCATED. ;; SHIFT_COUNT_TRUNCATED.
(define_insn "ashlsi3" (define_expand "ashlsi3"
[(use (match_operand:SI 0 "gpc_reg_operand" ""))
(use (match_operand:SI 1 "gpc_reg_operand" ""))
(use (match_operand:SI 2 "reg_or_cint_operand" ""))]
""
"
{
if (TARGET_POWER)
emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
else
emit_insn (gen_ashlsi3_powerpc (operands[0], operands[1], operands[2]));
DONE;
}")
(define_insn "ashlsi3_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
(clobber (match_scratch:SI 3 "=q,X"))] (clobber (match_scratch:SI 3 "=q,X"))]
"" "TARGET_POWER"
"@ "@
sle %0,%1,%2 sle %0,%1,%2
sli %0,%1,%h2" {sli|slwi} %0,%1,%h2"
[(set_attr "length" "8")])
(define_insn "ashlsi3_powerpc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC"
"slw%I2 %0,%1,%2"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -1441,10 +1582,19 @@ ...@@ -1441,10 +1582,19 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r")) (clobber (match_scratch:SI 3 "=r,r"))
(clobber (match_scratch:SI 4 "=q,X"))] (clobber (match_scratch:SI 4 "=q,X"))]
"" "TARGET_POWER"
"@ "@
sle. %3,%1,%2 sle. %3,%1,%2
sli. %3,%1,%h2" {sli.|slwi.} %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"TARGET_POWERPC"
"slw%I2. %3,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1455,10 +1605,20 @@ ...@@ -1455,10 +1605,20 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashift:SI (match_dup 1) (match_dup 2))) (ashift:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q,X"))] (clobber (match_scratch:SI 4 "=q,X"))]
"" "TARGET_POWER"
"@ "@
sle. %0,%1,%2 sle. %0,%1,%2
sli. %0,%1,%h2" {sli.|slwi.} %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashift:SI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC"
"slw%I2. %0,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1467,7 +1627,7 @@ ...@@ -1467,7 +1627,7 @@
(match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L")))] (match_operand:SI 3 "mask_operand" "L")))]
"includes_lshift_p (operands[2], operands[3])" "includes_lshift_p (operands[2], operands[3])"
"rlinm %0,%h1,%h2,%m3,%M3") "{rlinm|rlwinm} %0,%h1,%h2,%m3,%M3")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1478,7 +1638,7 @@ ...@@ -1478,7 +1638,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=r"))] (clobber (match_scratch:SI 4 "=r"))]
"includes_lshift_p (operands[2], operands[3])" "includes_lshift_p (operands[2], operands[3])"
"rlinm. %4,%h1,%h2,%m3,%M3" "{rlinm.|rlwinm.} %4,%h1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1491,20 +1651,41 @@ ...@@ -1491,20 +1651,41 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_lshift_p (operands[2], operands[3])" "includes_lshift_p (operands[2], operands[3])"
"rlinm. %0,%h1,%h2,%m3,%M3" "{rlinm.|rlwinm.} %0,%h1,%h2,%m3,%M3"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
;; "sli x,x,0". ;; "sli x,x,0".
(define_insn "lshrsi3" (define_expand "lshrsi3"
[(use (match_operand:SI 0 "gpc_reg_operand" ""))
(use (match_operand:SI 1 "gpc_reg_operand" ""))
(use (match_operand:SI 2 "reg_or_cint_operand" ""))]
""
"
{
if (TARGET_POWER)
emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
else
emit_insn (gen_lshrsi3_powerpc (operands[0], operands[1], operands[2]));
DONE;
}")
(define_insn "lshrsi3_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
(clobber (match_scratch:SI 3 "=q,X"))] (clobber (match_scratch:SI 3 "=q,X"))]
"" "TARGET_POWER"
"@ "@
sre %0,%1,%2 sre %0,%1,%2
s%A2i %0,%1,%h2") {s%A2i|s%A2wi} %0,%1,%h2")
(define_insn "lshrsi3_powerpc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC"
"srw%I2 %0,%1,%2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x") [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
...@@ -1513,10 +1694,20 @@ ...@@ -1513,10 +1694,20 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r")) (clobber (match_scratch:SI 3 "=r,r"))
(clobber (match_scratch:SI 4 "=q,X"))] (clobber (match_scratch:SI 4 "=q,X"))]
"" "TARGET_POWER"
"@ "@
sre. %3,%1,%2 sre. %3,%1,%2
s%A2i. %3,%1,%h2" {s%A2i.|s%A2wi.} %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"TARGET_POWERPC"
"srw%I2. %3,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1527,10 +1718,21 @@ ...@@ -1527,10 +1718,21 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(lshiftrt:SI (match_dup 1) (match_dup 2))) (lshiftrt:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q,X"))] (clobber (match_scratch:SI 4 "=q,X"))]
"" "TARGET_POWER"
"@ "@
sre. %0,%1,%2 sre. %0,%1,%2
s%A2i. %0,%1,%h2" {s%A2i.|s%A2wi.} %0,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC"
"srw%I2. %0,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1539,7 +1741,7 @@ ...@@ -1539,7 +1741,7 @@
(match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 2 "const_int_operand" "i"))
(match_operand:SI 3 "mask_operand" "L")))] (match_operand:SI 3 "mask_operand" "L")))]
"includes_rshift_p (operands[2], operands[3])" "includes_rshift_p (operands[2], operands[3])"
"rlinm %0,%1,%s2,%m3,%M3") "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1550,7 +1752,7 @@ ...@@ -1550,7 +1752,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=r"))] (clobber (match_scratch:SI 4 "=r"))]
"includes_rshift_p (operands[2], operands[3])" "includes_rshift_p (operands[2], operands[3])"
"rlinm. %4,%1,%s2,%m3,%M3" "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1563,7 +1765,7 @@ ...@@ -1563,7 +1765,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
"includes_rshift_p (operands[2], operands[3])" "includes_rshift_p (operands[2], operands[3])"
"rlinm. %0,%1,%s2,%m3,%M3" "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1573,7 +1775,7 @@ ...@@ -1573,7 +1775,7 @@
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))] (match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm %0,%1,%s2,0xff") "{rlinm|rlwinm} %0,%1,%s2,0xff")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1585,7 +1787,7 @@ ...@@ -1585,7 +1787,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm. %3,%1,%s2,0xff" "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1599,7 +1801,7 @@ ...@@ -1599,7 +1801,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
"rlinm. %0,%1,%s2,0xff" "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1609,7 +1811,7 @@ ...@@ -1609,7 +1811,7 @@
(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")) 0)))] (match_operand:SI 2 "const_int_operand" "i")) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm %0,%1,%s2,0xffff") "{rlinm|rlwinm} %0,%1,%s2,0xffff")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x") [(set (match_operand:CC 0 "cc_reg_operand" "=x")
...@@ -1621,7 +1823,7 @@ ...@@ -1621,7 +1823,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm. %3,%1,%s2,0xffff" "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1635,7 +1837,7 @@ ...@@ -1635,7 +1837,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
"includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
"rlinm. %0,%1,%s2,0xffff" "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1644,7 +1846,7 @@ ...@@ -1644,7 +1846,7 @@
(match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 1 "gpc_reg_operand" "r"))
(ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 31)))] (const_int 31)))]
"" "TARGET_POWER"
"rrib %0,%1,%2") "rrib %0,%1,%2")
(define_insn "" (define_insn ""
...@@ -1653,7 +1855,7 @@ ...@@ -1653,7 +1855,7 @@
(match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:SI 1 "gpc_reg_operand" "r"))
(lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 31)))] (const_int 31)))]
"" "TARGET_POWER"
"rrib %0,%1,%2") "rrib %0,%1,%2")
(define_insn "" (define_insn ""
...@@ -1663,18 +1865,39 @@ ...@@ -1663,18 +1865,39 @@
(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
(const_int 1) (const_int 1)
(const_int 0)))] (const_int 0)))]
"" "TARGET_POWER"
"rrib %0,%1,%2") "rrib %0,%1,%2")
(define_insn "ashrsi3" (define_expand "ashrsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "reg_or_cint_operand" "")))]
""
"
{
if (TARGET_POWER)
emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
else
emit_insn (gen_ashrsi3_powerpc (operands[0], operands[1], operands[2]));
DONE;
}")
(define_insn "ashrsi3_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
(clobber (match_scratch:SI 3 "=q,X"))] (clobber (match_scratch:SI 3 "=q,X"))]
"" "TARGET_POWER"
"@ "@
srea %0,%1,%2 srea %0,%1,%2
srai %0,%1,%h2") {srai|srawi} %0,%1,%h2")
(define_insn "ashrsi3_powerpc"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC"
"sraw%I2 %0,%1,%2")
(define_insn "" (define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x") [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
...@@ -1683,10 +1906,20 @@ ...@@ -1683,10 +1906,20 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=r,r")) (clobber (match_scratch:SI 3 "=r,r"))
(clobber (match_scratch:SI 4 "=q,X"))] (clobber (match_scratch:SI 4 "=q,X"))]
"" "TARGET_POWER"
"@ "@
srea. %3,%1,%2 srea. %3,%1,%2
srai. %3,%1,%h2" {srai.|srawi.} %3,%1,%h2"
[(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r"))]
"TARGET_POWERPC"
"sraw%I2. %3,%1,%2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn "" (define_insn ""
...@@ -1697,13 +1930,37 @@ ...@@ -1697,13 +1930,37 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ashiftrt:SI (match_dup 1) (match_dup 2))) (ashiftrt:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 4 "=q,X"))] (clobber (match_scratch:SI 4 "=q,X"))]
"" "TARGET_POWER"
"@ "@
srea. %0,%1,%2 srea. %0,%1,%2
srai. %0,%1,%h2" srai. %0,%1,%h2"
[(set_attr "type" "delayed_compare")]) [(set_attr "type" "delayed_compare")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x")
(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
"TARGET_POWERPC"
"sraw%I2. %0,%1,%2"
[(set_attr "type" "delayed_compare")])
(define_expand "extendqisi2" (define_expand "extendqisi2"
[(use (match_operand:SI 0 "gpc_reg_operand" ""))
(use (match_operand:QI 1 "gpc_reg_operand" ""))]
""
"
{
if (TARGET_POWER)
emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
else
emit_insn (gen_extendqisi2_powerpc (operands[0], operands[1]));
DONE;
}")
(define_expand "extendqisi2_power"
[(parallel [(set (match_dup 2) [(parallel [(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(const_int 24))) (const_int 24)))
...@@ -1712,12 +1969,37 @@ ...@@ -1712,12 +1969,37 @@
(ashiftrt:SI (match_dup 2) (ashiftrt:SI (match_dup 2)
(const_int 24))) (const_int 24)))
(clobber (scratch:SI))])] (clobber (scratch:SI))])]
"" "TARGET_POWER"
"
{ operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_reg_rtx (SImode); }")
(define_expand "extendqisi2_powerpc"
[(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(const_int 24)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 2)
(const_int 24)))]
"TARGET_POWERPC"
" "
{ operands[1] = gen_lowpart (SImode, operands[1]); { operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_reg_rtx (SImode); }") operands[2] = gen_reg_rtx (SImode); }")
(define_expand "extendqihi2" (define_expand "extendqihi2"
[(use (match_operand:HI 0 "gpc_reg_operand" ""))
(use (match_operand:QI 1 "gpc_reg_operand" ""))]
""
"
{
if (TARGET_POWER)
emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
else
emit_insn (gen_extendqihi2_powerpc (operands[0], operands[1]));
DONE;
}")
(define_expand "extendqihi2_power"
[(parallel [(set (match_dup 2) [(parallel [(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(const_int 24))) (const_int 24)))
...@@ -1726,7 +2008,20 @@ ...@@ -1726,7 +2008,20 @@
(ashiftrt:SI (match_dup 2) (ashiftrt:SI (match_dup 2)
(const_int 24))) (const_int 24)))
(clobber (scratch:SI))])] (clobber (scratch:SI))])]
"" "TARGET_POWER"
"
{ operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
operands[2] = gen_reg_rtx (SImode); }")
(define_expand "extendqihi2_powerpc"
[(set (match_dup 2)
(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
(const_int 24)))
(set (match_operand:HI 0 "gpc_reg_operand" "")
(ashiftrt:SI (match_dup 2)
(const_int 24)))]
"TARGET_POWERPC"
" "
{ operands[0] = gen_lowpart (SImode, operands[0]); { operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
...@@ -1734,10 +2029,12 @@ ...@@ -1734,10 +2029,12 @@
;; Floating-point insns, excluding normal data motion. ;; Floating-point insns, excluding normal data motion.
;; ;;
;; We pretend that we have both SFmode and DFmode insns, while, in fact, ;; PowerPC has a full set of single-precision floating point instructions.
;; all fp insns are actually done in double. The only conversions we will ;;
;; do will be when storing to memory. In that case, we will use the "frsp" ;; For the POWER architecture, we pretend that we have both SFmode and
;; instruction before storing. ;; DFmode insns, while, in fact, all fp insns are actually done in double.
;; The only conversions we will do will be when storing to memory. In that
;; case, we will use the "frsp" instruction before storing.
;; ;;
;; Note that when we store into a single-precision memory location, we need to ;; Note that when we store into a single-precision memory location, we need to
;; use the frsp insn first. If the register being stored isn't dead, we ;; use the frsp insn first. If the register being stored isn't dead, we
...@@ -1787,36 +2084,96 @@ ...@@ -1787,36 +2084,96 @@
"fnabs %0,%1" "fnabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "addsf3" (define_expand "addsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))]
""
"")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER"
"{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC"
"fadds %0,%1,%2"
[(set_attr "type" "fp")])
(define_expand "subsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))]
"" ""
"fa %0,%1,%2" "")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER"
"{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "subsf3" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC"
"fsubs %0,%1,%2"
[(set_attr "type" "fp")])
(define_expand "mulsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))]
"" ""
"fs %0,%1,%2" "")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWER"
"{fm|fmul} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "mulsf3" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"" "TARGET_POWERPC"
"fm %0,%1,%2" "fmuls %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "divsf3" (define_expand "divsf3"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))]
""
"")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"" "TARGET_POWER"
"fd %0,%1,%2" "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "sdiv")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC"
"fdivs %0,%1,%2"
[(set_attr "type" "sdiv")]) [(set_attr "type" "sdiv")])
(define_insn "" (define_insn ""
...@@ -1824,8 +2181,17 @@ ...@@ -1824,8 +2181,17 @@
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"" "TARGET_POWER"
"fma %0,%1,%2,%3" "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWERPC"
"fmadds %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -1833,8 +2199,17 @@ ...@@ -1833,8 +2199,17 @@
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"" "TARGET_POWER"
"fms %0,%1,%2,%3" "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWERPC"
"fmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -1842,8 +2217,17 @@ ...@@ -1842,8 +2217,17 @@
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"" "TARGET_POWER"
"fnma %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWERPC"
"fnmadds %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
...@@ -1851,10 +2235,39 @@ ...@@ -1851,10 +2235,39 @@
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"" "TARGET_POWER"
"fnms %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWERPC"
"fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_POWERPCSQR || TARGET_POWER2"
"")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_POWERPCSQR"
"fsqrts %0,%1"
[(set_attr "type" "ssqrt")])
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_POWER2"
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
(define_insn "negdf2" (define_insn "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
...@@ -1881,7 +2294,7 @@ ...@@ -1881,7 +2294,7 @@
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"" ""
"fa %0,%1,%2" "{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "subdf3" (define_insn "subdf3"
...@@ -1889,7 +2302,7 @@ ...@@ -1889,7 +2302,7 @@
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"" ""
"fs %0,%1,%2" "{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "muldf3" (define_insn "muldf3"
...@@ -1897,7 +2310,7 @@ ...@@ -1897,7 +2310,7 @@
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"" ""
"fm %0,%1,%2" "{fm|fmul} %0,%1,%2"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
(define_insn "divdf3" (define_insn "divdf3"
...@@ -1905,7 +2318,7 @@ ...@@ -1905,7 +2318,7 @@
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f") (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"" ""
"fd %0,%1,%2" "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "ddiv")]) [(set_attr "type" "ddiv")])
(define_insn "" (define_insn ""
...@@ -1914,7 +2327,7 @@ ...@@ -1914,7 +2327,7 @@
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "f")))]
"" ""
"fma %0,%1,%2,%3" "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
(define_insn "" (define_insn ""
...@@ -1923,7 +2336,7 @@ ...@@ -1923,7 +2336,7 @@
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "f")))]
"" ""
"fms %0,%1,%2,%3" "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
(define_insn "" (define_insn ""
...@@ -1932,7 +2345,7 @@ ...@@ -1932,7 +2345,7 @@
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f"))))] (match_operand:DF 3 "gpc_reg_operand" "f"))))]
"" ""
"fnma %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
(define_insn "" (define_insn ""
...@@ -1941,8 +2354,15 @@ ...@@ -1941,8 +2354,15 @@
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f"))))] (match_operand:DF 3 "gpc_reg_operand" "f"))))]
"" ""
"fnms %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_POWERPCSQR | TARGET_POWER2"
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
;; Conversions to and from floating-point. ;; Conversions to and from floating-point.
(define_expand "floatsidf2" (define_expand "floatsidf2"
...@@ -2116,31 +2536,84 @@ ...@@ -2116,31 +2536,84 @@
;; Define the DImode operations that can be done in a small number ;; Define the DImode operations that can be done in a small number
;; of instructions. ;; of instructions.
(define_insn "adddi3" (define_expand "adddi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:DI 2 "reg_or_short_operand" "")))]
""
"
{
if (TARGET_POWERPC
&& short_cint_operand (operands[2], DImode))
FAIL;
}")
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
(match_operand:DI 2 "reg_or_short_operand" "r,I")))] (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
"" "TARGET_POWER"
"@ "@
a %L0,%L1,%L2\;ae %0,%1,%2 {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
ai %L0,%L1,%2\;a%G2e %0,%1" {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "subdi3" (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC"
"addc %L0,%L1,%L2\;adde %0,%1,%2"
[(set_attr "length" "8")])
(define_expand "subdi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
(match_operand:DI 2 "gpc_reg_operand" "r,r")))] (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
"" ""
"
{
if (TARGET_POWERPC
&& short_cint_operand (operands[1], DImode))
FAIL;
}")
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
(match_operand:DI 2 "gpc_reg_operand" "r,r")))]
"TARGET_POWER"
"@ "@
sf %L0,%L2,%L1\;sfe %0,%2,%1 {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
sfi %L0,%L2,%1\;sf%G1e %0,%2" {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "negdi2" (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC"
"subfc %L0,%L2,%L1\;subfe %0,%2,%1"
[(set_attr "length" "8")])
(define_expand "negdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r") [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
"" ""
"sfi %L0,%L1,0\;sfze %0,%1" "")
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
"TARGET_POWER"
"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
[(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
"TARGET_POWERPC"
"subfic %L0,%L1,0\;subfze %0,%1"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "mulsidi3" (define_insn "mulsidi3"
...@@ -2148,7 +2621,7 @@ ...@@ -2148,7 +2621,7 @@
(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
(clobber (match_scratch:SI 3 "=q"))] (clobber (match_scratch:SI 3 "=q"))]
"" "TARGET_POWER"
"mul %0,%1,%2\;mfmq %L0" "mul %0,%1,%2\;mfmq %L0"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
...@@ -2160,9 +2633,9 @@ ...@@ -2160,9 +2633,9 @@
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
(match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
(clobber (match_scratch:SI 3 "=X,q,q,q"))] (clobber (match_scratch:SI 3 "=X,q,q,q"))]
"" "TARGET_POWER"
"@ "@
sli %0,%L1,%h2\;cal %L0,0(0) {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
...@@ -2173,9 +2646,9 @@ ...@@ -2173,9 +2646,9 @@
(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
(match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
(clobber (match_scratch:SI 3 "=X,q,q,q"))] (clobber (match_scratch:SI 3 "=X,q,q,q"))]
"" "TARGET_POWER"
"@ "@
cal %0,0(0)\;s%A2i %L0,%1,%h2 {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
...@@ -2189,7 +2662,7 @@ ...@@ -2189,7 +2662,7 @@
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "general_operand" ""))) (match_operand:SI 2 "general_operand" "")))
(clobber (match_scratch:SI 3 ""))])] (clobber (match_scratch:SI 3 ""))])]
"" "TARGET_POWER"
" "
{ if (GET_CODE (operands[2]) != CONST_INT) { if (GET_CODE (operands[2]) != CONST_INT)
FAIL; FAIL;
...@@ -2200,9 +2673,9 @@ ...@@ -2200,9 +2673,9 @@
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "M,i"))) (match_operand:SI 2 "const_int_operand" "M,i")))
(clobber (match_scratch:SI 3 "=X,q"))] (clobber (match_scratch:SI 3 "=X,q"))]
"" "TARGET_POWER"
"@ "@
srai %0,%1,31\;srai %L0,%1,%h2 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
...@@ -2247,20 +2720,35 @@ ...@@ -2247,20 +2720,35 @@
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l,*h") [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l,*h")
(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))] (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode) "TARGET_POWER && (gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)" || gpc_reg_operand (operands[1], SImode))"
"@ "@
ai %0,%1,0 {ai|addic} %0,%1,0
l%U1%X1 %0,%1 {l%U1%X1|lwz%U1%X1} %0,%1
st%U0%X0 %1,%0 {st%U0%X0|stw%U0%X0} %1,%0
cal %0,%1(0) {cal %0,%1(0)|li %0,%1}
cau %0,0,%u1 {cau %0,0,%u1|lis %0,%u1}
mf%1 %0 mf%1 %0
mt%0 %1 mt%0 %1
mt%0 %1 mt%0 %1
cror 0,0,0" cror 0,0,0"
[(set_attr "type" "*,load,*,*,*,*,*,mtlr,*")]) [(set_attr "type" "*,load,*,*,*,*,*,mtlr,*")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h")
(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))]
"TARGET_POWERPC && (gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode))"
"@
mr %0,%1
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0
li %0,%1
lis %0,%u1
mf%1 %0
mt%0 %1"
[(set_attr "type" "*,load,*,*,*,*,*")])
;; Split a load of a large constant into the appropriate two-insn ;; Split a load of a large constant into the appropriate two-insn
;; sequence. ;; sequence.
...@@ -2287,7 +2775,7 @@ ...@@ -2287,7 +2775,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"" ""
"ai. %0,%1,0" "{ai.|addic.} %0,%1,0"
[(set_attr "type" "compare")]) [(set_attr "type" "compare")])
(define_expand "movhi" (define_expand "movhi"
...@@ -2312,18 +2800,32 @@ ...@@ -2312,18 +2800,32 @@
(define_insn "" (define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))] (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
"gpc_reg_operand (operands[0], HImode) "TARGET_POWER && (gpc_reg_operand (operands[0], HImode)
|| gpc_reg_operand (operands[1], HImode)" || gpc_reg_operand (operands[1], HImode))"
"@ "@
oril %0,%1,0 {oril|ori} %0,%1,0
lhz%U1%X1 %0,%1 lhz%U1%X1 %0,%1
sth%U0%X0 %1,%0 sth%U0%X0 %1,%0
cal %0,%w1(0) {cal %0,%w1(0)|li %0,%w1}
mf%1 %0 mf%1 %0
mt%0 %1 mt%0 %1
cror 0,0,0" cror 0,0,0"
[(set_attr "type" "*,load,*,*,*,*,*")]) [(set_attr "type" "*,load,*,*,*,*,*")])
(define_insn ""
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
"TARGET_POWERPC && (gpc_reg_operand (operands[0], HImode)
|| gpc_reg_operand (operands[1], HImode))"
"@
ori %0,%1,0
lhz%U1%X1 %0,%1
sth%U0%X0 %1,%0
li %0,%w1
mf%1 %0
mt%0 %1"
[(set_attr "type" "*,load,*,*,*,*")])
(define_expand "movqi" (define_expand "movqi"
[(set (match_operand:QI 0 "general_operand" "") [(set (match_operand:QI 0 "general_operand" "")
(match_operand:QI 1 "any_operand" ""))] (match_operand:QI 1 "any_operand" ""))]
...@@ -2346,17 +2848,31 @@ ...@@ -2346,17 +2848,31 @@
(define_insn "" (define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h") [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))] (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
"gpc_reg_operand (operands[0], QImode) "TARGET_POWER && (gpc_reg_operand (operands[0], QImode)
|| gpc_reg_operand (operands[1], QImode)" || gpc_reg_operand (operands[1], QImode))"
"@ "@
oril %0,%1,0 {oril|ori} %0,%1,0
lbz%U1%X1 %0,%1 lbz%U1%X1 %0,%1
stb%U0%X0 %1,%0 stb%U0%X0 %1,%0
cal %0,%1(0) {cal %0,%1(0)|li %0,%1}
mf%1 %0 mf%1 %0
mt%0 %1 mt%0 %1
cror 0,0,0" cror 0,0,0"
[(set_attr "type" "*,load,*,*,*,*,*")]) [(set_attr "type" "*,load,*,*,*,*,*")])
(define_insn ""
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
"TARGET_POWERPC && (gpc_reg_operand (operands[0], QImode)
|| gpc_reg_operand (operands[1], QImode))"
"@
mr %0,%1
lbz%U1%X1 %0,%1
stb%U0%X0 %1,%0
li %0,%1
mf%1 %0
mt%0 %1"
[(set_attr "type" "*,load,*,*,*,*")])
;; Here is how to move condition codes around. When we store CC data in ;; Here is how to move condition codes around. When we store CC data in
;; an integer register or memory, we store just the high-order 4 bits. ;; an integer register or memory, we store just the high-order 4 bits.
...@@ -2375,12 +2891,12 @@ ...@@ -2375,12 +2891,12 @@
"@ "@
mcrf %0,%1 mcrf %0,%1
mtcrf 128,%1 mtcrf 128,%1
rlinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0xffffffff {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
mfcr %0 mfcr %0
mfcr %0\;rlinm %0,%0,%f1,0xf0000000 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
ai %0,%1,0 {ai %0,%1,0|mr %0,%1}
l%U1%X1 %0,%1 {l%U1%X1|lwz%U1%X1} %0,%1
st%U0%U1 %1,%0" {st%U0%U1|stw%U0%U1} %1,%0"
[(set_attr "type" "*,*,*,compare,*,*,load,*") [(set_attr "type" "*,*,*,compare,*,*,load,*")
(set_attr "length" "*,*,12,*,8,*,*,*")]) (set_attr "length" "*,*,12,*,8,*,*,*")])
...@@ -2471,15 +2987,6 @@ ...@@ -2471,15 +2987,6 @@
} }
}") }")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=r,r")
(match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
"REGNO (operands[0]) <= 31"
"@
#
l%U1%X1 %0,%1"
[(set_attr "type" "*,load")])
(define_split (define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(match_operand:SF 1 "easy_fp_constant" ""))] (match_operand:SF 1 "easy_fp_constant" ""))]
...@@ -2527,7 +3034,6 @@ ...@@ -2527,7 +3034,6 @@
operands[1] = change_address (operands[1], DFmode, operands[1] = change_address (operands[1], DFmode,
XEXP (operands[1], 0)); XEXP (operands[1], 0));
} }
}") }")
(define_split (define_split
...@@ -2556,9 +3062,9 @@ ...@@ -2556,9 +3062,9 @@
the first register operand 0 is the same as the second register of the first register operand 0 is the same as the second register of
operand 1, we must copy in the opposite order. */ operand 1, we must copy in the opposite order. */
if (REGNO (operands[0]) == REGNO (operands[1]) + 1) if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
return \"oril %L0,%L1,0\;oril %0,%1,0\"; return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
else else
return \"oril %0,%1,0\;oril %L0,%L1,0\"; return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\";
case 1: case 1:
/* If the low-address word is used in the address, we must load it /* If the low-address word is used in the address, we must load it
last. Otherwise, load it first. Note that we cannot have last. Otherwise, load it first. Note that we cannot have
...@@ -2566,11 +3072,11 @@ ...@@ -2566,11 +3072,11 @@
dead. */ dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands [1], 0)) operands [1], 0))
return \"l %L0,%L1\;l %0,%1\"; return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else else
return \"l%U1 %0,%1\;l %L0,%L1\"; return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
case 2: case 2:
return \"st%U0 %1,%0\;st %L1,%L0\"; return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
case 3: case 3:
return \"#\"; return \"#\";
case 4: case 4:
...@@ -2581,7 +3087,7 @@ ...@@ -2581,7 +3087,7 @@
return \"stfd%U0%X0 %1,%0\"; return \"stfd%U0%X0 %1,%0\";
} }
}" }"
[(set_attr "type" "*,load,*,*,fp,load,*") [(set_attr "type" "*,load,*,*,fp,fpload,*")
(set_attr "length" "8,8,8,8,*,*,*")]) (set_attr "length" "8,8,8,8,*,*,*")])
;; Next come the multi-word integer load and store and the load and store ;; Next come the multi-word integer load and store and the load and store
...@@ -2620,9 +3126,9 @@ ...@@ -2620,9 +3126,9 @@
the first register operand 0 is the same as the second register of the first register operand 0 is the same as the second register of
operand 1, we must copy in the opposite order. */ operand 1, we must copy in the opposite order. */
if (REGNO (operands[0]) == REGNO (operands[1]) + 1) if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
return \"oril %L0,%L1,0\;oril %0,%1,0\"; return \"{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
else else
return \"oril %0,%1,0\;oril %L0,%L1,0\"; return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\";
case 1: case 1:
/* If the low-address word is used in the address, we must load it /* If the low-address word is used in the address, we must load it
last. Otherwise, load it first. Note that we cannot have last. Otherwise, load it first. Note that we cannot have
...@@ -2630,11 +3136,11 @@ ...@@ -2630,11 +3136,11 @@
dead. */ dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands [1], 0)) operands [1], 0))
return \"l %L0,%L1\;l %0,%1\"; return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
else else
return \"l%U1 %0,%1\;l %L0,%L1\"; return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
case 2: case 2:
return \"st%U0 %1,%0\;st %L1,%L0\"; return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
} }
}" }"
[(set_attr "type" "*,load,*") [(set_attr "type" "*,load,*")
...@@ -2642,12 +3148,12 @@ ...@@ -2642,12 +3148,12 @@
;; TImode is similar, except that we usually want to compute the address into ;; TImode is similar, except that we usually want to compute the address into
;; a register and use lsi/stsi (the exception is during reload). MQ is also ;; a register and use lsi/stsi (the exception is during reload). MQ is also
;; clobbered in stsi, so we need a SCRATCH for it. ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
(define_expand "movti" (define_expand "movti"
[(parallel [(set (match_operand:TI 0 "general_operand" "") [(parallel [(set (match_operand:TI 0 "general_operand" "")
(match_operand:TI 1 "general_operand" "")) (match_operand:TI 1 "general_operand" ""))
(clobber (scratch:SI))])] (clobber (scratch:SI))])]
"" "TARGET_POWER"
" "
{ {
if (GET_CODE (operands[0]) == MEM) if (GET_CODE (operands[0]) == MEM)
...@@ -2675,17 +3181,17 @@ ...@@ -2675,17 +3181,17 @@
[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r") [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
(clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
"gpc_reg_operand (operands[0], TImode) "TARGET_POWER && (gpc_reg_operand (operands[0], TImode)
|| gpc_reg_operand (operands[1], TImode)" || gpc_reg_operand (operands[1], TImode))"
"* "*
{ {
switch (which_alternative) switch (which_alternative)
{ {
case 0: case 0:
return \"stsi %1,%P0,16\"; return \"{stsi|stswi} %1,%P0,16\";
case 1: case 1:
return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\"; return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
case 2: case 2:
/* Normally copy registers with lowest numbered register copied first. /* Normally copy registers with lowest numbered register copied first.
...@@ -2693,14 +3199,14 @@ ...@@ -2693,14 +3199,14 @@
is the second, third, or fourth register in the input. */ is the second, third, or fourth register in the input. */
if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
&& REGNO (operands[0]) <= REGNO (operands[1]) + 3) && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\"; return \"{oril %Z0,%Z1,0|mr %Z0,%Z1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %0,%1,0|mr %0,%1}\";
else else
return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\"; return \"{oril %0,%1,0|mr %0,%1}\;{oril %L0,%L1,0|mr %L0,%L1}\;{oril %Y0,%Y1,0|mr %Y0,%Y1}\;{oril %Z0,%Z1,0|mr %Z0,%Z1}\";
case 3: case 3:
/* If the address is not used in the output, we can use lsi. Otherwise, /* If the address is not used in the output, we can use lsi. Otherwise,
fall through to generating four loads. */ fall through to generating four loads. */
if (! reg_overlap_mentioned_p (operands[0], operands[1])) if (! reg_overlap_mentioned_p (operands[0], operands[1]))
return \"lsi %0,%P1,16\"; return \"{lsi|lswi} %0,%P1,16\";
/* ... fall through ... */ /* ... fall through ... */
case 4: case 4:
/* If the address register is the same as the register for the lowest- /* If the address register is the same as the register for the lowest-
...@@ -2708,15 +3214,15 @@ ...@@ -2708,15 +3214,15 @@
Otherwise load lowest address to highest. */ Otherwise load lowest address to highest. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands[1], 0)) operands[1], 0))
return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\"; return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
else if (refers_to_regno_p (REGNO (operands[0]) + 1, else if (refers_to_regno_p (REGNO (operands[0]) + 1,
REGNO (operands[0]) + 2, operands[1], 0)) REGNO (operands[0]) + 2, operands[1], 0))
return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\"; return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
else if (refers_to_regno_p (REGNO (operands[0]) + 2, else if (refers_to_regno_p (REGNO (operands[0]) + 2,
REGNO (operands[0]) + 3, operands[1], 0)) REGNO (operands[0]) + 3, operands[1], 0))
return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\"; return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
else else
return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\"; return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
} }
}" }"
[(set_attr "type" "*,load,load,*,*") [(set_attr "type" "*,load,load,*,*")
...@@ -2726,7 +3232,7 @@ ...@@ -2726,7 +3232,7 @@
[(match_par_dup 3 [(set (match_operand:SI 0 "" "") [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
(match_operand:SI 1 "" "")) (match_operand:SI 1 "" ""))
(use (match_operand:SI 2 "" ""))])] (use (match_operand:SI 2 "" ""))])]
"" "TARGET_POWER"
" "
{ {
int regno; int regno;
...@@ -2761,7 +3267,7 @@ ...@@ -2761,7 +3267,7 @@
[(match_parallel 0 "load_multiple_operation" [(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r") [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
(match_operand:SI 2 "indirect_operand" "Q"))])] (match_operand:SI 2 "indirect_operand" "Q"))])]
"" "TARGET_POWER"
"* "*
{ {
/* We have to handle the case where the pseudo used to contain the address /* We have to handle the case where the pseudo used to contain the address
...@@ -2773,12 +3279,12 @@ ...@@ -2773,12 +3279,12 @@
char newload[40]; char newload[40];
int i; int i;
strcpy (result, \"lsi %1,%P2,%N0\"); strcpy (result, \"{lsi|lswi} %1,%P2,%N0\");
for (i = 0; i < XVECLEN (operands[0], 0); i++) for (i = 0; i < XVECLEN (operands[0], 0); i++)
if (refers_to_regno_p (REGNO (operands[1]) + i, if (refers_to_regno_p (REGNO (operands[1]) + i,
REGNO (operands[1]) + i + 1, operands[2], 0)) REGNO (operands[1]) + i + 1, operands[2], 0))
{ {
sprintf (newload, \"\;l %d,%d(%d)\", sprintf (newload, \"\;{l|lwz} %d,%d(%d)\",
REGNO (operands[1]) + i, REGNO (operands[1]) + i,
i * 4, REGNO (XEXP (operands[2], 0))); i * 4, REGNO (XEXP (operands[2], 0)));
strcat (result, newload); strcat (result, newload);
...@@ -2795,7 +3301,7 @@ ...@@ -2795,7 +3301,7 @@
(match_operand:SI 1 "" "")) (match_operand:SI 1 "" ""))
(clobber (scratch:SI)) (clobber (scratch:SI))
(use (match_operand:SI 2 "" ""))])] (use (match_operand:SI 2 "" ""))])]
"" "TARGET_POWER"
" "
{ {
int regno; int regno;
...@@ -2837,8 +3343,8 @@ ...@@ -2837,8 +3343,8 @@
[(set (match_operand:SI 1 "indirect_operand" "=Q") [(set (match_operand:SI 1 "indirect_operand" "=Q")
(match_operand:SI 2 "gpc_reg_operand" "r")) (match_operand:SI 2 "gpc_reg_operand" "r"))
(clobber (match_scratch:SI 3 "=q"))])] (clobber (match_scratch:SI 3 "=q"))])]
"" "TARGET_POWER"
"stsi %2,%P1,%O0") "{stsi|stswi} %2,%P1,%O0")
;; Define insns that do load or store with update. Some of these we can ;; Define insns that do load or store with update. Some of these we can
;; get by using pre-decrement or pre-increment, but the hardware can also ;; get by using pre-decrement or pre-increment, but the hardware can also
...@@ -2857,8 +3363,8 @@ ...@@ -2857,8 +3363,8 @@
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"" ""
"@ "@
lux %3,%0,%2 {lux|lwzux} %3,%0,%2
lu %3,%2(%0)" {lu|lwzu} %3,%2(%0)"
[(set_attr "type" "load")]) [(set_attr "type" "load")])
(define_insn "" (define_insn ""
...@@ -2869,8 +3375,8 @@ ...@@ -2869,8 +3375,8 @@
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"" ""
"@ "@
stux %3,%0,%2 {stux|stwux} %3,%0,%2
stu %3,%2(%0)") {stu|stwu} %3,%2(%0)")
(define_insn "" (define_insn ""
[(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
...@@ -3164,8 +3670,8 @@ ...@@ -3164,8 +3670,8 @@
(clobber (match_scratch:SI 2 "=l,l"))] (clobber (match_scratch:SI 2 "=l,l"))]
"" ""
"@ "@
brl\;l 2,20(1) {brl|blrl}\;{l|lwz} 2,20(1)
bl %z0\;cror %.,%.,%." bl %z0\;{cror %.,%.,%.|nop}"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -3183,8 +3689,8 @@ ...@@ -3183,8 +3689,8 @@
(clobber (match_scratch:SI 3 "=l,l"))] (clobber (match_scratch:SI 3 "=l,l"))]
"" ""
"@ "@
brl\;l 2,20(1) {brl|blrl}\;{l|lwz} 2,20(1)
bl %z1\;cror %.,%.,%." bl %z1\;{cror %.,%.,%.|nop}"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
;; Call subroutine returning any type. ;; Call subroutine returning any type.
...@@ -3674,7 +4180,7 @@ ...@@ -3674,7 +4180,7 @@
[(match_operand 2 "cc_reg_operand" "y") [(match_operand 2 "cc_reg_operand" "y")
(const_int 0)]))] (const_int 0)]))]
"" ""
"%D1mfcr %0\;rlinm %0,%0,%J1,1" "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -3686,7 +4192,7 @@ ...@@ -3686,7 +4192,7 @@
(set (match_operand:SI 3 "gpc_reg_operand" "=r") (set (match_operand:SI 3 "gpc_reg_operand" "=r")
(match_op_dup 1 [(match_dup 2) (const_int 0)]))] (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
"" ""
"%D1mfcr %3\;rlinm. %3,%3,%J1,1" "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
[(set_attr "type" "delayed_compare") [(set_attr "type" "delayed_compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -3711,7 +4217,7 @@ ...@@ -3711,7 +4217,7 @@
operands[4] = gen_rtx (CONST_INT, VOIDmode, count); operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\"; return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
}" }"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
...@@ -3741,7 +4247,7 @@ ...@@ -3741,7 +4247,7 @@
operands[5] = gen_rtx (CONST_INT, VOIDmode, count); operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\"; return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
}" }"
[(set_attr "type" "delayed_compare") [(set_attr "type" "delayed_compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -3791,7 +4297,7 @@ ...@@ -3791,7 +4297,7 @@
[(match_operand 5 "cc_reg_operand" "y") [(match_operand 5 "cc_reg_operand" "y")
(const_int 0)]))] (const_int 0)]))]
"REGNO (operands[2]) != REGNO (operands[5])" "REGNO (operands[2]) != REGNO (operands[5])"
"%D1%D4mfcr %3\;rlinm %0,%3,%J1,1\;rlinm %3,%3,%J4,1" "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
[(set_attr "length" "20")]) [(set_attr "length" "20")])
;; There are some scc insns that can be done directly, without a compare. ;; There are some scc insns that can be done directly, without a compare.
...@@ -3815,11 +4321,11 @@ ...@@ -3815,11 +4321,11 @@
(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
"" ""
"@ "@
xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
sfi %3,%1,0\;ae %0,%3,%1 {sfi|xubfic} %3,%1,0\;{ae|adde} %0,%3,%1
xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0" {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
[(set_attr "length" "12,8,12,12,12")]) [(set_attr "length" "12,8,12,12,12")])
(define_insn "" (define_insn ""
...@@ -3833,11 +4339,11 @@ ...@@ -3833,11 +4339,11 @@
(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
"" ""
"@ "@
xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
sfi %3,%1,0\;ae. %0,%3,%1 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0" {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12,8,12,12,12")]) (set_attr "length" "12,8,12,12,12")])
...@@ -3864,11 +4370,11 @@ ...@@ -3864,11 +4370,11 @@
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
"" ""
"@ "@
xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
sfi %4,%1,0\;aze %0,%3 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3" {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|adddze} %0,%3"
[(set_attr "length" "12,8,12,12,12")]) [(set_attr "length" "12,8,12,12,12")])
(define_insn "" (define_insn ""
...@@ -3882,11 +4388,11 @@ ...@@ -3882,11 +4388,11 @@
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
"" ""
"@ "@
xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
sfi %4,%1,0\;aze. %0,%3 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3" {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12,8,12,12,12")]) (set_attr "length" "12,8,12,12,12")])
...@@ -3903,11 +4409,11 @@ ...@@ -3903,11 +4409,11 @@
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
"" ""
"@ "@
xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
sfi %4,%1,0\;aze. %4,%3 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3" {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12,8,12,12,12")]) (set_attr "length" "12,8,12,12,12")])
...@@ -3917,11 +4423,11 @@ ...@@ -3917,11 +4423,11 @@
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
"" ""
"@ "@
xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
ai %0,%1,-1\;sfe %0,%0,%0 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0" {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12,8,12,12,12")]) [(set_attr "length" "12,8,12,12,12")])
;; This is what (plus (ne X (const_int 0)) Y) looks like. ;; This is what (plus (ne X (const_int 0)) Y) looks like.
...@@ -3933,7 +4439,7 @@ ...@@ -3933,7 +4439,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r"))) (match_operand:SI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"ai %3,%1,-1\;aze %0,%2" "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -3946,7 +4452,7 @@ ...@@ -3946,7 +4452,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"ai %3,%1,-1\;aze. %3,%2" "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -3963,7 +4469,7 @@ ...@@ -3963,7 +4469,7 @@
(match_dup 2))) (match_dup 2)))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"ai %3,%1,-1\;aze. %0,%2" "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -3972,10 +4478,10 @@ ...@@ -3972,10 +4478,10 @@
(le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O"))) (match_operand:SI 2 "reg_or_short_operand" "r,O")))
(clobber (match_scratch:SI 3 "=r,X"))] (clobber (match_scratch:SI 3 "=r,X"))]
"" "TARGET_POWER"
"@ "@
doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31" {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;sri %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -3987,10 +4493,10 @@ ...@@ -3987,10 +4493,10 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(le:SI (match_dup 1) (match_dup 2))) (le:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 "=r,X"))] (clobber (match_scratch:SI 3 "=r,X"))]
"" "TARGET_POWER"
"@ "@
doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31" {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;sri. %0,%0,31"
[(set_attr "type" "delayed_compare,compare") [(set_attr "type" "delayed_compare,compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4000,10 +4506,10 @@ ...@@ -4000,10 +4506,10 @@
(match_operand:SI 2 "reg_or_short_operand" "r,O")) (match_operand:SI 2 "reg_or_short_operand" "r,O"))
(match_operand:SI 3 "gpc_reg_operand" "r,r"))) (match_operand:SI 3 "gpc_reg_operand" "r,r")))
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" "TARGET_POWER"
"@ "@
doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3" {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4014,10 +4520,10 @@ ...@@ -4014,10 +4520,10 @@
(match_operand:SI 3 "gpc_reg_operand" "r,r")) (match_operand:SI 3 "gpc_reg_operand" "r,r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" "TARGET_POWER"
"@ "@
doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3" {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4031,10 +4537,10 @@ ...@@ -4031,10 +4537,10 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" "TARGET_POWER"
"@ "@
doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3" {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4042,10 +4548,10 @@ ...@@ -4042,10 +4548,10 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_short_operand" "r,O"))))] (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
"" "TARGET_POWER"
"@ "@
doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31" {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4053,7 +4559,7 @@ ...@@ -4053,7 +4559,7 @@
(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))] (match_operand:SI 2 "reg_or_short_operand" "rI")))]
"" ""
"sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0" "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4065,7 +4571,7 @@ ...@@ -4065,7 +4571,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(leu:SI (match_dup 1) (match_dup 2)))] (leu:SI (match_dup 1) (match_dup 2)))]
"" ""
"sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0" "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4076,7 +4582,7 @@ ...@@ -4076,7 +4582,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r"))) (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" ""
"sf%I2 %4,%1,%2\;aze %0,%3" "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -4088,7 +4594,7 @@ ...@@ -4088,7 +4594,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" ""
"sf%I2 %4,%1,%2\;aze. %4,%3" "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -4103,7 +4609,7 @@ ...@@ -4103,7 +4609,7 @@
(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" ""
"sf%I2 %4,%1,%2\;aze. %0,%3" "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -4112,7 +4618,7 @@ ...@@ -4112,7 +4618,7 @@
(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))] (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"" ""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4123,7 +4629,7 @@ ...@@ -4123,7 +4629,7 @@
(match_operand:SI 3 "gpc_reg_operand" "r"))) (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" ""
"sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4" "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4136,7 +4642,7 @@ ...@@ -4136,7 +4642,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" ""
"sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4" "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4152,7 +4658,7 @@ ...@@ -4152,7 +4658,7 @@
(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" ""
"sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4" "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4160,7 +4666,7 @@ ...@@ -4160,7 +4666,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))] (match_operand:SI 2 "reg_or_short_operand" "rI")))]
"" "TARGET_POWER"
"doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31" "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
...@@ -4172,7 +4678,7 @@ ...@@ -4172,7 +4678,7 @@
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(lt:SI (match_dup 1) (match_dup 2)))] (lt:SI (match_dup 1) (match_dup 2)))]
"" "TARGET_POWER"
"doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31" "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
[(set_attr "type" "delayed_compare") [(set_attr "type" "delayed_compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4183,8 +4689,8 @@ ...@@ -4183,8 +4689,8 @@
(match_operand:SI 2 "reg_or_short_operand" "rI")) (match_operand:SI 2 "reg_or_short_operand" "rI"))
(match_operand:SI 3 "gpc_reg_operand" "r"))) (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3" "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4195,8 +4701,8 @@ ...@@ -4195,8 +4701,8 @@
(match_operand:SI 3 "gpc_reg_operand" "r")) (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3" "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4210,8 +4716,8 @@ ...@@ -4210,8 +4716,8 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3" "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4219,8 +4725,8 @@ ...@@ -4219,8 +4725,8 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))] (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"" "TARGET_POWER"
"doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31" "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4229,8 +4735,8 @@ ...@@ -4229,8 +4735,8 @@
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"" ""
"@ "@
sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0" {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4243,8 +4749,8 @@ ...@@ -4243,8 +4749,8 @@
(ltu:SI (match_dup 1) (match_dup 2)))] (ltu:SI (match_dup 1) (match_dup 2)))]
"" ""
"@ "@
sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0" {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4256,10 +4762,10 @@ ...@@ -4256,10 +4762,10 @@
(clobber (match_scratch:SI 4 "=&r,r,&r,r"))] (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
"" ""
"@ "@
sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3" {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4272,8 +4778,8 @@ ...@@ -4272,8 +4778,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;sfe %4,%4,%4\;sf. %4,%4,%3 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
ai %4,%1,%n2\;sfe %4,%4,%4\;sf. %4,%4,%3" {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4289,8 +4795,8 @@ ...@@ -4289,8 +4795,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;sfe %4,%4,%4\;sf. %0,%4,%3 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
ai %4,%1,%n2\;sfe %4,%4,%4\;sf. %0,%4,%3" {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4300,8 +4806,8 @@ ...@@ -4300,8 +4806,8 @@
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
"" ""
"@ "@
sf %0,%2,%1\;sfe %0,%0,%0 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
ai %0,%1,%n2\;sfe %0,%0,%0" {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -4309,8 +4815,8 @@ ...@@ -4309,8 +4815,8 @@
(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))) (match_operand:SI 2 "reg_or_short_operand" "rI")))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" "TARGET_POWER"
"doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3" "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4322,8 +4828,8 @@ ...@@ -4322,8 +4828,8 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ge:SI (match_dup 1) (match_dup 2))) (ge:SI (match_dup 1) (match_dup 2)))
(clobber (match_scratch:SI 3 "=r"))] (clobber (match_scratch:SI 3 "=r"))]
"" "TARGET_POWER"
"doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3" "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4333,8 +4839,8 @@ ...@@ -4333,8 +4839,8 @@
(match_operand:SI 2 "reg_or_short_operand" "rI")) (match_operand:SI 2 "reg_or_short_operand" "rI"))
(match_operand:SI 3 "gpc_reg_operand" "r"))) (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3" "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4345,8 +4851,8 @@ ...@@ -4345,8 +4851,8 @@
(match_operand:SI 3 "gpc_reg_operand" "r")) (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3" "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4360,8 +4866,8 @@ ...@@ -4360,8 +4866,8 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3" "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4369,8 +4875,8 @@ ...@@ -4369,8 +4875,8 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))] (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"" "TARGET_POWER"
"doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0" "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
;; This is (and (neg (ge X (const_int 0))) Y). ;; This is (and (neg (ge X (const_int 0))) Y).
...@@ -4383,7 +4889,7 @@ ...@@ -4383,7 +4889,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r"))) (match_operand:SI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"srai %3,%1,31\;andc %0,%2,%3" "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -4397,7 +4903,7 @@ ...@@ -4397,7 +4903,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"srai %3,%1,31\;andc. %3,%2,%3" "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -4416,7 +4922,7 @@ ...@@ -4416,7 +4922,7 @@
(match_dup 2))) (match_dup 2)))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"srai %3,%1,31\;andc. %0,%2,%3" "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -4426,8 +4932,8 @@ ...@@ -4426,8 +4932,8 @@
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"" ""
"@ "@
sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0" {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4440,8 +4946,8 @@ ...@@ -4440,8 +4946,8 @@
(geu:SI (match_dup 1) (match_dup 2)))] (geu:SI (match_dup 1) (match_dup 2)))]
"" ""
"@ "@
sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0" {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4453,8 +4959,8 @@ ...@@ -4453,8 +4959,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;aze %0,%3 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
ai %4,%1,%n2\;aze %0,%3" {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -4467,8 +4973,8 @@ ...@@ -4467,8 +4973,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;aze. %4,%3 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
ai %4,%1,%n2\;aze. %4,%3" {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -4484,8 +4990,8 @@ ...@@ -4484,8 +4990,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;aze. %0,%3 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
ai %4,%1,%n2\;aze. %4,%3" {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8")]) (set_attr "length" "8")])
...@@ -4495,8 +5001,8 @@ ...@@ -4495,8 +5001,8 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))] (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
"" ""
"@ "@
sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0" {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4508,8 +5014,8 @@ ...@@ -4508,8 +5014,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4" {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4523,8 +5029,8 @@ ...@@ -4523,8 +5029,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4" {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4541,8 +5047,8 @@ ...@@ -4541,8 +5047,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4" {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4551,7 +5057,7 @@ ...@@ -4551,7 +5057,7 @@
(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0)))] (const_int 0)))]
"" ""
"sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31" "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4563,7 +5069,7 @@ ...@@ -4563,7 +5069,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_dup 1) (const_int 0)))] (gt:SI (match_dup 1) (const_int 0)))]
"" ""
"sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31" "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
[(set_attr "type" "delayed_compare") [(set_attr "type" "delayed_compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4571,8 +5077,8 @@ ...@@ -4571,8 +5077,8 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r")))] (match_operand:SI 2 "reg_or_short_operand" "r")))]
"" "TARGET_POWER"
"doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31" "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4583,8 +5089,8 @@ ...@@ -4583,8 +5089,8 @@
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gt:SI (match_dup 1) (match_dup 2)))] (gt:SI (match_dup 1) (match_dup 2)))]
"" "TARGET_POWER"
"doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31" "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
[(set_attr "type" "delayed_compare") [(set_attr "type" "delayed_compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4595,7 +5101,7 @@ ...@@ -4595,7 +5101,7 @@
(match_operand:SI 2 "gpc_reg_operand" "r"))) (match_operand:SI 2 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2" "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4607,7 +5113,7 @@ ...@@ -4607,7 +5113,7 @@
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2" "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4622,7 +5128,7 @@ ...@@ -4622,7 +5128,7 @@
(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
(clobber (match_scratch:SI 3 "=&r"))] (clobber (match_scratch:SI 3 "=&r"))]
"" ""
"a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2" "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4632,8 +5138,8 @@ ...@@ -4632,8 +5138,8 @@
(match_operand:SI 2 "reg_or_short_operand" "r")) (match_operand:SI 2 "reg_or_short_operand" "r"))
(match_operand:SI 3 "gpc_reg_operand" "r"))) (match_operand:SI 3 "gpc_reg_operand" "r")))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3" "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4644,8 +5150,8 @@ ...@@ -4644,8 +5150,8 @@
(match_operand:SI 3 "gpc_reg_operand" "r")) (match_operand:SI 3 "gpc_reg_operand" "r"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3" "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4659,8 +5165,8 @@ ...@@ -4659,8 +5165,8 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(clobber (match_scratch:SI 4 "=&r"))] (clobber (match_scratch:SI 4 "=&r"))]
"" "TARGET_POWER"
"doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3" "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4669,15 +5175,15 @@ ...@@ -4669,15 +5175,15 @@
(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(const_int 0))))] (const_int 0))))]
"" ""
"sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31" "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "r"))))] (match_operand:SI 2 "reg_or_short_operand" "r"))))]
"" "TARGET_POWER"
"doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31" "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4685,7 +5191,7 @@ ...@@ -4685,7 +5191,7 @@
(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))] (match_operand:SI 2 "reg_or_short_operand" "rI")))]
"" ""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
[(set_attr "length" "12")]) [(set_attr "length" "12")])
(define_insn "" (define_insn ""
...@@ -4697,7 +5203,7 @@ ...@@ -4697,7 +5203,7 @@
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gtu:SI (match_dup 1) (match_dup 2)))] (gtu:SI (match_dup 1) (match_dup 2)))]
"" ""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "12")]) (set_attr "length" "12")])
...@@ -4709,9 +5215,9 @@ ...@@ -4709,9 +5215,9 @@
(clobber (match_scratch:SI 4 "=&r,&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
"" ""
"@ "@
ai %4,%1,%k2\;aze %0,%3 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3" {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
[(set_attr "length" "8,12,12")]) [(set_attr "length" "8,12,12")])
(define_insn "" (define_insn ""
...@@ -4724,8 +5230,8 @@ ...@@ -4724,8 +5230,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
ai %4,%1,%k2\;aze. %0,%3 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf. %0,%4,%3" {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8,12")]) (set_attr "length" "8,12")])
...@@ -4741,8 +5247,8 @@ ...@@ -4741,8 +5247,8 @@
(clobber (match_scratch:SI 4 "=&r,&r"))] (clobber (match_scratch:SI 4 "=&r,&r"))]
"" ""
"@ "@
ai %4,%1,%k2\;aze. %0,%3 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf. %0,%4,%3" {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
[(set_attr "type" "compare") [(set_attr "type" "compare")
(set_attr "length" "8,12")]) (set_attr "length" "8,12")])
...@@ -4751,7 +5257,7 @@ ...@@ -4751,7 +5257,7 @@
(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))] (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"" ""
"sf%I2 %0,%1,%2\;sfe %0,%0,%0" "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
;; Define both directions of branch and return. If we need a reload ;; Define both directions of branch and return. If we need a reload
...@@ -4786,7 +5292,7 @@ ...@@ -4786,7 +5292,7 @@
(return) (return)
(pc)))] (pc)))]
"direct_return ()" "direct_return ()"
"%C0bcr %t0,%j0" "{%C0bcr|%C0bclr} %t0,%j0"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
(define_insn "" (define_insn ""
...@@ -4816,7 +5322,7 @@ ...@@ -4816,7 +5322,7 @@
(pc) (pc)
(return)))] (return)))]
"direct_return ()" "direct_return ()"
"%C0bcr %T0,%j0" "{%C0bcr|%C0bclr} %T0,%j0"
[(set_attr "length" "8")]) [(set_attr "length" "8")])
;; Unconditional branch and return. ;; Unconditional branch and return.
...@@ -4830,14 +5336,14 @@ ...@@ -4830,14 +5336,14 @@
(define_insn "return" (define_insn "return"
[(return)] [(return)]
"direct_return ()" "direct_return ()"
"br") "{br|blr}")
(define_insn "indirect_jump" (define_insn "indirect_jump"
[(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
"" ""
"@ "@
bctr bctr
br") {br|blr}")
;; Table jump for switch statements: ;; Table jump for switch statements:
(define_expand "tablejump" (define_expand "tablejump"
...@@ -4860,12 +5366,12 @@ ...@@ -4860,12 +5366,12 @@
"" ""
"@ "@
bctr bctr
br") {br|blr}")
(define_insn "nop" (define_insn "nop"
[(const_int 0)] [(const_int 0)]
"" ""
"cror 0,0,0") "{cror 0,0,0|nop}")
;; Define the subtract-one-and-jump insns, starting with the template ;; Define the subtract-one-and-jump insns, starting with the template
;; so loop.c knows what to generate. ;; so loop.c knows what to generate.
...@@ -4898,7 +5404,7 @@ ...@@ -4898,7 +5404,7 @@
if (which_alternative == 1) if (which_alternative == 1)
return \"#\"; return \"#\";
else if (get_attr_length (insn) == 8) else if (get_attr_length (insn) == 8)
return \"bdn %l2\"; return \"{bdn|bdnz} %l2\";
else else
return \"bdz $+8\;b %l2\"; return \"bdz $+8\;b %l2\";
}" }"
...@@ -4921,7 +5427,7 @@ ...@@ -4921,7 +5427,7 @@
if (which_alternative == 1) if (which_alternative == 1)
return \"#\"; return \"#\";
else if (get_attr_length (insn) == 8) else if (get_attr_length (insn) == 8)
return \"bdn %l2\"; return \"{bdn|bdnz} %l2\";
else else
return \"bdz $+8\;b %l2\"; return \"bdz $+8\;b %l2\";
}" }"
...@@ -4945,7 +5451,7 @@ ...@@ -4945,7 +5451,7 @@
else if (get_attr_length (insn) == 8) else if (get_attr_length (insn) == 8)
return \"bdz %l2\"; return \"bdz %l2\";
else else
return \"bdn $+8\;b %l2\"; return \"{bdn|bdnz} $+8\;b %l2\";
}" }"
[(set_attr "type" "branch")]) [(set_attr "type" "branch")])
......
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