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riscv-gcc-1
Commit c77e04ae by Richard Henderson Committed by Richard Henderson
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genoutput.c (validate_insn_operands): New. 

        * genoutput.c (validate_insn_operands): New.
        (gen_insn): Call it.

        * config/alpha/alpha.md (divmodsi_internal): Renumber operands.
        (divmoddi_internal): Likewise.
        * config/arm/arm.md (andsi3_compare0_scratch): Likewise.
        * config/i960/i960.md (branch patterns): Likewise.
        * config/ia64/ia64.md (tbit_and_0): Likewise.
        (tbit_and_1, tbit_or_0, tbit_or_1): Likewise.
        * config/m68k/m68k.md (zero_extract memory patterns): Likewise.
        * config/mips/mips.md (divmodsi4_internal): Likewise.
        (divmoddi4_internal): Likewise.
        * config/rs6000/rs6000.md (call patterns): Likewise.
        * config/sh/sh.md (movsi_y): Likewise.
        * config/sparc/sparc.md: Comment out if 0 v8p shift pattern.

From-SVN: r37828
parent 79bc4669
Showing with 94 additions and 58 deletions
gcc/ChangeLog
2000-11-28 Richard Henderson <rth@redhat.com>
* genoutput.c (validate_insn_operands): New.
(gen_insn): Call it.
* config/alpha/alpha.md (divmodsi_internal): Renumber operands.
(divmoddi_internal): Likewise.
* config/arm/arm.md (andsi3_compare0_scratch): Likewise.
* config/i960/i960.md (branch patterns): Likewise.
* config/ia64/ia64.md (tbit_and_0): Likewise.
(tbit_and_1, tbit_or_0, tbit_or_1): Likewise.
* config/m68k/m68k.md (zero_extract memory patterns): Likewise.
* config/mips/mips.md (divmodsi4_internal): Likewise.
(divmoddi4_internal): Likewise.
* config/rs6000/rs6000.md (call patterns): Likewise.
* config/sh/sh.md (movsi_y): Likewise.
* config/sparc/sparc.md: Comment out if 0 v8p shift pattern.
2000-11-28 Richard Henderson <rth@redhat.com>
* config.gcc: Kill residual pyramid support.
2000-11-28 Neil Booth <neilb@earthling.net>
......
gcc/config/alpha/alpha.md
......@@ -986,23 +986,23 @@
;; expanded by the assembler.
(define_insn "*divmodsi_internal"
[(set (reg:DI 27)
(sign_extend:DI (match_operator:SI 1 "divmod_operator"
(sign_extend:DI (match_operator:SI 0 "divmod_operator"
[(reg:DI 24) (reg:DI 25)])))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"!TARGET_OPEN_VMS"
"%E1 $24,$25,$27"
"%E0 $24,$25,$27"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
(define_insn "*divmoddi_internal"
[(set (reg:DI 27)
(match_operator:DI 1 "divmod_operator"
(match_operator:DI 0 "divmod_operator"
[(reg:DI 24) (reg:DI 25)]))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"!TARGET_OPEN_VMS"
"%E1 $24,$25,$27"
"%E0 $24,$25,$27"
[(set_attr "type" "jsr")
(set_attr "length" "8")])
......
gcc/config/arm/arm.md
......@@ -1708,11 +1708,11 @@
(and:SI (match_operand:SI 0 "s_register_operand" "r,r")
(match_operand:SI 1 "arm_not_operand" "rI,K"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=X,r"))]
(clobber (match_scratch:SI 2 "=X,r"))]
"TARGET_ARM"
"@
tst%?\\t%0, %1
bic%?s\\t%3, %0, #%B1"
bic%?s\\t%2, %0, #%B1"
[(set_attr "conds" "set")]
)
......
gcc/config/i960/i960.md
......@@ -164,53 +164,53 @@
(define_insn ""
[(set (pc)
(if_then_else
(ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(ne (sign_extract:SI (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(match_operand:SI 2 "arith_operand" "dI"))
(match_operand:SI 1 "arith_operand" "dI"))
(const_int 0))
(label_ref (match_operand 3 "" ""))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"bbs%+ %2,%1,%l3"
"bbs%+ %1,%0,%l2"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc)
(if_then_else
(eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
(eq (sign_extract:SI (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(match_operand:SI 2 "arith_operand" "dI"))
(match_operand:SI 1 "arith_operand" "dI"))
(const_int 0))
(label_ref (match_operand 3 "" ""))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"bbc%+ %2,%1,%l3"
"bbc%+ %1,%0,%l2"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc)
(if_then_else
(ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(ne (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(match_operand:SI 2 "arith_operand" "dI"))
(match_operand:SI 1 "arith_operand" "dI"))
(const_int 0))
(label_ref (match_operand 3 "" ""))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"bbs%+ %2,%1,%l3"
"bbs%+ %1,%0,%l2"
[(set_attr "type" "branch")])
(define_insn ""
[(set (pc)
(if_then_else
(eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
(eq (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
(const_int 1)
(match_operand:SI 2 "arith_operand" "dI"))
(match_operand:SI 1 "arith_operand" "dI"))
(const_int 0))
(label_ref (match_operand 3 "" ""))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"bbc%+ %2,%1,%l3"
"bbc%+ %1,%0,%l2"
[(set_attr "type" "branch")])
;; ??? These will never match. The LOG_LINKs necessary to make these match
......
gcc/config/ia64/ia64.md
......@@ -1662,7 +1662,7 @@
(and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
(const_int 1))
(const_int 0))
(match_operand:BI 3 "register_operand" "0")))]
(match_operand:BI 2 "register_operand" "0")))]
""
"tbit.nz.and.orcm %0, %I0 = %1, 0"
[(set_attr "itanium_class" "tbit")])
......@@ -1672,7 +1672,7 @@
(and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
(const_int 1))
(const_int 0))
(match_operand:BI 3 "register_operand" "0")))]
(match_operand:BI 2 "register_operand" "0")))]
""
"tbit.z.and.orcm %0, %I0 = %1, 0"
[(set_attr "itanium_class" "tbit")])
......@@ -1786,7 +1786,7 @@
(ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
(const_int 1))
(const_int 0))
(match_operand:BI 3 "register_operand" "0")))]
(match_operand:BI 2 "register_operand" "0")))]
""
"tbit.nz.or.andcm %0, %I0 = %1, 0"
[(set_attr "itanium_class" "tbit")])
......@@ -1796,7 +1796,7 @@
(ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
(const_int 1))
(const_int 0))
(match_operand:BI 3 "register_operand" "0")))]
(match_operand:BI 2 "register_operand" "0")))]
""
"tbit.z.or.andcm %0, %I0 = %1, 0"
[(set_attr "itanium_class" "tbit")])
......
gcc/config/m68k/m68k.md
......@@ -5277,17 +5277,17 @@
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
(const_int 32)
(match_operand:SI 2 "const_int_operand" "n"))
(match_operand:SI 3 "general_src_operand" "rmSi"))]
(match_operand:SI 1 "const_int_operand" "n"))
(match_operand:SI 2 "general_src_operand" "rmSi"))]
"TARGET_68020 && TARGET_BITFIELD
&& (INTVAL (operands[2]) % 8) == 0
&& (INTVAL (operands[1]) % 8) == 0
&& ! mode_dependent_address_p (XEXP (operands[0], 0))"
"*
{
operands[0]
= adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
= adj_offsettable_operand (operands[0], INTVAL (operands[1]) / 8);
return \"move%.l %3,%0\";
return \"move%.l %2,%0\";
}")
(define_insn ""
......@@ -5331,14 +5331,14 @@
[(set (match_operand:SI 0 "general_operand" "=rm")
(zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
(const_int 32)
(match_operand:SI 3 "const_int_operand" "n")))]
(match_operand:SI 2 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
&& (INTVAL (operands[3]) % 8) == 0
&& (INTVAL (operands[2]) % 8) == 0
&& ! mode_dependent_address_p (XEXP (operands[1], 0))"
"*
{
operands[1]
= adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
= adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
return \"move%.l %1,%0\";
}")
......@@ -5385,14 +5385,14 @@
[(set (match_operand:SI 0 "general_operand" "=rm")
(sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
(const_int 32)
(match_operand:SI 3 "const_int_operand" "n")))]
(match_operand:SI 2 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
&& (INTVAL (operands[3]) % 8) == 0
&& (INTVAL (operands[2]) % 8) == 0
&& ! mode_dependent_address_p (XEXP (operands[1], 0))"
"*
{
operands[1]
= adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
= adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
return \"move%.l %1,%0\";
}")
......
gcc/config/mips/mips.md
......@@ -2291,7 +2291,7 @@
(set (match_operand:SI 3 "register_operand" "=h")
(mod:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:SI 6 "=a"))]
(clobber (match_scratch:SI 4 "=a"))]
"optimize"
"div\\t$0,%1,%2"
[(set_attr "type" "idiv")
......@@ -2338,7 +2338,7 @@
(set (match_operand:DI 3 "register_operand" "=h")
(mod:DI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:DI 6 "=a"))]
(clobber (match_scratch:DI 4 "=a"))]
"TARGET_64BIT && optimize"
"ddiv\\t$0,%1,%2"
[(set_attr "type" "idiv")
......@@ -2376,7 +2376,7 @@
(set (match_operand:SI 3 "register_operand" "=h")
(umod:SI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:SI 6 "=a"))]
(clobber (match_scratch:SI 4 "=a"))]
"optimize"
"divu\\t$0,%1,%2"
[(set_attr "type" "idiv")
......@@ -2414,7 +2414,7 @@
(set (match_operand:DI 3 "register_operand" "=h")
(umod:DI (match_dup 1)
(match_dup 2)))
(clobber (match_scratch:DI 6 "=a"))]
(clobber (match_scratch:DI 4 "=a"))]
"TARGET_64BIT && optimize"
"ddivu\\t$0,%1,%2"
[(set_attr "type" "idiv")
......
gcc/config/rs6000/rs6000.md
......@@ -9552,7 +9552,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
(use (reg:SI 11))
(set (reg:SI 2)
(mem:SI (plus:SI (reg:SI 1) (const_int 20))))
(clobber (match_scratch:SI 3 "=l"))]
(clobber (match_scratch:SI 2 "=l"))]
"TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;{l|lwz} 2,20(1)"
[(set_attr "type" "jmpreg")
......@@ -9577,7 +9577,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
(use (reg:DI 11))
(set (reg:DI 2)
(mem:DI (plus:DI (reg:DI 1) (const_int 40))))
(clobber (match_scratch:SI 3 "=l"))]
(clobber (match_scratch:SI 2 "=l"))]
"TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
"b%T0l\;ld 2,40(1)"
[(set_attr "type" "jmpreg")
......@@ -12568,7 +12568,7 @@ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
(compare:CCEQ (match_operator:SI 2
"branch_positive_comparison_operator"
[(match_operand 3
[(match_operand 1
"cc_reg_operand" "y")
(const_int 0)])
(const_int 0)))]
......
gcc/config/sh/sh.md
......@@ -3172,7 +3172,7 @@
(define_insn "*movsi_y"
[(set (match_operand:SI 0 "register_operand" "=y,y")
(match_operand:SI 1 "immediate_operand" "Qi,I"))
(clobber (match_scratch:SI 3 "=&z,r"))]
(clobber (match_scratch:SI 2 "=&z,r"))]
"TARGET_SH3E
&& (reload_in_progress || reload_completed)"
"#"
......
gcc/config/sparc/sparc.md
......@@ -8113,19 +8113,19 @@
;; Optimize (1LL<<x)-1
;; XXX this also needs to be fixed to handle equal subregs
;; XXX first before we could re-enable it.
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=h")
(plus:DI (ashift:DI (const_int 1)
(match_operand:SI 2 "arith_operand" "rI"))
(const_int -1)))]
"0 && TARGET_V8PLUS"
"*
{
if (GET_CODE (operands[2]) == REG && REGNO (operands[2]) == REGNO (operands[0]))
return \"mov\\t1, %L0\;sllx\\t%L0, %2, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
return \"mov\\t1, %H0\;sllx\\t%H0, %2, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
}"
[(set_attr "length" "4")])
;(define_insn ""
; [(set (match_operand:DI 0 "register_operand" "=h")
; (plus:DI (ashift:DI (const_int 1)
; (match_operand:SI 1 "arith_operand" "rI"))
; (const_int -1)))]
; "0 && TARGET_V8PLUS"
; "*
;{
; if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0]))
; return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
; return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
;}"
; [(set_attr "length" "4")])
(define_insn "*cmp_cc_ashift_1"
[(set (reg:CC_NOOV 100)
......
gcc/genoutput.c
......@@ -182,6 +182,7 @@ static int compare_operands PARAMS ((struct operand_data *,
static void place_operands PARAMS ((struct data *));
static void process_template PARAMS ((struct data *, const char *));
static void validate_insn_alternatives PARAMS ((struct data *));
static void validate_insn_operands PARAMS ((struct data *));
static void gen_insn PARAMS ((rtx, int));
static void gen_peephole PARAMS ((rtx, int));
static void gen_expand PARAMS ((rtx, int));
......@@ -738,6 +739,22 @@ validate_insn_alternatives (d)
d->n_alternatives = n;
}
/* Verify that there are no gaps in operand numbers for INSNs. */
static void
validate_insn_operands (d)
struct data *d;
{
int i;
for (i = 0; i < d->n_operands; ++i)
if (d->operand[i].seen == 0)
{
message_with_line (d->lineno, "missing operand %d", i);
have_error = 1;
}
}
/* Look at a define_insn just read. Assign its code number. Record
on idata the template and the number of arguments. If the insn has
a hairy output action, output a function for now. */
......@@ -774,6 +791,7 @@ gen_insn (insn, lineno)
d->n_operands = max_opno + 1;
d->n_dups = num_dups;
validate_insn_operands (d);
validate_insn_alternatives (d);
place_operands (d);
process_template (d, XSTR (insn, 3));
......
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