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riscv-gcc-1
Commit c7453384 by Eric Christopher Committed by Eric Christopher
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s390.c (s390_valid_pointer_mode): New. 

2003-07-22  Eric Christopher <echristo@redhat.com>

	* config/s390.c (s390_valid_pointer_mode): New.
	(TARGET_VALID_POINTER_MODE): Use.
	(s390_emit_prologue): Add tpf profiling hooks.
	(s390_emit_epilogue): Ditto.
	* config/s390.h (MASK_TPF): New.
	(TARGET_TPF): Use.
	(POINTERS_EXTEND_UNSIGNED): Define.
	* config/s390.md (ptr_extend): New pattern.

From-SVN: r69674
parent 817aed6f
Showing with 574 additions and 476 deletions
gcc/ChangeLog
2003-07-22 Eric Christopher <echristo@redhat.com>
* config/s390.c (s390_valid_pointer_mode): New.
(TARGET_VALID_POINTER_MODE): Use.
(s390_emit_prologue): Add tpf profiling hooks.
(s390_emit_epilogue): Ditto.
* config/s390.h (MASK_TPF): New.
(TARGET_TPF): Use.
(POINTERS_EXTEND_UNSIGNED): Define.
* config/s390.md (ptr_extend): New pattern.
2003-07-22 Zack Weinberg <zack@codesourcery.com> 2003-07-22 Zack Weinberg <zack@codesourcery.com>
* hashtable.c (approx_sqrt): Make static. * hashtable.c (approx_sqrt): Make static.
......
gcc/config/s390/s390.c
...@@ -55,13 +55,13 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA ...@@ -55,13 +55,13 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int)); static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int));
static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx, static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx,
unsigned HOST_WIDE_INT)); unsigned HOST_WIDE_INT));
static void s390_encode_section_info PARAMS ((tree, rtx, int)); static void s390_encode_section_info PARAMS ((tree, rtx, int));
static bool s390_cannot_force_const_mem PARAMS ((rtx)); static bool s390_cannot_force_const_mem PARAMS ((rtx));
static rtx s390_delegitimize_address PARAMS ((rtx)); static rtx s390_delegitimize_address PARAMS ((rtx));
static void s390_init_builtins PARAMS ((void)); static void s390_init_builtins PARAMS ((void));
static rtx s390_expand_builtin PARAMS ((tree, rtx, rtx, static rtx s390_expand_builtin PARAMS ((tree, rtx, rtx,
enum machine_mode, int)); enum machine_mode, int));
static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree)); HOST_WIDE_INT, tree));
...@@ -76,7 +76,7 @@ static int s390_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int)); ...@@ -76,7 +76,7 @@ static int s390_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
static bool s390_rtx_costs PARAMS ((rtx, int, int, int *)); static bool s390_rtx_costs PARAMS ((rtx, int, int, int *));
static int s390_address_cost PARAMS ((rtx)); static int s390_address_cost PARAMS ((rtx));
static void s390_reorg PARAMS ((void)); static void s390_reorg PARAMS ((void));
static bool s390_valid_pointer_mode PARAMS ((enum machine_mode));
#undef TARGET_ASM_ALIGNED_HI_OP #undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
...@@ -138,6 +138,9 @@ static void s390_reorg PARAMS ((void)); ...@@ -138,6 +138,9 @@ static void s390_reorg PARAMS ((void));
#undef TARGET_MACHINE_DEPENDENT_REORG #undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
#undef TARGET_VALID_POINTER_MODE
#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
struct gcc_target targetm = TARGET_INITIALIZER; struct gcc_target targetm = TARGET_INITIALIZER;
extern int reload_completed; extern int reload_completed;
...@@ -233,11 +236,11 @@ static struct machine_function * s390_init_machine_status PARAMS ((void)); ...@@ -233,11 +236,11 @@ static struct machine_function * s390_init_machine_status PARAMS ((void));
#define DISP_IN_RANGE(d) \ #define DISP_IN_RANGE(d) \
(TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
: ((d) >= 0 && (d) <= 4095)) : ((d) >= 0 && (d) <= 4095))
/* Return true if SET either doesn't set the CC register, or else /* Return true if SET either doesn't set the CC register, or else
the source and destination have matching CC modes and that the source and destination have matching CC modes and that
CC mode is at least as constrained as REQ_MODE. */ CC mode is at least as constrained as REQ_MODE. */
static int static int
s390_match_ccmode_set (set, req_mode) s390_match_ccmode_set (set, req_mode)
rtx set; rtx set;
...@@ -279,19 +282,19 @@ s390_match_ccmode_set (set, req_mode) ...@@ -279,19 +282,19 @@ s390_match_ccmode_set (set, req_mode)
if (req_mode != CCAmode) if (req_mode != CCAmode)
return 0; return 0;
break; break;
default: default:
abort (); abort ();
} }
return (GET_MODE (SET_SRC (set)) == set_mode); return (GET_MODE (SET_SRC (set)) == set_mode);
} }
/* Return true if every SET in INSN that sets the CC register /* Return true if every SET in INSN that sets the CC register
has source and destination with matching CC modes and that has source and destination with matching CC modes and that
CC mode is at least as constrained as REQ_MODE. CC mode is at least as constrained as REQ_MODE.
If REQ_MODE is VOIDmode, always return false. */ If REQ_MODE is VOIDmode, always return false. */
int int
s390_match_ccmode (insn, req_mode) s390_match_ccmode (insn, req_mode)
rtx insn; rtx insn;
...@@ -318,9 +321,9 @@ s390_match_ccmode (insn, req_mode) ...@@ -318,9 +321,9 @@ s390_match_ccmode (insn, req_mode)
return 1; return 1;
} }
/* If a test-under-mask instruction can be used to implement /* If a test-under-mask instruction can be used to implement
(compare (and ... OP1) OP2), return the CC mode required (compare (and ... OP1) OP2), return the CC mode required
to do that. Otherwise, return VOIDmode. to do that. Otherwise, return VOIDmode.
MIXED is true if the instruction can distinguish between MIXED is true if the instruction can distinguish between
CC1 and CC2 for mixed selected bits (TMxx), it is false CC1 and CC2 for mixed selected bits (TMxx), it is false
if the instruction cannot (TM). */ if the instruction cannot (TM). */
...@@ -357,12 +360,12 @@ s390_tm_ccmode (op1, op2, mixed) ...@@ -357,12 +360,12 @@ s390_tm_ccmode (op1, op2, mixed)
return VOIDmode; return VOIDmode;
} }
/* Given a comparison code OP (EQ, NE, etc.) and the operands /* Given a comparison code OP (EQ, NE, etc.) and the operands
OP0 and OP1 of a COMPARE, return the mode to be used for the OP0 and OP1 of a COMPARE, return the mode to be used for the
comparison. */ comparison. */
enum machine_mode enum machine_mode
s390_select_ccmode (code, op0, op1) s390_select_ccmode (code, op0, op1)
enum rtx_code code; enum rtx_code code;
rtx op0; rtx op0;
rtx op1; rtx op1;
...@@ -372,7 +375,7 @@ s390_select_ccmode (code, op0, op1) ...@@ -372,7 +375,7 @@ s390_select_ccmode (code, op0, op1)
case EQ: case EQ:
case NE: case NE:
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K')) && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
return CCAPmode; return CCAPmode;
if (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS if (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
|| GET_CODE (op1) == NEG) || GET_CODE (op1) == NEG)
...@@ -391,11 +394,11 @@ s390_select_ccmode (code, op0, op1) ...@@ -391,11 +394,11 @@ s390_select_ccmode (code, op0, op1)
} }
} }
if (register_operand (op0, HImode) if (register_operand (op0, HImode)
&& GET_CODE (op1) == CONST_INT && GET_CODE (op1) == CONST_INT
&& (INTVAL (op1) == -1 || INTVAL (op1) == 65535)) && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
return CCT3mode; return CCT3mode;
if (register_operand (op0, QImode) if (register_operand (op0, QImode)
&& GET_CODE (op1) == CONST_INT && GET_CODE (op1) == CONST_INT
&& (INTVAL (op1) == -1 || INTVAL (op1) == 255)) && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
return CCT3mode; return CCT3mode;
...@@ -407,7 +410,7 @@ s390_select_ccmode (code, op0, op1) ...@@ -407,7 +410,7 @@ s390_select_ccmode (code, op0, op1)
case GE: case GE:
case GT: case GT:
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K')) && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
{ {
if (INTVAL (XEXP((op0), 1)) < 0) if (INTVAL (XEXP((op0), 1)) < 0)
return CCANmode; return CCANmode;
...@@ -452,13 +455,13 @@ s390_select_ccmode (code, op0, op1) ...@@ -452,13 +455,13 @@ s390_select_ccmode (code, op0, op1)
} }
} }
/* Return branch condition mask to implement a branch /* Return branch condition mask to implement a branch
specified by CODE. */ specified by CODE. */
static int static int
s390_branch_condition_mask (code) s390_branch_condition_mask (code)
rtx code; rtx code;
{ {
const int CC0 = 1 << 3; const int CC0 = 1 << 3;
const int CC1 = 1 << 2; const int CC1 = 1 << 2;
const int CC2 = 1 << 1; const int CC2 = 1 << 1;
...@@ -646,8 +649,8 @@ s390_branch_condition_mask (code) ...@@ -646,8 +649,8 @@ s390_branch_condition_mask (code)
} }
} }
/* If INV is false, return assembler mnemonic string to implement /* If INV is false, return assembler mnemonic string to implement
a branch specified by CODE. If INV is true, return mnemonic a branch specified by CODE. If INV is true, return mnemonic
for the corresponding inverted branch. */ for the corresponding inverted branch. */
static const char * static const char *
...@@ -675,7 +678,7 @@ s390_branch_condition_mnemonic (code, inv) ...@@ -675,7 +678,7 @@ s390_branch_condition_mnemonic (code, inv)
} }
/* If OP is an integer constant of mode MODE with exactly one /* If OP is an integer constant of mode MODE with exactly one
HImode subpart unequal to DEF, return the number of that HImode subpart unequal to DEF, return the number of that
subpart. As a special case, all HImode subparts of OP are subpart. As a special case, all HImode subparts of OP are
equal to DEF, return zero. Otherwise, return -1. */ equal to DEF, return zero. Otherwise, return -1. */
...@@ -738,10 +741,10 @@ s390_single_hi (op, mode, def) ...@@ -738,10 +741,10 @@ s390_single_hi (op, mode, def)
return part == -1 ? 0 : (n_parts - 1 - part); return part == -1 ? 0 : (n_parts - 1 - part);
} }
return -1; return -1;
} }
/* Extract the HImode part number PART from integer /* Extract the HImode part number PART from integer
constant OP of mode MODE. */ constant OP of mode MODE. */
int int
...@@ -771,14 +774,14 @@ s390_extract_hi (op, mode, part) ...@@ -771,14 +774,14 @@ s390_extract_hi (op, mode, part)
value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op), value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op),
part -= HOST_BITS_PER_WIDE_INT / 16; part -= HOST_BITS_PER_WIDE_INT / 16;
return ((value >> (16 * part)) & 0xffff); return ((value >> (16 * part)) & 0xffff);
} }
abort (); abort ();
} }
/* If OP is an integer constant of mode MODE with exactly one /* If OP is an integer constant of mode MODE with exactly one
QImode subpart unequal to DEF, return the number of that QImode subpart unequal to DEF, return the number of that
subpart. As a special case, all QImode subparts of OP are subpart. As a special case, all QImode subparts of OP are
equal to DEF, return zero. Otherwise, return -1. */ equal to DEF, return zero. Otherwise, return -1. */
...@@ -841,10 +844,10 @@ s390_single_qi (op, mode, def) ...@@ -841,10 +844,10 @@ s390_single_qi (op, mode, def)
return part == -1 ? 0 : (n_parts - 1 - part); return part == -1 ? 0 : (n_parts - 1 - part);
} }
return -1; return -1;
} }
/* Extract the QImode part number PART from integer /* Extract the QImode part number PART from integer
constant OP of mode MODE. */ constant OP of mode MODE. */
int int
...@@ -874,14 +877,14 @@ s390_extract_qi (op, mode, part) ...@@ -874,14 +877,14 @@ s390_extract_qi (op, mode, part)
value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op), value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op),
part -= HOST_BITS_PER_WIDE_INT / 8; part -= HOST_BITS_PER_WIDE_INT / 8;
return ((value >> (8 * part)) & 0xff); return ((value >> (8 * part)) & 0xff);
} }
abort (); abort ();
} }
/* Check whether we can (and want to) split a double-word /* Check whether we can (and want to) split a double-word
move in mode MODE from SRC to DST into two single-word move in mode MODE from SRC to DST into two single-word
moves, moving the subword FIRST_SUBWORD first. */ moves, moving the subword FIRST_SUBWORD first. */
bool bool
...@@ -917,7 +920,7 @@ s390_split_ok_p (dst, src, mode, first_subword) ...@@ -917,7 +920,7 @@ s390_split_ok_p (dst, src, mode, first_subword)
} }
/* Change optimizations to be performed, depending on the /* Change optimizations to be performed, depending on the
optimization level. optimization level.
LEVEL is the optimization level specified; 2 if `-O2' is LEVEL is the optimization level specified; 2 if `-O2' is
...@@ -953,7 +956,7 @@ override_options () ...@@ -953,7 +956,7 @@ override_options ()
{"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT}, {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
{"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT}, {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
{"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH}, {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
{"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT}, | PF_LONG_DISPLACEMENT},
}; };
...@@ -1026,7 +1029,7 @@ const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = ...@@ -1026,7 +1029,7 @@ const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS,
ADDR_REGS, NO_REGS, ADDR_REGS ADDR_REGS, NO_REGS, ADDR_REGS
}; };
/* Return attribute type of insn. */ /* Return attribute type of insn. */
...@@ -1044,7 +1047,7 @@ s390_safe_attr_type (insn) ...@@ -1044,7 +1047,7 @@ s390_safe_attr_type (insn)
/* Return true if OP a (const_int 0) operand. /* Return true if OP a (const_int 0) operand.
OP is the current operation. OP is the current operation.
MODE is the current operation mode. */ MODE is the current operation mode. */
int int
const0_operand (op, mode) const0_operand (op, mode)
register rtx op; register rtx op;
...@@ -1066,7 +1069,7 @@ consttable_operand (op, mode) ...@@ -1066,7 +1069,7 @@ consttable_operand (op, mode)
} }
/* Return true if the mode of operand OP matches MODE. /* Return true if the mode of operand OP matches MODE.
If MODE is set to VOIDmode, set it to the mode of OP. */ If MODE is set to VOIDmode, set it to the mode of OP. */
static int static int
check_mode (op, mode) check_mode (op, mode)
...@@ -1118,7 +1121,7 @@ larl_operand (op, mode) ...@@ -1118,7 +1121,7 @@ larl_operand (op, mode)
if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32 if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
|| INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32)) || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
return 0; return 0;
#endif #endif
op = XEXP (op, 0); op = XEXP (op, 0);
} }
...@@ -1166,8 +1169,8 @@ general_s_operand (op, mode, allow_immediate) ...@@ -1166,8 +1169,8 @@ general_s_operand (op, mode, allow_immediate)
/* Just like memory_operand, allow (subreg (mem ...)) /* Just like memory_operand, allow (subreg (mem ...))
after reload. */ after reload. */
if (reload_completed if (reload_completed
&& GET_CODE (op) == SUBREG && GET_CODE (op) == SUBREG
&& GET_CODE (SUBREG_REG (op)) == MEM) && GET_CODE (SUBREG_REG (op)) == MEM)
op = SUBREG_REG (op); op = SUBREG_REG (op);
...@@ -1176,7 +1179,7 @@ general_s_operand (op, mode, allow_immediate) ...@@ -1176,7 +1179,7 @@ general_s_operand (op, mode, allow_immediate)
/* Constants that we are sure will be forced to the /* Constants that we are sure will be forced to the
literal pool in reload are OK as s-operand. Note literal pool in reload are OK as s-operand. Note
that we cannot call s390_preferred_reload_class here that we cannot call s390_preferred_reload_class here
because it might not be known yet at this point because it might not be known yet at this point
whether the current function is a leaf or not. */ whether the current function is a leaf or not. */
case CONST_INT: case CONST_INT:
case CONST_DOUBLE: case CONST_DOUBLE:
...@@ -1193,7 +1196,7 @@ general_s_operand (op, mode, allow_immediate) ...@@ -1193,7 +1196,7 @@ general_s_operand (op, mode, allow_immediate)
case MEM: case MEM:
if (GET_CODE (XEXP (op, 0)) == ADDRESSOF) if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
return 1; return 1;
if (s390_decompose_address (XEXP (op, 0), &addr) if (s390_decompose_address (XEXP (op, 0), &addr)
&& !addr.indx) && !addr.indx)
return 1; return 1;
break; break;
...@@ -1217,8 +1220,8 @@ s_operand (op, mode) ...@@ -1217,8 +1220,8 @@ s_operand (op, mode)
return general_s_operand (op, mode, 0); return general_s_operand (op, mode, 0);
} }
/* Return true if OP is a valid S-type operand or an immediate /* Return true if OP is a valid S-type operand or an immediate
operand that can be addressed as S-type operand by forcing operand that can be addressed as S-type operand by forcing
it into the literal pool. it into the literal pool.
OP is the current operation. OP is the current operation.
MODE is the current operation mode. */ MODE is the current operation mode. */
...@@ -1472,7 +1475,7 @@ tls_symbolic_operand (op) ...@@ -1472,7 +1475,7 @@ tls_symbolic_operand (op)
} }
/* Return true if OP is a load multiple operation. It is known to be a /* Return true if OP is a load multiple operation. It is known to be a
PARALLEL and the first section will be tested. PARALLEL and the first section will be tested.
OP is the current operation. OP is the current operation.
MODE is the current operation mode. */ MODE is the current operation mode. */
...@@ -1502,7 +1505,7 @@ load_multiple_operation (op, mode) ...@@ -1502,7 +1505,7 @@ load_multiple_operation (op, mode)
if (GET_CODE (src_addr) == REG) if (GET_CODE (src_addr) == REG)
off = 0; off = 0;
else if (GET_CODE (src_addr) == PLUS else if (GET_CODE (src_addr) == PLUS
&& GET_CODE (XEXP (src_addr, 0)) == REG && GET_CODE (XEXP (src_addr, 0)) == REG
&& GET_CODE (XEXP (src_addr, 1)) == CONST_INT) && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
{ {
off = INTVAL (XEXP (src_addr, 1)); off = INTVAL (XEXP (src_addr, 1));
...@@ -1536,7 +1539,7 @@ load_multiple_operation (op, mode) ...@@ -1536,7 +1539,7 @@ load_multiple_operation (op, mode)
} }
/* Return true if OP is a store multiple operation. It is known to be a /* Return true if OP is a store multiple operation. It is known to be a
PARALLEL and the first section will be tested. PARALLEL and the first section will be tested.
OP is the current operation. OP is the current operation.
MODE is the current operation mode. */ MODE is the current operation mode. */
...@@ -1565,7 +1568,7 @@ store_multiple_operation (op, mode) ...@@ -1565,7 +1568,7 @@ store_multiple_operation (op, mode)
if (GET_CODE (dest_addr) == REG) if (GET_CODE (dest_addr) == REG)
off = 0; off = 0;
else if (GET_CODE (dest_addr) == PLUS else if (GET_CODE (dest_addr) == PLUS
&& GET_CODE (XEXP (dest_addr, 0)) == REG && GET_CODE (XEXP (dest_addr, 0)) == REG
&& GET_CODE (XEXP (dest_addr, 1)) == CONST_INT) && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
{ {
off = INTVAL (XEXP (dest_addr, 1)); off = INTVAL (XEXP (dest_addr, 1));
...@@ -1661,8 +1664,8 @@ tls_symbolic_reference_mentioned_p (op) ...@@ -1661,8 +1664,8 @@ tls_symbolic_reference_mentioned_p (op)
} }
/* Return true if OP is a legitimate general operand when /* Return true if OP is a legitimate general operand when
generating PIC code. It is given that flag_pic is on generating PIC code. It is given that flag_pic is on
and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */ and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
int int
...@@ -1673,7 +1676,7 @@ legitimate_pic_operand_p (op) ...@@ -1673,7 +1676,7 @@ legitimate_pic_operand_p (op)
if (!SYMBOLIC_CONST (op)) if (!SYMBOLIC_CONST (op))
return 1; return 1;
/* Reject everything else; must be handled /* Reject everything else; must be handled
via emit_symbolic_move. */ via emit_symbolic_move. */
return 0; return 0;
} }
...@@ -1771,7 +1774,7 @@ s390_cannot_force_const_mem (x) ...@@ -1771,7 +1774,7 @@ s390_cannot_force_const_mem (x)
} }
/* Returns true if the constant value OP is a legitimate general /* Returns true if the constant value OP is a legitimate general
operand during and after reload. The difference to operand during and after reload. The difference to
legitimate_constant_p is that this function will not accept legitimate_constant_p is that this function will not accept
a constant that would need to be forced to the literal pool a constant that would need to be forced to the literal pool
before it can be used as operand. */ before it can be used as operand. */
...@@ -1781,7 +1784,7 @@ legitimate_reload_constant_p (op) ...@@ -1781,7 +1784,7 @@ legitimate_reload_constant_p (op)
register rtx op; register rtx op;
{ {
/* Accept la(y) operands. */ /* Accept la(y) operands. */
if (GET_CODE (op) == CONST_INT if (GET_CODE (op) == CONST_INT
&& DISP_IN_RANGE (INTVAL (op))) && DISP_IN_RANGE (INTVAL (op)))
return 1; return 1;
...@@ -1871,7 +1874,7 @@ s390_secondary_input_reload_class (class, mode, in) ...@@ -1871,7 +1874,7 @@ s390_secondary_input_reload_class (class, mode, in)
/* Return the register class of a scratch register needed to /* Return the register class of a scratch register needed to
store a register of class CLASS in MODE into OUT: store a register of class CLASS in MODE into OUT:
We need a temporary when storing a double-word to a We need a temporary when storing a double-word to a
non-offsettable memory address. */ non-offsettable memory address. */
enum reg_class enum reg_class
...@@ -1892,7 +1895,7 @@ s390_secondary_output_reload_class (class, mode, out) ...@@ -1892,7 +1895,7 @@ s390_secondary_output_reload_class (class, mode, out)
} }
/* Return true if OP is a PLUS that is not a legitimate /* Return true if OP is a PLUS that is not a legitimate
operand for the LA instruction. operand for the LA instruction.
OP is the current operation. OP is the current operation.
MODE is the current operation mode. */ MODE is the current operation mode. */
...@@ -2147,7 +2150,7 @@ s390_decompose_address (addr, out) ...@@ -2147,7 +2150,7 @@ s390_decompose_address (addr, out)
{ {
pointer = TRUE; pointer = TRUE;
} }
/* Likewise if a constant offset is present. */ /* Likewise if a constant offset is present. */
else if (GET_CODE (disp) == CONST else if (GET_CODE (disp) == CONST
&& GET_CODE (XEXP (disp, 0)) == PLUS && GET_CODE (XEXP (disp, 0)) == PLUS
...@@ -2159,7 +2162,7 @@ s390_decompose_address (addr, out) ...@@ -2159,7 +2162,7 @@ s390_decompose_address (addr, out)
pointer = TRUE; pointer = TRUE;
} }
/* We can convert literal pool addresses to /* We can convert literal pool addresses to
displacements by basing them off the base register. */ displacements by basing them off the base register. */
else else
{ {
...@@ -2186,7 +2189,7 @@ s390_decompose_address (addr, out) ...@@ -2186,7 +2189,7 @@ s390_decompose_address (addr, out)
if (offset && offset >= GET_MODE_SIZE (get_pool_mode (disp))) if (offset && offset >= GET_MODE_SIZE (get_pool_mode (disp)))
return FALSE; return FALSE;
/* Either base or index must be free to /* Either base or index must be free to
hold the base register. */ hold the base register. */
if (base && indx) if (base && indx)
return FALSE; return FALSE;
...@@ -2197,7 +2200,7 @@ s390_decompose_address (addr, out) ...@@ -2197,7 +2200,7 @@ s390_decompose_address (addr, out)
else else
base = gen_rtx_REG (Pmode, BASE_REGISTER); base = gen_rtx_REG (Pmode, BASE_REGISTER);
disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp), disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
UNSPEC_LTREL_OFFSET); UNSPEC_LTREL_OFFSET);
disp = gen_rtx_CONST (Pmode, disp); disp = gen_rtx_CONST (Pmode, disp);
...@@ -2210,7 +2213,7 @@ s390_decompose_address (addr, out) ...@@ -2210,7 +2213,7 @@ s390_decompose_address (addr, out)
if (!base && !indx) if (!base && !indx)
pointer = TRUE; pointer = TRUE;
if (out) if (out)
{ {
out->base = base; out->base = base;
...@@ -2273,7 +2276,7 @@ legitimate_la_operand_p (op) ...@@ -2273,7 +2276,7 @@ legitimate_la_operand_p (op)
/* Return 1 if OP is a valid operand for the LA instruction, /* Return 1 if OP is a valid operand for the LA instruction,
and we prefer to use LA over addition to compute it. */ and we prefer to use LA over addition to compute it. */
int int
preferred_la_operand_p (op) preferred_la_operand_p (op)
register rtx op; register rtx op;
...@@ -2343,8 +2346,8 @@ legitimize_pic_address (orig, reg) ...@@ -2343,8 +2346,8 @@ legitimize_pic_address (orig, reg)
/* This is a local symbol. */ /* This is a local symbol. */
if (TARGET_64BIT && larl_operand (addr, VOIDmode)) if (TARGET_64BIT && larl_operand (addr, VOIDmode))
{ {
/* Access local symbols PC-relative via LARL. /* Access local symbols PC-relative via LARL.
This is the same as in the non-PIC case, so it is This is the same as in the non-PIC case, so it is
handled automatically ... */ handled automatically ... */
} }
else else
...@@ -2408,7 +2411,7 @@ legitimize_pic_address (orig, reg) ...@@ -2408,7 +2411,7 @@ legitimize_pic_address (orig, reg)
} }
else else
{ {
/* If the GOT offset might be >= 4k, we have to load it /* If the GOT offset might be >= 4k, we have to load it
from the literal pool (@GOT). */ from the literal pool (@GOT). */
rtx temp = gen_reg_rtx (Pmode); rtx temp = gen_reg_rtx (Pmode);
...@@ -2427,7 +2430,7 @@ legitimize_pic_address (orig, reg) ...@@ -2427,7 +2430,7 @@ legitimize_pic_address (orig, reg)
emit_move_insn (reg, new); emit_move_insn (reg, new);
new = reg; new = reg;
} }
} }
else else
{ {
if (GET_CODE (addr) == CONST) if (GET_CODE (addr) == CONST)
...@@ -2467,7 +2470,7 @@ legitimize_pic_address (orig, reg) ...@@ -2467,7 +2470,7 @@ legitimize_pic_address (orig, reg)
regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
addr = XVECEXP (addr, 0, 0); addr = XVECEXP (addr, 0, 0);
addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
UNSPEC_PLTOFF); UNSPEC_PLTOFF);
addr = gen_rtx_CONST (Pmode, addr); addr = gen_rtx_CONST (Pmode, addr);
addr = force_const_mem (Pmode, addr); addr = force_const_mem (Pmode, addr);
...@@ -2493,7 +2496,7 @@ legitimize_pic_address (orig, reg) ...@@ -2493,7 +2496,7 @@ legitimize_pic_address (orig, reg)
if (GET_CODE (addr) == PLUS) if (GET_CODE (addr) == PLUS)
{ {
rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1); rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
/* Check first to see if this is a constant offset /* Check first to see if this is a constant offset
from a local symbol reference. */ from a local symbol reference. */
if ((GET_CODE (op0) == LABEL_REF if ((GET_CODE (op0) == LABEL_REF
|| (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0))) || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
...@@ -2503,7 +2506,7 @@ legitimize_pic_address (orig, reg) ...@@ -2503,7 +2506,7 @@ legitimize_pic_address (orig, reg)
{ {
if (INTVAL (op1) & 1) if (INTVAL (op1) & 1)
{ {
/* LARL can't handle odd offsets, so emit a /* LARL can't handle odd offsets, so emit a
pair of LARL and LA. */ pair of LARL and LA. */
rtx temp = reg? reg : gen_reg_rtx (Pmode); rtx temp = reg? reg : gen_reg_rtx (Pmode);
...@@ -2539,7 +2542,7 @@ legitimize_pic_address (orig, reg) ...@@ -2539,7 +2542,7 @@ legitimize_pic_address (orig, reg)
if (reload_in_progress || reload_completed) if (reload_in_progress || reload_completed)
regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
UNSPEC_GOTOFF); UNSPEC_GOTOFF);
addr = gen_rtx_PLUS (Pmode, addr, op1); addr = gen_rtx_PLUS (Pmode, addr, op1);
addr = gen_rtx_CONST (Pmode, addr); addr = gen_rtx_CONST (Pmode, addr);
...@@ -2725,7 +2728,7 @@ legitimize_tls_address (addr, reg) ...@@ -2725,7 +2728,7 @@ legitimize_tls_address (addr, reg)
} }
else if (flag_pic) else if (flag_pic)
{ {
/* If the GOT offset might be >= 4k, we have to load it /* If the GOT offset might be >= 4k, we have to load it
from the literal pool. */ from the literal pool. */
if (reload_in_progress || reload_completed) if (reload_in_progress || reload_completed)
...@@ -2859,8 +2862,8 @@ legitimize_address (x, oldx, mode) ...@@ -2859,8 +2862,8 @@ legitimize_address (x, oldx, mode)
else if (flag_pic) else if (flag_pic)
{ {
if (SYMBOLIC_CONST (x) if (SYMBOLIC_CONST (x)
|| (GET_CODE (x) == PLUS || (GET_CODE (x) == PLUS
&& (SYMBOLIC_CONST (XEXP (x, 0)) && (SYMBOLIC_CONST (XEXP (x, 0))
|| SYMBOLIC_CONST (XEXP (x, 1))))) || SYMBOLIC_CONST (XEXP (x, 1)))))
x = legitimize_pic_address (x, 0); x = legitimize_pic_address (x, 0);
...@@ -2872,7 +2875,7 @@ legitimize_address (x, oldx, mode) ...@@ -2872,7 +2875,7 @@ legitimize_address (x, oldx, mode)
/* Optimize loading of large displacements by splitting them /* Optimize loading of large displacements by splitting them
into the multiple of 4K and the rest; this allows the into the multiple of 4K and the rest; this allows the
former to be CSE'd if possible. former to be CSE'd if possible.
Don't do this if the displacement is added to a register Don't do this if the displacement is added to a register
pointing into the stack frame, as the offsets will pointing into the stack frame, as the offsets will
...@@ -2932,9 +2935,9 @@ s390_expand_movstr (dst, src, len) ...@@ -2932,9 +2935,9 @@ s390_expand_movstr (dst, src, len)
rtx src; rtx src;
rtx len; rtx len;
{ {
rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) = rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) =
TARGET_64BIT ? gen_movstr_short_64 : gen_movstr_short_31; TARGET_64BIT ? gen_movstr_short_64 : gen_movstr_short_31;
rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) = rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) =
TARGET_64BIT ? gen_movstr_long_64 : gen_movstr_long_31; TARGET_64BIT ? gen_movstr_long_64 : gen_movstr_long_31;
...@@ -2951,9 +2954,9 @@ s390_expand_movstr (dst, src, len) ...@@ -2951,9 +2954,9 @@ s390_expand_movstr (dst, src, len)
rtx reg0 = gen_reg_rtx (double_mode); rtx reg0 = gen_reg_rtx (double_mode);
rtx reg1 = gen_reg_rtx (double_mode); rtx reg1 = gen_reg_rtx (double_mode);
emit_move_insn (gen_highpart (single_mode, reg0), emit_move_insn (gen_highpart (single_mode, reg0),
force_operand (XEXP (dst, 0), NULL_RTX)); force_operand (XEXP (dst, 0), NULL_RTX));
emit_move_insn (gen_highpart (single_mode, reg1), emit_move_insn (gen_highpart (single_mode, reg1),
force_operand (XEXP (src, 0), NULL_RTX)); force_operand (XEXP (src, 0), NULL_RTX));
convert_move (gen_lowpart (single_mode, reg0), len, 1); convert_move (gen_lowpart (single_mode, reg0), len, 1);
...@@ -2983,14 +2986,14 @@ s390_expand_movstr (dst, src, len) ...@@ -2983,14 +2986,14 @@ s390_expand_movstr (dst, src, len)
blocks = gen_reg_rtx (mode); blocks = gen_reg_rtx (mode);
convert_move (count, len, 1); convert_move (count, len, 1);
emit_cmp_and_jump_insns (count, const0_rtx, emit_cmp_and_jump_insns (count, const0_rtx,
EQ, NULL_RTX, mode, 1, end_label); EQ, NULL_RTX, mode, 1, end_label);
emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX)); emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
dst = change_address (dst, VOIDmode, dst_addr); dst = change_address (dst, VOIDmode, dst_addr);
src = change_address (src, VOIDmode, src_addr); src = change_address (src, VOIDmode, src_addr);
temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0); temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
if (temp != count) if (temp != count)
emit_move_insn (count, temp); emit_move_insn (count, temp);
...@@ -3005,11 +3008,11 @@ s390_expand_movstr (dst, src, len) ...@@ -3005,11 +3008,11 @@ s390_expand_movstr (dst, src, len)
make_tree (type, const0_rtx))); make_tree (type, const0_rtx)));
emit_insn ((*gen_short) (dst, src, GEN_INT (255))); emit_insn ((*gen_short) (dst, src, GEN_INT (255)));
s390_load_address (dst_addr, s390_load_address (dst_addr,
gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
s390_load_address (src_addr, s390_load_address (src_addr,
gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256))); gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0); temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
if (temp != blocks) if (temp != blocks)
emit_move_insn (blocks, temp); emit_move_insn (blocks, temp);
...@@ -3028,9 +3031,9 @@ s390_expand_clrstr (dst, len) ...@@ -3028,9 +3031,9 @@ s390_expand_clrstr (dst, len)
rtx dst; rtx dst;
rtx len; rtx len;
{ {
rtx (*gen_short) PARAMS ((rtx, rtx)) = rtx (*gen_short) PARAMS ((rtx, rtx)) =
TARGET_64BIT ? gen_clrstr_short_64 : gen_clrstr_short_31; TARGET_64BIT ? gen_clrstr_short_64 : gen_clrstr_short_31;
rtx (*gen_long) PARAMS ((rtx, rtx, rtx)) = rtx (*gen_long) PARAMS ((rtx, rtx, rtx)) =
TARGET_64BIT ? gen_clrstr_long_64 : gen_clrstr_long_31; TARGET_64BIT ? gen_clrstr_long_64 : gen_clrstr_long_31;
...@@ -3047,7 +3050,7 @@ s390_expand_clrstr (dst, len) ...@@ -3047,7 +3050,7 @@ s390_expand_clrstr (dst, len)
rtx reg0 = gen_reg_rtx (double_mode); rtx reg0 = gen_reg_rtx (double_mode);
rtx reg1 = gen_reg_rtx (double_mode); rtx reg1 = gen_reg_rtx (double_mode);
emit_move_insn (gen_highpart (single_mode, reg0), emit_move_insn (gen_highpart (single_mode, reg0),
force_operand (XEXP (dst, 0), NULL_RTX)); force_operand (XEXP (dst, 0), NULL_RTX));
convert_move (gen_lowpart (single_mode, reg0), len, 1); convert_move (gen_lowpart (single_mode, reg0), len, 1);
...@@ -3078,12 +3081,12 @@ s390_expand_clrstr (dst, len) ...@@ -3078,12 +3081,12 @@ s390_expand_clrstr (dst, len)
blocks = gen_reg_rtx (mode); blocks = gen_reg_rtx (mode);
convert_move (count, len, 1); convert_move (count, len, 1);
emit_cmp_and_jump_insns (count, const0_rtx, emit_cmp_and_jump_insns (count, const0_rtx,
EQ, NULL_RTX, mode, 1, end_label); EQ, NULL_RTX, mode, 1, end_label);
emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
dst = change_address (dst, VOIDmode, dst_addr); dst = change_address (dst, VOIDmode, dst_addr);
temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0); temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
if (temp != count) if (temp != count)
emit_move_insn (count, temp); emit_move_insn (count, temp);
...@@ -3098,9 +3101,9 @@ s390_expand_clrstr (dst, len) ...@@ -3098,9 +3101,9 @@ s390_expand_clrstr (dst, len)
make_tree (type, const0_rtx))); make_tree (type, const0_rtx)));
emit_insn ((*gen_short) (dst, GEN_INT (255))); emit_insn ((*gen_short) (dst, GEN_INT (255)));
s390_load_address (dst_addr, s390_load_address (dst_addr,
gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0); temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
if (temp != blocks) if (temp != blocks)
emit_move_insn (blocks, temp); emit_move_insn (blocks, temp);
...@@ -3122,9 +3125,9 @@ s390_expand_cmpmem (target, op0, op1, len) ...@@ -3122,9 +3125,9 @@ s390_expand_cmpmem (target, op0, op1, len)
rtx op1; rtx op1;
rtx len; rtx len;
{ {
rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) = rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) =
TARGET_64BIT ? gen_cmpmem_short_64 : gen_cmpmem_short_31; TARGET_64BIT ? gen_cmpmem_short_64 : gen_cmpmem_short_31;
rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) = rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) =
TARGET_64BIT ? gen_cmpmem_long_64 : gen_cmpmem_long_31; TARGET_64BIT ? gen_cmpmem_long_64 : gen_cmpmem_long_31;
rtx (*gen_result) PARAMS ((rtx)) = rtx (*gen_result) PARAMS ((rtx)) =
GET_MODE (target) == DImode ? gen_cmpint_di : gen_cmpint_si; GET_MODE (target) == DImode ? gen_cmpint_di : gen_cmpint_si;
...@@ -3151,9 +3154,9 @@ s390_expand_cmpmem (target, op0, op1, len) ...@@ -3151,9 +3154,9 @@ s390_expand_cmpmem (target, op0, op1, len)
rtx reg0 = gen_reg_rtx (double_mode); rtx reg0 = gen_reg_rtx (double_mode);
rtx reg1 = gen_reg_rtx (double_mode); rtx reg1 = gen_reg_rtx (double_mode);
emit_move_insn (gen_highpart (single_mode, reg0), emit_move_insn (gen_highpart (single_mode, reg0),
force_operand (XEXP (op0, 0), NULL_RTX)); force_operand (XEXP (op0, 0), NULL_RTX));
emit_move_insn (gen_highpart (single_mode, reg1), emit_move_insn (gen_highpart (single_mode, reg1),
force_operand (XEXP (op1, 0), NULL_RTX)); force_operand (XEXP (op1, 0), NULL_RTX));
convert_move (gen_lowpart (single_mode, reg0), len, 1); convert_move (gen_lowpart (single_mode, reg0), len, 1);
...@@ -3187,14 +3190,14 @@ s390_expand_cmpmem (target, op0, op1, len) ...@@ -3187,14 +3190,14 @@ s390_expand_cmpmem (target, op0, op1, len)
blocks = gen_reg_rtx (mode); blocks = gen_reg_rtx (mode);
convert_move (count, len, 1); convert_move (count, len, 1);
emit_cmp_and_jump_insns (count, const0_rtx, emit_cmp_and_jump_insns (count, const0_rtx,
EQ, NULL_RTX, mode, 1, end_label); EQ, NULL_RTX, mode, 1, end_label);
emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX)); emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
op0 = change_address (op0, VOIDmode, addr0); op0 = change_address (op0, VOIDmode, addr0);
op1 = change_address (op1, VOIDmode, addr1); op1 = change_address (op1, VOIDmode, addr1);
temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0); temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
if (temp != count) if (temp != count)
emit_move_insn (count, temp); emit_move_insn (count, temp);
...@@ -3210,16 +3213,16 @@ s390_expand_cmpmem (target, op0, op1, len) ...@@ -3210,16 +3213,16 @@ s390_expand_cmpmem (target, op0, op1, len)
emit_insn ((*gen_short) (op0, op1, GEN_INT (255))); emit_insn ((*gen_short) (op0, op1, GEN_INT (255)));
temp = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCSmode, 33), const0_rtx); temp = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCSmode, 33), const0_rtx);
temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx); gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
temp = gen_rtx_SET (VOIDmode, pc_rtx, temp); temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
emit_jump_insn (temp); emit_jump_insn (temp);
s390_load_address (addr0, s390_load_address (addr0,
gen_rtx_PLUS (Pmode, addr0, GEN_INT (256))); gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
s390_load_address (addr1, s390_load_address (addr1,
gen_rtx_PLUS (Pmode, addr1, GEN_INT (256))); gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0); temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
if (temp != blocks) if (temp != blocks)
emit_move_insn (blocks, temp); emit_move_insn (blocks, temp);
...@@ -3293,7 +3296,7 @@ s390_delegitimize_address (orig_x) ...@@ -3293,7 +3296,7 @@ s390_delegitimize_address (orig_x)
return orig_x; return orig_x;
} }
return orig_x; return orig_x;
} }
/* Locate some local-dynamic symbol still in use by this function /* Locate some local-dynamic symbol still in use by this function
...@@ -3338,7 +3341,7 @@ get_some_local_dynamic_name_1 (px, data) ...@@ -3338,7 +3341,7 @@ get_some_local_dynamic_name_1 (px, data)
return 0; return 0;
} }
/* Output symbolic constant X in assembler syntax to /* Output symbolic constant X in assembler syntax to
stdio stream FILE. */ stdio stream FILE. */
void void
...@@ -3380,7 +3383,7 @@ s390_output_symbolic_const (file, x) ...@@ -3380,7 +3383,7 @@ s390_output_symbolic_const (file, x)
{ {
case UNSPEC_LTREL_OFFSET: case UNSPEC_LTREL_OFFSET:
s390_output_symbolic_const (file, XVECEXP (x, 0, 0)); s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
fprintf (file, "-"); fprintf (file, "-");
s390_output_symbolic_const (file, cfun->machine->literal_pool_label); s390_output_symbolic_const (file, cfun->machine->literal_pool_label);
break; break;
case UNSPEC_GOTENT: case UNSPEC_GOTENT:
...@@ -3439,7 +3442,7 @@ s390_output_symbolic_const (file, x) ...@@ -3439,7 +3442,7 @@ s390_output_symbolic_const (file, x)
} }
} }
/* Output address operand ADDR in assembler syntax to /* Output address operand ADDR in assembler syntax to
stdio stream FILE. */ stdio stream FILE. */
void void
...@@ -3453,7 +3456,7 @@ print_operand_address (file, addr) ...@@ -3453,7 +3456,7 @@ print_operand_address (file, addr)
|| (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base)) || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
|| (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))) || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
output_operand_lossage ("Cannot decompose address."); output_operand_lossage ("Cannot decompose address.");
if (ad.disp) if (ad.disp)
s390_output_symbolic_const (file, ad.disp); s390_output_symbolic_const (file, ad.disp);
else else
...@@ -3466,8 +3469,8 @@ print_operand_address (file, addr) ...@@ -3466,8 +3469,8 @@ print_operand_address (file, addr)
fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
} }
/* Output operand X in assembler syntax to stdio stream FILE. /* Output operand X in assembler syntax to stdio stream FILE.
CODE specified the format flag. The following format flags CODE specified the format flag. The following format flags
are recognized: are recognized:
'C': print opcode suffix for branch condition. 'C': print opcode suffix for branch condition.
...@@ -3638,7 +3641,7 @@ s390_assemble_integer (x, size, aligned_p) ...@@ -3638,7 +3641,7 @@ s390_assemble_integer (x, size, aligned_p)
return default_assemble_integer (x, size, aligned_p); return default_assemble_integer (x, size, aligned_p);
} }
/* Returns true if register REGNO is used for forming /* Returns true if register REGNO is used for forming
a memory address in expression X. */ a memory address in expression X. */
static int static int
...@@ -3649,14 +3652,14 @@ reg_used_in_mem_p (regno, x) ...@@ -3649,14 +3652,14 @@ reg_used_in_mem_p (regno, x)
enum rtx_code code = GET_CODE (x); enum rtx_code code = GET_CODE (x);
int i, j; int i, j;
const char *fmt; const char *fmt;
if (code == MEM) if (code == MEM)
{ {
if (refers_to_regno_p (regno, regno+1, if (refers_to_regno_p (regno, regno+1,
XEXP (x, 0), 0)) XEXP (x, 0), 0))
return 1; return 1;
} }
else if (code == SET else if (code == SET
&& GET_CODE (SET_DEST (x)) == PC) && GET_CODE (SET_DEST (x)) == PC)
{ {
if (refers_to_regno_p (regno, regno+1, if (refers_to_regno_p (regno, regno+1,
...@@ -3670,7 +3673,7 @@ reg_used_in_mem_p (regno, x) ...@@ -3670,7 +3673,7 @@ reg_used_in_mem_p (regno, x)
if (fmt[i] == 'e' if (fmt[i] == 'e'
&& reg_used_in_mem_p (regno, XEXP (x, i))) && reg_used_in_mem_p (regno, XEXP (x, i)))
return 1; return 1;
else if (fmt[i] == 'E') else if (fmt[i] == 'E')
for (j = 0; j < XVECLEN (x, i); j++) for (j = 0; j < XVECLEN (x, i); j++)
if (reg_used_in_mem_p (regno, XVECEXP (x, i, j))) if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
...@@ -3682,9 +3685,9 @@ reg_used_in_mem_p (regno, x) ...@@ -3682,9 +3685,9 @@ reg_used_in_mem_p (regno, x)
/* Returns true if expression DEP_RTX sets an address register /* Returns true if expression DEP_RTX sets an address register
used by instruction INSN to address memory. */ used by instruction INSN to address memory. */
static int static int
addr_generation_dependency_p (dep_rtx, insn) addr_generation_dependency_p (dep_rtx, insn)
rtx dep_rtx; rtx dep_rtx;
rtx insn; rtx insn;
{ {
rtx target, pat; rtx target, pat;
...@@ -3727,15 +3730,15 @@ addr_generation_dependency_p (dep_rtx, insn) ...@@ -3727,15 +3730,15 @@ addr_generation_dependency_p (dep_rtx, insn)
/* Return 1, if dep_insn sets register used in insn in the agen unit. */ /* Return 1, if dep_insn sets register used in insn in the agen unit. */
int int
s390_agen_dep_p(dep_insn, insn) s390_agen_dep_p(dep_insn, insn)
rtx dep_insn; rtx dep_insn;
rtx insn; rtx insn;
{ {
rtx dep_rtx = PATTERN (dep_insn); rtx dep_rtx = PATTERN (dep_insn);
int i; int i;
if (GET_CODE (dep_rtx) == SET if (GET_CODE (dep_rtx) == SET
&& addr_generation_dependency_p (dep_rtx, insn)) && addr_generation_dependency_p (dep_rtx, insn))
return 1; return 1;
else if (GET_CODE (dep_rtx) == PARALLEL) else if (GET_CODE (dep_rtx) == PARALLEL)
...@@ -3750,13 +3753,13 @@ s390_agen_dep_p(dep_insn, insn) ...@@ -3750,13 +3753,13 @@ s390_agen_dep_p(dep_insn, insn)
} }
/* Return the modified cost of the dependency of instruction INSN /* Return the modified cost of the dependency of instruction INSN
on instruction DEP_INSN through the link LINK. COST is the on instruction DEP_INSN through the link LINK. COST is the
default cost of that dependency. default cost of that dependency.
Data dependencies are all handled without delay. However, if a Data dependencies are all handled without delay. However, if a
register is modified and subsequently used as base or index register is modified and subsequently used as base or index
register of a memory reference, at least 4 cycles need to pass register of a memory reference, at least 4 cycles need to pass
between setting and using the register to avoid pipeline stalls. between setting and using the register to avoid pipeline stalls.
An exception is the LA instruction. An address generated by LA can An exception is the LA instruction. An address generated by LA can
be used by introducing only a one cycle stall on the pipeline. */ be used by introducing only a one cycle stall on the pipeline. */
...@@ -3784,7 +3787,7 @@ s390_adjust_cost (insn, link, dep_insn, cost) ...@@ -3784,7 +3787,7 @@ s390_adjust_cost (insn, link, dep_insn, cost)
/* DFA based scheduling checks address dependency in md file. */ /* DFA based scheduling checks address dependency in md file. */
if (s390_use_dfa_pipeline_interface ()) if (s390_use_dfa_pipeline_interface ())
{ {
/* Operand forward in case of lr, load and la. */ /* Operand forward in case of lr, load and la. */
if (s390_tune == PROCESSOR_2084_Z990 if (s390_tune == PROCESSOR_2084_Z990
&& cost == 1 && cost == 1
&& (s390_safe_attr_type (dep_insn) == TYPE_LA && (s390_safe_attr_type (dep_insn) == TYPE_LA
...@@ -3796,15 +3799,15 @@ s390_adjust_cost (insn, link, dep_insn, cost) ...@@ -3796,15 +3799,15 @@ s390_adjust_cost (insn, link, dep_insn, cost)
dep_rtx = PATTERN (dep_insn); dep_rtx = PATTERN (dep_insn);
if (GET_CODE (dep_rtx) == SET if (GET_CODE (dep_rtx) == SET
&& addr_generation_dependency_p (dep_rtx, insn)) && addr_generation_dependency_p (dep_rtx, insn))
cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
else if (GET_CODE (dep_rtx) == PARALLEL) else if (GET_CODE (dep_rtx) == PARALLEL)
{ {
for (i = 0; i < XVECLEN (dep_rtx, 0); i++) for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
{ {
if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
} }
} }
...@@ -3813,9 +3816,9 @@ s390_adjust_cost (insn, link, dep_insn, cost) ...@@ -3813,9 +3816,9 @@ s390_adjust_cost (insn, link, dep_insn, cost)
/* A C statement (sans semicolon) to update the integer scheduling priority /* A C statement (sans semicolon) to update the integer scheduling priority
INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier, INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
reduce the priority to execute INSN later. Do not define this macro if reduce the priority to execute INSN later. Do not define this macro if
you do not need to adjust the scheduling priorities of insns. you do not need to adjust the scheduling priorities of insns.
A STD instruction should be scheduled earlier, A STD instruction should be scheduled earlier,
in order to use the bypass. */ in order to use the bypass. */
static int static int
...@@ -3849,7 +3852,7 @@ s390_adjust_priority (insn, priority) ...@@ -3849,7 +3852,7 @@ s390_adjust_priority (insn, priority)
static int static int
s390_issue_rate () s390_issue_rate ()
{ {
if (s390_tune == PROCESSOR_2084_Z990) if (s390_tune == PROCESSOR_2084_Z990)
return 3; return 3;
return 1; return 1;
} }
...@@ -3888,14 +3891,14 @@ s390_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var) ...@@ -3888,14 +3891,14 @@ s390_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
} }
/* Split all branches that exceed the maximum distance. /* Split all branches that exceed the maximum distance.
Returns true if this created a new literal pool entry. Returns true if this created a new literal pool entry.
Code generated by this routine is allowed to use Code generated by this routine is allowed to use
TEMP_REG as temporary scratch register. If this is TEMP_REG as temporary scratch register. If this is
done, TEMP_USED is set to true. */ done, TEMP_USED is set to true. */
static int static int
s390_split_branches (temp_reg, temp_used) s390_split_branches (temp_reg, temp_used)
rtx temp_reg; rtx temp_reg;
bool *temp_used; bool *temp_used;
...@@ -3921,15 +3924,15 @@ s390_split_branches (temp_reg, temp_used) ...@@ -3921,15 +3924,15 @@ s390_split_branches (temp_reg, temp_used)
if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
continue; continue;
if (GET_CODE (SET_SRC (pat)) == LABEL_REF) if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
{ {
label = &SET_SRC (pat); label = &SET_SRC (pat);
} }
else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE) else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
{ {
if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF) if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
label = &XEXP (SET_SRC (pat), 1); label = &XEXP (SET_SRC (pat), 1);
else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF) else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
label = &XEXP (SET_SRC (pat), 2); label = &XEXP (SET_SRC (pat), 2);
else else
continue; continue;
...@@ -3961,14 +3964,14 @@ s390_split_branches (temp_reg, temp_used) ...@@ -3961,14 +3964,14 @@ s390_split_branches (temp_reg, temp_used)
else else
{ {
new_literal = 1; new_literal = 1;
target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label), target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
UNSPEC_LTREL_OFFSET); UNSPEC_LTREL_OFFSET);
target = gen_rtx_CONST (Pmode, target); target = gen_rtx_CONST (Pmode, target);
target = force_const_mem (Pmode, target); target = force_const_mem (Pmode, target);
tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn); tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
INSN_ADDRESSES_NEW (tmp, -1); INSN_ADDRESSES_NEW (tmp, -1);
target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (target, 0)), target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (target, 0)),
UNSPEC_LTREL_BASE); UNSPEC_LTREL_BASE);
target = gen_rtx_PLUS (Pmode, temp_reg, target); target = gen_rtx_PLUS (Pmode, temp_reg, target);
} }
...@@ -3981,12 +3984,12 @@ s390_split_branches (temp_reg, temp_used) ...@@ -3981,12 +3984,12 @@ s390_split_branches (temp_reg, temp_used)
} }
/* Find a literal pool symbol referenced in RTX X, and store /* Find a literal pool symbol referenced in RTX X, and store
it at REF. Will abort if X contains references to more than it at REF. Will abort if X contains references to more than
one such pool symbol; multiple references to the same symbol one such pool symbol; multiple references to the same symbol
are allowed, however. are allowed, however.
The rtx pointed to by REF must be initialized to NULL_RTX The rtx pointed to by REF must be initialized to NULL_RTX
by the caller before calling this routine. */ by the caller before calling this routine. */
static void static void
...@@ -4100,7 +4103,7 @@ replace_constant_pool_ref (x, ref, addr) ...@@ -4100,7 +4103,7 @@ replace_constant_pool_ref (x, ref, addr)
} }
} }
/* Check whether X contains an UNSPEC_LTREL_BASE. /* Check whether X contains an UNSPEC_LTREL_BASE.
Return its constant pool symbol if found, NULL_RTX otherwise. */ Return its constant pool symbol if found, NULL_RTX otherwise. */
static rtx static rtx
...@@ -4174,7 +4177,7 @@ replace_ltrel_base (x, base) ...@@ -4174,7 +4177,7 @@ replace_ltrel_base (x, base)
constant tables in the middle of large functions. */ constant tables in the middle of large functions. */
#define NR_C_MODES 7 #define NR_C_MODES 7
enum machine_mode constant_modes[NR_C_MODES] = enum machine_mode constant_modes[NR_C_MODES] =
{ {
TImode, TImode,
DFmode, DImode, DFmode, DImode,
...@@ -4331,7 +4334,7 @@ s390_add_constant (pool, val, mode) ...@@ -4331,7 +4334,7 @@ s390_add_constant (pool, val, mode)
/* Find constant VAL of mode MODE in the constant pool POOL. /* Find constant VAL of mode MODE in the constant pool POOL.
Return an RTX describing the distance from the start of Return an RTX describing the distance from the start of
the pool to the location of the new constant. */ the pool to the location of the new constant. */
static rtx static rtx
s390_find_constant (pool, val, mode) s390_find_constant (pool, val, mode)
struct constant_pool *pool; struct constant_pool *pool;
...@@ -4341,20 +4344,20 @@ s390_find_constant (pool, val, mode) ...@@ -4341,20 +4344,20 @@ s390_find_constant (pool, val, mode)
struct constant *c; struct constant *c;
rtx offset; rtx offset;
int i; int i;
for (i = 0; i < NR_C_MODES; i++) for (i = 0; i < NR_C_MODES; i++)
if (constant_modes[i] == mode) if (constant_modes[i] == mode)
break; break;
if (i == NR_C_MODES) if (i == NR_C_MODES)
abort (); abort ();
for (c = pool->constants[i]; c != NULL; c = c->next) for (c = pool->constants[i]; c != NULL; c = c->next)
if (rtx_equal_p (val, c->value)) if (rtx_equal_p (val, c->value))
break; break;
if (c == NULL) if (c == NULL)
abort (); abort ();
offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label), offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
gen_rtx_LABEL_REF (Pmode, pool->label)); gen_rtx_LABEL_REF (Pmode, pool->label));
offset = gen_rtx_CONST (Pmode, offset); offset = gen_rtx_CONST (Pmode, offset);
...@@ -4371,7 +4374,7 @@ s390_dump_pool (pool) ...@@ -4371,7 +4374,7 @@ s390_dump_pool (pool)
rtx insn; rtx insn;
int i; int i;
/* Pool start insn switches to proper section /* Pool start insn switches to proper section
and guarantees necessary alignment. */ and guarantees necessary alignment. */
if (TARGET_64BIT) if (TARGET_64BIT)
insn = emit_insn_after (gen_pool_start_64 (), pool->pool_insn); insn = emit_insn_after (gen_pool_start_64 (), pool->pool_insn);
...@@ -4405,7 +4408,7 @@ s390_dump_pool (pool) ...@@ -4405,7 +4408,7 @@ s390_dump_pool (pool)
INSN_ADDRESSES_NEW (insn, -1); INSN_ADDRESSES_NEW (insn, -1);
} }
/* Pool end insn switches back to previous section /* Pool end insn switches back to previous section
and guarantees necessary alignment. */ and guarantees necessary alignment. */
if (TARGET_64BIT) if (TARGET_64BIT)
insn = emit_insn_after (gen_pool_end_64 (), insn); insn = emit_insn_after (gen_pool_end_64 (), insn);
...@@ -4443,7 +4446,7 @@ s390_free_pool (pool) ...@@ -4443,7 +4446,7 @@ s390_free_pool (pool)
BITMAP_XFREE (pool->insns); BITMAP_XFREE (pool->insns);
free (pool); free (pool);
} }
/* Chunkify the literal pool if required. */ /* Chunkify the literal pool if required. */
...@@ -4451,7 +4454,7 @@ s390_free_pool (pool) ...@@ -4451,7 +4454,7 @@ s390_free_pool (pool)
#define S390_POOL_CHUNK_MIN 0xc00 #define S390_POOL_CHUNK_MIN 0xc00
#define S390_POOL_CHUNK_MAX 0xe00 #define S390_POOL_CHUNK_MAX 0xe00
static struct constant_pool * static struct constant_pool *
s390_chunkify_start (void) s390_chunkify_start (void)
{ {
rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER); rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER);
...@@ -4529,7 +4532,7 @@ s390_chunkify_start (void) ...@@ -4529,7 +4532,7 @@ s390_chunkify_start (void)
abort (); abort ();
} }
if (!curr_pool if (!curr_pool
|| INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn) || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
|| INSN_ADDRESSES (INSN_UID (insn)) == -1) || INSN_ADDRESSES (INSN_UID (insn)) == -1)
continue; continue;
...@@ -4579,7 +4582,7 @@ s390_chunkify_start (void) ...@@ -4579,7 +4582,7 @@ s390_chunkify_start (void)
if (get_attr_length (insn) == 0) if (get_attr_length (insn) == 0)
continue; continue;
/* Don't separate LTREL_BASE from the corresponding /* Don't separate LTREL_BASE from the corresponding
LTREL_OFFSET load. */ LTREL_OFFSET load. */
if (pending_ltrel) if (pending_ltrel)
continue; continue;
...@@ -4608,7 +4611,7 @@ s390_chunkify_start (void) ...@@ -4608,7 +4611,7 @@ s390_chunkify_start (void)
abort (); abort ();
/* Find all labels that are branched into /* Find all labels that are branched into
from an insn belonging to a different chunk. */ from an insn belonging to a different chunk. */
far_labels = BITMAP_XMALLOC (); far_labels = BITMAP_XMALLOC ();
...@@ -4622,11 +4625,11 @@ s390_chunkify_start (void) ...@@ -4622,11 +4625,11 @@ s390_chunkify_start (void)
Don't do that, however, if it is the label before Don't do that, however, if it is the label before
a jump table. */ a jump table. */
if (GET_CODE (insn) == CODE_LABEL if (GET_CODE (insn) == CODE_LABEL
&& (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn))) && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
{ {
rtx vec_insn = next_real_insn (insn); rtx vec_insn = next_real_insn (insn);
rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
PATTERN (vec_insn) : NULL_RTX; PATTERN (vec_insn) : NULL_RTX;
if (!vec_pat if (!vec_pat
|| !(GET_CODE (vec_pat) == ADDR_VEC || !(GET_CODE (vec_pat) == ADDR_VEC
...@@ -4636,22 +4639,22 @@ s390_chunkify_start (void) ...@@ -4636,22 +4639,22 @@ s390_chunkify_start (void)
/* If we have a direct jump (conditional or unconditional) /* If we have a direct jump (conditional or unconditional)
or a casesi jump, check all potential targets. */ or a casesi jump, check all potential targets. */
else if (GET_CODE (insn) == JUMP_INSN) else if (GET_CODE (insn) == JUMP_INSN)
{ {
rtx pat = PATTERN (insn); rtx pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2) if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
pat = XVECEXP (pat, 0, 0); pat = XVECEXP (pat, 0, 0);
if (GET_CODE (pat) == SET) if (GET_CODE (pat) == SET)
{ {
rtx label = JUMP_LABEL (insn); rtx label = JUMP_LABEL (insn);
if (label) if (label)
{ {
if (s390_find_pool (pool_list, label) if (s390_find_pool (pool_list, label)
!= s390_find_pool (pool_list, insn)) != s390_find_pool (pool_list, insn))
bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
} }
} }
else if (GET_CODE (pat) == PARALLEL else if (GET_CODE (pat) == PARALLEL
&& XVECLEN (pat, 0) == 2 && XVECLEN (pat, 0) == 2
&& GET_CODE (XVECEXP (pat, 0, 0)) == SET && GET_CODE (XVECEXP (pat, 0, 0)) == SET
...@@ -4661,7 +4664,7 @@ s390_chunkify_start (void) ...@@ -4661,7 +4664,7 @@ s390_chunkify_start (void)
/* Find the jump table used by this casesi jump. */ /* Find the jump table used by this casesi jump. */
rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0); rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
rtx vec_insn = next_real_insn (vec_label); rtx vec_insn = next_real_insn (vec_label);
rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
PATTERN (vec_insn) : NULL_RTX; PATTERN (vec_insn) : NULL_RTX;
if (vec_pat if (vec_pat
&& (GET_CODE (vec_pat) == ADDR_VEC && (GET_CODE (vec_pat) == ADDR_VEC
...@@ -4673,7 +4676,7 @@ s390_chunkify_start (void) ...@@ -4673,7 +4676,7 @@ s390_chunkify_start (void)
{ {
rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0); rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
if (s390_find_pool (pool_list, label) if (s390_find_pool (pool_list, label)
!= s390_find_pool (pool_list, insn)) != s390_find_pool (pool_list, insn))
bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
} }
...@@ -4694,7 +4697,7 @@ s390_chunkify_start (void) ...@@ -4694,7 +4697,7 @@ s390_chunkify_start (void)
/* Insert base register reload insns at every far label. */ /* Insert base register reload insns at every far label. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
if (GET_CODE (insn) == CODE_LABEL if (GET_CODE (insn) == CODE_LABEL
&& bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn))) && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
{ {
struct constant_pool *pool = s390_find_pool (pool_list, insn); struct constant_pool *pool = s390_find_pool (pool_list, insn);
...@@ -4718,9 +4721,9 @@ s390_chunkify_start (void) ...@@ -4718,9 +4721,9 @@ s390_chunkify_start (void)
} }
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start. /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
After we have decided to use this list, finish implementing After we have decided to use this list, finish implementing
all changes to the current function as required. */ all changes to the current function as required. */
static void static void
s390_chunkify_finish (pool_list) s390_chunkify_finish (pool_list)
struct constant_pool *pool_list; struct constant_pool *pool_list;
...@@ -4728,11 +4731,11 @@ s390_chunkify_finish (pool_list) ...@@ -4728,11 +4731,11 @@ s390_chunkify_finish (pool_list)
rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER); rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER);
struct constant_pool *curr_pool = NULL; struct constant_pool *curr_pool = NULL;
rtx insn; rtx insn;
/* Replace all literal pool references. */ /* Replace all literal pool references. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{ {
if (INSN_P (insn)) if (INSN_P (insn))
replace_ltrel_base (&PATTERN (insn), base_reg); replace_ltrel_base (&PATTERN (insn), base_reg);
...@@ -4757,10 +4760,10 @@ s390_chunkify_finish (pool_list) ...@@ -4757,10 +4760,10 @@ s390_chunkify_finish (pool_list)
} }
/* Dump out all literal pools. */ /* Dump out all literal pools. */
for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
s390_dump_pool (curr_pool); s390_dump_pool (curr_pool);
/* Free pool list. */ /* Free pool list. */
while (pool_list) while (pool_list)
...@@ -4774,7 +4777,7 @@ s390_chunkify_finish (pool_list) ...@@ -4774,7 +4777,7 @@ s390_chunkify_finish (pool_list)
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start. /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
We have decided we cannot use this list, so revert all changes We have decided we cannot use this list, so revert all changes
to the current function that were done by s390_chunkify_start. */ to the current function that were done by s390_chunkify_start. */
static void static void
s390_chunkify_cancel (pool_list) s390_chunkify_cancel (pool_list)
struct constant_pool *pool_list; struct constant_pool *pool_list;
...@@ -4840,25 +4843,25 @@ int s390_pool_count = -1; ...@@ -4840,25 +4843,25 @@ int s390_pool_count = -1;
/* Number of elements of current constant pool. */ /* Number of elements of current constant pool. */
int s390_nr_constants; int s390_nr_constants;
/* Output main constant pool to stdio stream FILE. */ /* Output main constant pool to stdio stream FILE. */
void void
s390_output_constant_pool (start_label, end_label) s390_output_constant_pool (start_label, end_label)
rtx start_label; rtx start_label;
rtx end_label; rtx end_label;
{ {
if (TARGET_64BIT) if (TARGET_64BIT)
{ {
readonly_data_section (); readonly_data_section ();
ASM_OUTPUT_ALIGN (asm_out_file, 3); ASM_OUTPUT_ALIGN (asm_out_file, 3);
(*targetm.asm_out.internal_label) (asm_out_file, "L", (*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (start_label)); CODE_LABEL_NUMBER (start_label));
} }
else else
{ {
(*targetm.asm_out.internal_label) (asm_out_file, "L", (*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (start_label)); CODE_LABEL_NUMBER (start_label));
ASM_OUTPUT_ALIGN (asm_out_file, 2); ASM_OUTPUT_ALIGN (asm_out_file, 2);
} }
s390_pool_count = 0; s390_pool_count = 0;
...@@ -4869,15 +4872,15 @@ s390_output_constant_pool (start_label, end_label) ...@@ -4869,15 +4872,15 @@ s390_output_constant_pool (start_label, end_label)
else else
{ {
ASM_OUTPUT_ALIGN (asm_out_file, 1); ASM_OUTPUT_ALIGN (asm_out_file, 1);
(*targetm.asm_out.internal_label) (asm_out_file, "L", (*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (end_label)); CODE_LABEL_NUMBER (end_label));
} }
} }
/* Rework the prolog/epilog to avoid saving/restoring /* Rework the prolog/epilog to avoid saving/restoring
registers unnecessarily. If TEMP_REGNO is nonnegative, registers unnecessarily. If TEMP_REGNO is nonnegative,
it specifies the number of a caller-saved register used it specifies the number of a caller-saved register used
as temporary scratch register by code emitted during as temporary scratch register by code emitted during
machine dependent reorg. */ machine dependent reorg. */
static void static void
...@@ -4894,12 +4897,12 @@ s390_optimize_prolog (temp_regno) ...@@ -4894,12 +4897,12 @@ s390_optimize_prolog (temp_regno)
regs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0; regs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0;
/* If there is (possibly) any pool entry, we need to /* If there is (possibly) any pool entry, we need to
load the base register. load the base register.
??? FIXME: this should be more precise. */ ??? FIXME: this should be more precise. */
if (get_pool_size ()) if (get_pool_size ())
regs_ever_live[BASE_REGISTER] = 1; regs_ever_live[BASE_REGISTER] = 1;
/* In non-leaf functions, the prolog/epilog code relies /* In non-leaf functions, the prolog/epilog code relies
on RETURN_REGNUM being saved in any case. */ on RETURN_REGNUM being saved in any case. */
if (!current_function_is_leaf) if (!current_function_is_leaf)
regs_ever_live[RETURN_REGNUM] = 1; regs_ever_live[RETURN_REGNUM] = 1;
...@@ -4910,22 +4913,22 @@ s390_optimize_prolog (temp_regno) ...@@ -4910,22 +4913,22 @@ s390_optimize_prolog (temp_regno)
/* Find first and last gpr to be saved. */ /* Find first and last gpr to be saved. */
for (i = 6; i < 16; i++) for (i = 6; i < 16; i++)
if (regs_ever_live[i]) if (regs_ever_live[i])
if (!global_regs[i] if (!global_regs[i]
|| i == STACK_POINTER_REGNUM || i == STACK_POINTER_REGNUM
|| i == RETURN_REGNUM || i == RETURN_REGNUM
|| i == BASE_REGISTER || i == BASE_REGISTER
|| (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM)) || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
break; break;
for (j = 15; j > i; j--) for (j = 15; j > i; j--)
if (regs_ever_live[j]) if (regs_ever_live[j])
if (!global_regs[j] if (!global_regs[j]
|| j == STACK_POINTER_REGNUM || j == STACK_POINTER_REGNUM
|| j == RETURN_REGNUM || j == RETURN_REGNUM
|| j == BASE_REGISTER || j == BASE_REGISTER
|| (flag_pic && j == (int)PIC_OFFSET_TABLE_REGNUM)) || (flag_pic && j == (int)PIC_OFFSET_TABLE_REGNUM))
break; break;
...@@ -5098,26 +5101,26 @@ s390_reorg () ...@@ -5098,26 +5101,26 @@ s390_reorg ()
/* There are two problematic situations we need to correct: /* There are two problematic situations we need to correct:
- the literal pool might be > 4096 bytes in size, so that - the literal pool might be > 4096 bytes in size, so that
some of its elements cannot be directly accessed some of its elements cannot be directly accessed
- a branch target might be > 64K away from the branch, so that - a branch target might be > 64K away from the branch, so that
it is not possible to use a PC-relative instruction. it is not possible to use a PC-relative instruction.
To fix those, we split the single literal pool into multiple To fix those, we split the single literal pool into multiple
pool chunks, reloading the pool base register at various pool chunks, reloading the pool base register at various
points throughout the function to ensure it always points to points throughout the function to ensure it always points to
the pool chunk the following code expects, and / or replace the pool chunk the following code expects, and / or replace
PC-relative branches by absolute branches. PC-relative branches by absolute branches.
However, the two problems are interdependent: splitting the However, the two problems are interdependent: splitting the
literal pool can move a branch further away from its target, literal pool can move a branch further away from its target,
causing the 64K limit to overflow, and on the other hand, causing the 64K limit to overflow, and on the other hand,
replacing a PC-relative branch by an absolute branch means replacing a PC-relative branch by an absolute branch means
we need to put the branch target address into the literal we need to put the branch target address into the literal
pool, possibly causing it to overflow. pool, possibly causing it to overflow.
So, we loop trying to fix up both problems until we manage So, we loop trying to fix up both problems until we manage
to satisfy both conditions at the same time. Note that the to satisfy both conditions at the same time. Note that the
loop is guaranteed to terminate as every pass of the loop loop is guaranteed to terminate as every pass of the loop
...@@ -5125,11 +5128,11 @@ s390_reorg () ...@@ -5125,11 +5128,11 @@ s390_reorg ()
in the function. (This is not completely true as there in the function. (This is not completely true as there
might be branch-over-pool insns introduced by chunkify_start. might be branch-over-pool insns introduced by chunkify_start.
Those never need to be split however.) */ Those never need to be split however.) */
for (;;) for (;;)
{ {
struct constant_pool *pool_list; struct constant_pool *pool_list;
/* Try to chunkify the literal pool. */ /* Try to chunkify the literal pool. */
pool_list = s390_chunkify_start (); pool_list = s390_chunkify_start ();
...@@ -5140,7 +5143,7 @@ s390_reorg () ...@@ -5140,7 +5143,7 @@ s390_reorg ()
{ {
if (pool_list) if (pool_list)
s390_chunkify_cancel (pool_list); s390_chunkify_cancel (pool_list);
continue; continue;
} }
...@@ -5158,15 +5161,15 @@ s390_reorg () ...@@ -5158,15 +5161,15 @@ s390_reorg ()
continue; continue;
} }
/* If we made it up to here, both conditions are satisfied. /* If we made it up to here, both conditions are satisfied.
Finish up pool chunkification if required. */ Finish up pool chunkification if required. */
if (pool_list) if (pool_list)
s390_chunkify_finish (pool_list); s390_chunkify_finish (pool_list);
break; break;
} }
s390_optimize_prolog (temp_used? RETURN_REGNUM : -1); s390_optimize_prolog (temp_used? RETURN_REGNUM : -1);
} }
...@@ -5194,7 +5197,7 @@ s390_return_addr_rtx (count, frame) ...@@ -5194,7 +5197,7 @@ s390_return_addr_rtx (count, frame)
addr = plus_constant (frame, RETURN_REGNUM * UNITS_PER_WORD); addr = plus_constant (frame, RETURN_REGNUM * UNITS_PER_WORD);
addr = memory_address (Pmode, addr); addr = memory_address (Pmode, addr);
return gen_rtx_MEM (Pmode, addr); return gen_rtx_MEM (Pmode, addr);
} }
/* Find first call clobbered register unsused in a function. /* Find first call clobbered register unsused in a function.
This could be used as base register in a leaf function This could be used as base register in a leaf function
...@@ -5225,7 +5228,7 @@ s390_frame_info () ...@@ -5225,7 +5228,7 @@ s390_frame_info ()
/* fprs 8 - 15 are caller saved for 64 Bit ABI. */ /* fprs 8 - 15 are caller saved for 64 Bit ABI. */
cfun->machine->save_fprs_p = 0; cfun->machine->save_fprs_p = 0;
if (TARGET_64BIT) if (TARGET_64BIT)
for (i = 24; i < 32; i++) for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i]) if (regs_ever_live[i] && !global_regs[i])
{ {
cfun->machine->save_fprs_p = 1; cfun->machine->save_fprs_p = 1;
...@@ -5235,10 +5238,10 @@ s390_frame_info () ...@@ -5235,10 +5238,10 @@ s390_frame_info ()
cfun->machine->frame_size = fsize + cfun->machine->save_fprs_p * 64; cfun->machine->frame_size = fsize + cfun->machine->save_fprs_p * 64;
/* Does function need to setup frame and save area. */ /* Does function need to setup frame and save area. */
if (! current_function_is_leaf if (! current_function_is_leaf
|| cfun->machine->frame_size > 0 || cfun->machine->frame_size > 0
|| current_function_calls_alloca || current_function_calls_alloca
|| current_function_stdarg) || current_function_stdarg)
cfun->machine->frame_size += STARTING_FRAME_OFFSET; cfun->machine->frame_size += STARTING_FRAME_OFFSET;
...@@ -5258,7 +5261,7 @@ s390_frame_info () ...@@ -5258,7 +5261,7 @@ s390_frame_info ()
gprs_ever_live[BASE_REGISTER] = 1; gprs_ever_live[BASE_REGISTER] = 1;
gprs_ever_live[RETURN_REGNUM] = 1; gprs_ever_live[RETURN_REGNUM] = 1;
gprs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0; gprs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0;
for (i = 6; i < 16; i++) for (i = 6; i < 16; i++)
if (gprs_ever_live[i]) if (gprs_ever_live[i])
break; break;
...@@ -5278,10 +5281,10 @@ s390_frame_info () ...@@ -5278,10 +5281,10 @@ s390_frame_info ()
cfun->machine->first_save_gpr = 2; cfun->machine->first_save_gpr = 2;
} }
/* Return offset between argument pointer and frame pointer /* Return offset between argument pointer and frame pointer
initially after prologue. */ initially after prologue. */
int int
s390_arg_frame_offset () s390_arg_frame_offset ()
{ {
HOST_WIDE_INT fsize = get_frame_size (); HOST_WIDE_INT fsize = get_frame_size ();
...@@ -5290,7 +5293,7 @@ s390_arg_frame_offset () ...@@ -5290,7 +5293,7 @@ s390_arg_frame_offset ()
/* fprs 8 - 15 are caller saved for 64 Bit ABI. */ /* fprs 8 - 15 are caller saved for 64 Bit ABI. */
save_fprs_p = 0; save_fprs_p = 0;
if (TARGET_64BIT) if (TARGET_64BIT)
for (i = 24; i < 32; i++) for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i]) if (regs_ever_live[i] && !global_regs[i])
{ {
save_fprs_p = 1; save_fprs_p = 1;
...@@ -5300,23 +5303,23 @@ s390_arg_frame_offset () ...@@ -5300,23 +5303,23 @@ s390_arg_frame_offset ()
fsize = fsize + save_fprs_p * 64; fsize = fsize + save_fprs_p * 64;
/* Does function need to setup frame and save area. */ /* Does function need to setup frame and save area. */
if (! current_function_is_leaf if (! current_function_is_leaf
|| fsize > 0 || fsize > 0
|| current_function_calls_alloca || current_function_calls_alloca
|| current_function_stdarg) || current_function_stdarg)
fsize += STARTING_FRAME_OFFSET; fsize += STARTING_FRAME_OFFSET;
return fsize + STACK_POINTER_OFFSET; return fsize + STACK_POINTER_OFFSET;
} }
/* Emit insn to save fpr REGNUM at offset OFFSET relative /* Emit insn to save fpr REGNUM at offset OFFSET relative
to register BASE. Return generated insn. */ to register BASE. Return generated insn. */
static rtx static rtx
save_fpr (base, offset, regnum) save_fpr (base, offset, regnum)
rtx base; rtx base;
int offset; int offset;
int regnum; int regnum;
{ {
rtx addr; rtx addr;
addr = gen_rtx_MEM (DFmode, plus_constant (base, offset)); addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
...@@ -5326,7 +5329,7 @@ save_fpr (base, offset, regnum) ...@@ -5326,7 +5329,7 @@ save_fpr (base, offset, regnum)
} }
/* Emit insn to restore fpr REGNUM from offset OFFSET relative /* Emit insn to restore fpr REGNUM from offset OFFSET relative
to register BASE. Return generated insn. */ to register BASE. Return generated insn. */
static rtx static rtx
restore_fpr (base, offset, regnum) restore_fpr (base, offset, regnum)
...@@ -5342,7 +5345,7 @@ restore_fpr (base, offset, regnum) ...@@ -5342,7 +5345,7 @@ restore_fpr (base, offset, regnum)
} }
/* Generate insn to save registers FIRST to LAST into /* Generate insn to save registers FIRST to LAST into
the register save area located at offset OFFSET the register save area located at offset OFFSET
relative to register BASE. */ relative to register BASE. */
static rtx static rtx
...@@ -5381,7 +5384,7 @@ save_gprs (base, offset, first, last) ...@@ -5381,7 +5384,7 @@ save_gprs (base, offset, first, last)
inside the store-multiple pattern. inside the store-multiple pattern.
However, we must not emit DWARF records for registers 2..5 However, we must not emit DWARF records for registers 2..5
if they are stored for use by variable arguments ... if they are stored for use by variable arguments ...
??? Unfortunately, it is not enough to simply not the the ??? Unfortunately, it is not enough to simply not the the
FRAME_RELATED flags for those SETs, because the first SET FRAME_RELATED flags for those SETs, because the first SET
...@@ -5402,13 +5405,13 @@ save_gprs (base, offset, first, last) ...@@ -5402,13 +5405,13 @@ save_gprs (base, offset, first, last)
else if (last >= 6) else if (last >= 6)
{ {
addr = plus_constant (base, offset + 6 * UNITS_PER_WORD); addr = plus_constant (base, offset + 6 * UNITS_PER_WORD);
note = gen_store_multiple (gen_rtx_MEM (Pmode, addr), note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
gen_rtx_REG (Pmode, 6), gen_rtx_REG (Pmode, 6),
GEN_INT (last - 6 + 1)); GEN_INT (last - 6 + 1));
note = PATTERN (note); note = PATTERN (note);
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
note, REG_NOTES (insn)); note, REG_NOTES (insn));
for (i = 0; i < XVECLEN (note, 0); i++) for (i = 0; i < XVECLEN (note, 0); i++)
...@@ -5422,7 +5425,7 @@ save_gprs (base, offset, first, last) ...@@ -5422,7 +5425,7 @@ save_gprs (base, offset, first, last)
} }
/* Generate insn to restore registers FIRST to LAST from /* Generate insn to restore registers FIRST to LAST from
the register save area located at offset OFFSET the register save area located at offset OFFSET
relative to register BASE. */ relative to register BASE. */
static rtx static rtx
...@@ -5480,7 +5483,7 @@ s390_load_got (maybe_dead) ...@@ -5480,7 +5483,7 @@ s390_load_got (maybe_dead)
{ {
rtx offset, insn; rtx offset, insn;
offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol), offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
UNSPEC_LTREL_OFFSET); UNSPEC_LTREL_OFFSET);
offset = gen_rtx_CONST (Pmode, offset); offset = gen_rtx_CONST (Pmode, offset);
offset = force_const_mem (Pmode, offset); offset = force_const_mem (Pmode, offset);
...@@ -5490,7 +5493,7 @@ s390_load_got (maybe_dead) ...@@ -5490,7 +5493,7 @@ s390_load_got (maybe_dead)
REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX, REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
REG_NOTES (insn)); REG_NOTES (insn));
offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)), offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
UNSPEC_LTREL_BASE); UNSPEC_LTREL_BASE);
offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset); offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
...@@ -5515,18 +5518,20 @@ s390_emit_prologue () ...@@ -5515,18 +5518,20 @@ s390_emit_prologue ()
s390_frame_info (); s390_frame_info ();
/* Choose best register to use for temp use within prologue. */ /* Choose best register to use for temp use within prologue.
See below for why TPF must use the register 1. */
if (!current_function_is_leaf if (!current_function_is_leaf
&& !has_hard_reg_initial_val (Pmode, RETURN_REGNUM) && !has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
&& get_pool_size () < S390_POOL_CHUNK_MAX / 2) && get_pool_size () < S390_POOL_CHUNK_MAX / 2
&& !TARGET_TPF)
temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
else else
temp_reg = gen_rtx_REG (Pmode, 1); temp_reg = gen_rtx_REG (Pmode, 1);
/* Save call saved gprs. */ /* Save call saved gprs. */
insn = save_gprs (stack_pointer_rtx, 0, insn = save_gprs (stack_pointer_rtx, 0,
cfun->machine->first_save_gpr, cfun->machine->last_save_gpr); cfun->machine->first_save_gpr, cfun->machine->last_save_gpr);
emit_insn (insn); emit_insn (insn);
...@@ -5535,29 +5540,29 @@ s390_emit_prologue () ...@@ -5535,29 +5540,29 @@ s390_emit_prologue ()
pool_start_label = gen_label_rtx(); pool_start_label = gen_label_rtx();
pool_end_label = gen_label_rtx(); pool_end_label = gen_label_rtx();
cfun->machine->literal_pool_label = pool_start_label; cfun->machine->literal_pool_label = pool_start_label;
if (TARGET_64BIT) if (TARGET_64BIT)
insn = emit_insn (gen_literal_pool_64 (gen_rtx_REG (Pmode, BASE_REGISTER), insn = emit_insn (gen_literal_pool_64 (gen_rtx_REG (Pmode, BASE_REGISTER),
pool_start_label, pool_end_label)); pool_start_label, pool_end_label));
else else
insn = emit_insn (gen_literal_pool_31 (gen_rtx_REG (Pmode, BASE_REGISTER), insn = emit_insn (gen_literal_pool_31 (gen_rtx_REG (Pmode, BASE_REGISTER),
pool_start_label, pool_end_label)); pool_start_label, pool_end_label));
/* Save fprs for variable args. */ /* Save fprs for variable args. */
if (current_function_stdarg) if (current_function_stdarg)
{ {
/* Save fpr 0 and 2. */ /* Save fpr 0 and 2. */
save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 32, 16);
save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 24, 17);
save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 32, 16);
save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 24, 17);
if (TARGET_64BIT) if (TARGET_64BIT)
{ {
/* Save fpr 4 and 6. */ /* Save fpr 4 and 6. */
save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 16, 18); save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 16, 18);
save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19); save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
} }
} }
...@@ -5573,7 +5578,7 @@ s390_emit_prologue () ...@@ -5573,7 +5578,7 @@ s390_emit_prologue ()
} }
if (regs_ever_live[19] && !global_regs[19]) if (regs_ever_live[19] && !global_regs[19])
{ {
insn = save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19); insn = save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
RTX_FRAME_RELATED_P (insn) = 1; RTX_FRAME_RELATED_P (insn) = 1;
} }
} }
...@@ -5585,18 +5590,18 @@ s390_emit_prologue () ...@@ -5585,18 +5590,18 @@ s390_emit_prologue ()
rtx frame_off = GEN_INT (-cfun->machine->frame_size); rtx frame_off = GEN_INT (-cfun->machine->frame_size);
/* Save incoming stack pointer into temp reg. */ /* Save incoming stack pointer into temp reg. */
if (TARGET_BACKCHAIN || cfun->machine->save_fprs_p) if (TARGET_BACKCHAIN || cfun->machine->save_fprs_p)
{ {
insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx)); insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
} }
/* Subtract frame size from stack pointer. */ /* Subtract frame size from stack pointer. */
if (DISP_IN_RANGE (INTVAL (frame_off))) if (DISP_IN_RANGE (INTVAL (frame_off)))
{ {
insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx, insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
gen_rtx_PLUS (Pmode, stack_pointer_rtx, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
frame_off)); frame_off));
insn = emit_insn (insn); insn = emit_insn (insn);
} }
...@@ -5609,7 +5614,7 @@ s390_emit_prologue () ...@@ -5609,7 +5614,7 @@ s390_emit_prologue ()
} }
RTX_FRAME_RELATED_P (insn) = 1; RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
gen_rtx_SET (VOIDmode, stack_pointer_rtx, gen_rtx_SET (VOIDmode, stack_pointer_rtx,
gen_rtx_PLUS (Pmode, stack_pointer_rtx, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
...@@ -5617,7 +5622,7 @@ s390_emit_prologue () ...@@ -5617,7 +5622,7 @@ s390_emit_prologue ()
REG_NOTES (insn)); REG_NOTES (insn));
/* Set backchain. */ /* Set backchain. */
if (TARGET_BACKCHAIN) if (TARGET_BACKCHAIN)
{ {
addr = gen_rtx_MEM (Pmode, stack_pointer_rtx); addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
...@@ -5637,7 +5642,7 @@ s390_emit_prologue () ...@@ -5637,7 +5642,7 @@ s390_emit_prologue ()
} }
/* Save fprs 8 - 15 (64 bit ABI). */ /* Save fprs 8 - 15 (64 bit ABI). */
if (cfun->machine->save_fprs_p) if (cfun->machine->save_fprs_p)
{ {
insn = emit_insn (gen_add2_insn (temp_reg, GEN_INT(-64))); insn = emit_insn (gen_add2_insn (temp_reg, GEN_INT(-64)));
...@@ -5645,22 +5650,22 @@ s390_emit_prologue () ...@@ -5645,22 +5650,22 @@ s390_emit_prologue ()
for (i = 24; i < 32; i++) for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i]) if (regs_ever_live[i] && !global_regs[i])
{ {
rtx addr = plus_constant (stack_pointer_rtx, rtx addr = plus_constant (stack_pointer_rtx,
cfun->machine->frame_size - 64 + (i-24)*8); cfun->machine->frame_size - 64 + (i-24)*8);
insn = save_fpr (temp_reg, (i-24)*8, i); insn = save_fpr (temp_reg, (i-24)*8, i);
RTX_FRAME_RELATED_P (insn) = 1; RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
gen_rtx_SET (VOIDmode, gen_rtx_SET (VOIDmode,
gen_rtx_MEM (DFmode, addr), gen_rtx_MEM (DFmode, addr),
gen_rtx_REG (DFmode, i)), gen_rtx_REG (DFmode, i)),
REG_NOTES (insn)); REG_NOTES (insn));
} }
} }
/* Set frame pointer, if needed. */ /* Set frame pointer, if needed. */
if (frame_pointer_needed) if (frame_pointer_needed)
{ {
insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
...@@ -5668,9 +5673,31 @@ s390_emit_prologue () ...@@ -5668,9 +5673,31 @@ s390_emit_prologue ()
} }
/* Set up got pointer, if needed. */ /* Set up got pointer, if needed. */
if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
s390_load_got (true); s390_load_got(true);
if (TARGET_TPF)
{
/* Generate a BAS instruction to serve as a function
entry intercept to facilitate the use of tracing
algorithms located at the branch target.
This must use register 1. */
rtx addr;
rtx unkn;
rtx link;
addr = GEN_INT (0xfe0);
unkn = CONST0_RTX (SImode);
link = gen_rtx_REG (Pmode, 1);
emit_call_insn (gen_call_exp (gen_rtx_MEM (QImode, addr), unkn, link));
/* Emit a blockage here so that all code
lies between the profiling mechanisms. */
emit_insn (gen_blockage ());
}
} }
/* Expand the epilogue into a bunch of separate insns. */ /* Expand the epilogue into a bunch of separate insns. */
...@@ -5682,9 +5709,33 @@ s390_emit_epilogue () ...@@ -5682,9 +5709,33 @@ s390_emit_epilogue ()
int area_bottom, area_top, offset = 0; int area_bottom, area_top, offset = 0;
rtvec p; rtvec p;
if (TARGET_TPF)
{
/* Generate a BAS instruction to serve as a function
entry intercept to facilitate the use of tracing
algorithms located at the branch target.
This must use register 1. */
rtx addr;
rtx unkn;
rtx link;
addr = GEN_INT (0xfe6);
unkn = CONST0_RTX (SImode);
link = gen_rtx_REG (Pmode, 1);
/* Emit a blockage here so that all code
lies between the profiling mechanisms. */
emit_insn (gen_blockage ());
emit_call_insn (gen_call_exp (gen_rtx_MEM (QImode, addr), unkn, link));
}
/* Check whether to use frame or stack pointer for restore. */ /* Check whether to use frame or stack pointer for restore. */
frame_pointer = frame_pointer_needed ? frame_pointer = frame_pointer_needed ?
hard_frame_pointer_rtx : stack_pointer_rtx; hard_frame_pointer_rtx : stack_pointer_rtx;
/* Compute which parts of the save area we need to access. */ /* Compute which parts of the save area we need to access. */
...@@ -5728,7 +5779,7 @@ s390_emit_epilogue () ...@@ -5728,7 +5779,7 @@ s390_emit_epilogue ()
} }
} }
/* Check whether we can access the register save area. /* Check whether we can access the register save area.
If not, increment the frame pointer as required. */ If not, increment the frame pointer as required. */
if (area_top <= area_bottom) if (area_top <= area_bottom)
...@@ -5745,12 +5796,12 @@ s390_emit_epilogue () ...@@ -5745,12 +5796,12 @@ s390_emit_epilogue ()
{ {
rtx insn, frame_off; rtx insn, frame_off;
offset = area_bottom < 0 ? -area_bottom : 0; offset = area_bottom < 0 ? -area_bottom : 0;
frame_off = GEN_INT (cfun->machine->frame_size - offset); frame_off = GEN_INT (cfun->machine->frame_size - offset);
if (DISP_IN_RANGE (INTVAL (frame_off))) if (DISP_IN_RANGE (INTVAL (frame_off)))
{ {
insn = gen_rtx_SET (VOIDmode, frame_pointer, insn = gen_rtx_SET (VOIDmode, frame_pointer,
gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
insn = emit_insn (insn); insn = emit_insn (insn);
} }
...@@ -5772,7 +5823,7 @@ s390_emit_epilogue () ...@@ -5772,7 +5823,7 @@ s390_emit_epilogue ()
if (cfun->machine->save_fprs_p) if (cfun->machine->save_fprs_p)
for (i = 24; i < 32; i++) for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i]) if (regs_ever_live[i] && !global_regs[i])
restore_fpr (frame_pointer, restore_fpr (frame_pointer,
offset - 64 + (i-24) * 8, i); offset - 64 + (i-24) * 8, i);
} }
else else
...@@ -5785,7 +5836,7 @@ s390_emit_epilogue () ...@@ -5785,7 +5836,7 @@ s390_emit_epilogue ()
/* Return register. */ /* Return register. */
return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
/* Restore call saved gprs. */ /* Restore call saved gprs. */
...@@ -5794,29 +5845,29 @@ s390_emit_epilogue () ...@@ -5794,29 +5845,29 @@ s390_emit_epilogue ()
rtx insn, addr; rtx insn, addr;
int i; int i;
/* Check for global register and save them /* Check for global register and save them
to stack location from where they get restored. */ to stack location from where they get restored. */
for (i = cfun->machine->first_restore_gpr; for (i = cfun->machine->first_restore_gpr;
i <= cfun->machine->last_save_gpr; i <= cfun->machine->last_save_gpr;
i++) i++)
{ {
/* These registers are special and need to be /* These registers are special and need to be
restored in any case. */ restored in any case. */
if (i == STACK_POINTER_REGNUM if (i == STACK_POINTER_REGNUM
|| i == RETURN_REGNUM || i == RETURN_REGNUM
|| i == BASE_REGISTER || i == BASE_REGISTER
|| (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM)) || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
continue; continue;
if (global_regs[i]) if (global_regs[i])
{ {
addr = plus_constant (frame_pointer, addr = plus_constant (frame_pointer,
offset + i * UNITS_PER_WORD); offset + i * UNITS_PER_WORD);
addr = gen_rtx_MEM (Pmode, addr); addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, s390_sr_alias_set); set_mem_alias_set (addr, s390_sr_alias_set);
emit_move_insn (addr, gen_rtx_REG (Pmode, i)); emit_move_insn (addr, gen_rtx_REG (Pmode, i));
} }
} }
/* Fetch return address from stack before load multiple, /* Fetch return address from stack before load multiple,
...@@ -5828,9 +5879,9 @@ s390_emit_epilogue () ...@@ -5828,9 +5879,9 @@ s390_emit_epilogue ()
if (!return_regnum) if (!return_regnum)
return_regnum = 4; return_regnum = 4;
return_reg = gen_rtx_REG (Pmode, return_regnum); return_reg = gen_rtx_REG (Pmode, return_regnum);
addr = plus_constant (frame_pointer, addr = plus_constant (frame_pointer,
offset + RETURN_REGNUM * UNITS_PER_WORD); offset + RETURN_REGNUM * UNITS_PER_WORD);
addr = gen_rtx_MEM (Pmode, addr); addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, s390_sr_alias_set); set_mem_alias_set (addr, s390_sr_alias_set);
emit_move_insn (return_reg, addr); emit_move_insn (return_reg, addr);
...@@ -5840,10 +5891,10 @@ s390_emit_epilogue () ...@@ -5840,10 +5891,10 @@ s390_emit_epilogue ()
explicit in insn RTX code, we have to add a barrier here explicit in insn RTX code, we have to add a barrier here
to prevent incorrect scheduling. */ to prevent incorrect scheduling. */
emit_insn (gen_blockage()); emit_insn (gen_blockage());
insn = restore_gprs (frame_pointer, offset, insn = restore_gprs (frame_pointer, offset,
cfun->machine->first_restore_gpr, cfun->machine->first_restore_gpr,
cfun->machine->last_save_gpr); cfun->machine->last_save_gpr);
emit_insn (insn); emit_insn (insn);
} }
...@@ -5851,14 +5902,14 @@ s390_emit_epilogue () ...@@ -5851,14 +5902,14 @@ s390_emit_epilogue ()
/* Return to caller. */ /* Return to caller. */
p = rtvec_alloc (2); p = rtvec_alloc (2);
RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg); RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
} }
/* Return the size in bytes of a function argument of /* Return the size in bytes of a function argument of
type TYPE and/or mode MODE. At least one of TYPE or type TYPE and/or mode MODE. At least one of TYPE or
MODE must be specified. */ MODE must be specified. */
...@@ -5943,7 +5994,7 @@ s390_function_arg_pass_by_reference (mode, type) ...@@ -5943,7 +5994,7 @@ s390_function_arg_pass_by_reference (mode, type)
if (TREE_CODE (type) == COMPLEX_TYPE) if (TREE_CODE (type) == COMPLEX_TYPE)
return 1; return 1;
} }
return 0; return 0;
} }
...@@ -5986,7 +6037,7 @@ s390_function_arg_advance (cum, mode, type, named) ...@@ -5986,7 +6037,7 @@ s390_function_arg_advance (cum, mode, type, named)
CUM is a variable of type CUMULATIVE_ARGS which gives info about CUM is a variable of type CUMULATIVE_ARGS which gives info about
the preceding args and about the function being called. the preceding args and about the function being called.
NAMED is nonzero if this argument is a named parameter NAMED is nonzero if this argument is a named parameter
(otherwise it is an extra parameter matching an ellipsis). (otherwise it is an extra parameter matching an ellipsis).
On S/390, we use general purpose registers 2 through 6 to On S/390, we use general purpose registers 2 through 6 to
pass integer, pointer, and certain structure arguments, and pass integer, pointer, and certain structure arguments, and
...@@ -6034,12 +6085,12 @@ s390_function_arg (cum, mode, type, named) ...@@ -6034,12 +6085,12 @@ s390_function_arg (cum, mode, type, named)
long __fpr; long __fpr;
void *__overflow_arg_area; void *__overflow_arg_area;
void *__reg_save_area; void *__reg_save_area;
} va_list[1]; } va_list[1];
where __gpr and __fpr hold the number of general purpose where __gpr and __fpr hold the number of general purpose
or floating point arguments used up to now, respectively, or floating point arguments used up to now, respectively,
__overflow_arg_area points to the stack location of the __overflow_arg_area points to the stack location of the
next argument passed on the stack, and __reg_save_area next argument passed on the stack, and __reg_save_area
always points to the start of the register area in the always points to the start of the register area in the
call frame of the current function. The function prologue call frame of the current function. The function prologue
...@@ -6056,9 +6107,9 @@ s390_build_va_list () ...@@ -6056,9 +6107,9 @@ s390_build_va_list ()
type_decl = type_decl =
build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"), f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
long_integer_type_node); long_integer_type_node);
f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"), f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
long_integer_type_node); long_integer_type_node);
f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"), f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
ptr_type_node); ptr_type_node);
...@@ -6154,15 +6205,15 @@ s390_va_start (valist, nextarg) ...@@ -6154,15 +6205,15 @@ s390_va_start (valist, nextarg)
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
} }
/* Implement va_arg by updating the va_list structure /* Implement va_arg by updating the va_list structure
VALIST as required to retrieve an argument of type VALIST as required to retrieve an argument of type
TYPE, and returning that argument. TYPE, and returning that argument.
Generates code equivalent to: Generates code equivalent to:
if (integral value) { if (integral value) {
if (size <= 4 && args.gpr < 5 || if (size <= 4 && args.gpr < 5 ||
size > 4 && args.gpr < 4 ) size > 4 && args.gpr < 4 )
ret = args.reg_save_area[args.gpr+8] ret = args.reg_save_area[args.gpr+8]
else else
ret = *args.overflow_arg_area++; ret = *args.overflow_arg_area++;
...@@ -6248,6 +6299,7 @@ s390_va_arg (valist, type) ...@@ -6248,6 +6299,7 @@ s390_va_arg (valist, type)
reg = gpr; reg = gpr;
n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
sav_ofs = 2 * UNITS_PER_WORD; sav_ofs = 2 * UNITS_PER_WORD;
if (size < UNITS_PER_WORD) if (size < UNITS_PER_WORD)
sav_ofs += UNITS_PER_WORD - size; sav_ofs += UNITS_PER_WORD - size;
...@@ -6316,10 +6368,10 @@ s390_va_arg (valist, type) ...@@ -6316,10 +6368,10 @@ s390_va_arg (valist, type)
emit_label (lab_over); emit_label (lab_over);
/* If less than max_regs a registers are retrieved out /* If less than max_regs a registers are retrieved out
of register save area, increment. */ of register save area, increment. */
u = build (PREINCREMENT_EXPR, TREE_TYPE (reg), reg, u = build (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
build_int_2 (n_reg, 0)); build_int_2 (n_reg, 0));
TREE_SIDE_EFFECTS (u) = 1; TREE_SIDE_EFFECTS (u) = 1;
expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
...@@ -6388,7 +6440,7 @@ s390_expand_builtin (exp, target, subtarget, mode, ignore) ...@@ -6388,7 +6440,7 @@ s390_expand_builtin (exp, target, subtarget, mode, ignore)
{ {
#define MAX_ARGS 2 #define MAX_ARGS 2
unsigned int const *code_for_builtin = unsigned int const *code_for_builtin =
TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31; TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
...@@ -6504,13 +6556,13 @@ s390_initialize_trampoline (addr, fnaddr, cxt) ...@@ -6504,13 +6556,13 @@ s390_initialize_trampoline (addr, fnaddr, cxt)
rtx fnaddr; rtx fnaddr;
rtx cxt; rtx cxt;
{ {
emit_move_insn (gen_rtx emit_move_insn (gen_rtx
(MEM, Pmode, (MEM, Pmode,
memory_address (Pmode, memory_address (Pmode,
plus_constant (addr, (TARGET_64BIT ? 20 : 12) ))), cxt); plus_constant (addr, (TARGET_64BIT ? 20 : 12) ))), cxt);
emit_move_insn (gen_rtx emit_move_insn (gen_rtx
(MEM, Pmode, (MEM, Pmode,
memory_address (Pmode, memory_address (Pmode,
plus_constant (addr, (TARGET_64BIT ? 28 : 16) ))), fnaddr); plus_constant (addr, (TARGET_64BIT ? 28 : 16) ))), fnaddr);
} }
...@@ -6527,7 +6579,7 @@ s390_gen_rtx_const_DI (high, low) ...@@ -6527,7 +6579,7 @@ s390_gen_rtx_const_DI (high, low)
val = (HOST_WIDE_INT)high; val = (HOST_WIDE_INT)high;
val <<= 32; val <<= 32;
val |= (HOST_WIDE_INT)low; val |= (HOST_WIDE_INT)low;
return GEN_INT (val); return GEN_INT (val);
#else #else
#if HOST_BITS_PER_WIDE_INT >= 32 #if HOST_BITS_PER_WIDE_INT >= 32
...@@ -6536,7 +6588,7 @@ s390_gen_rtx_const_DI (high, low) ...@@ -6536,7 +6588,7 @@ s390_gen_rtx_const_DI (high, low)
abort (); abort ();
#endif #endif
#endif #endif
} }
/* Output assembler code to FILE to increment profiler label # LABELNO /* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */ for profiling a function entry. */
...@@ -6636,13 +6688,13 @@ s390_encode_section_info (decl, rtl, first) ...@@ -6636,13 +6688,13 @@ s390_encode_section_info (decl, rtl, first)
/* If a variable has a forced alignment to < 2 bytes, mark it with /* If a variable has a forced alignment to < 2 bytes, mark it with
SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */ SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
if (TREE_CODE (decl) == VAR_DECL if (TREE_CODE (decl) == VAR_DECL
&& DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16) && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1; SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
} }
/* Output thunk to FILE that implements a C++ virtual function call (with /* Output thunk to FILE that implements a C++ virtual function call (with
multiple inheritance) to FUNCTION. The thunk adjusts the this pointer multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
stored at VCALL_OFFSET in the vtable whose address is located at offset 0 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
relative to the resulting this pointer. */ relative to the resulting this pointer. */
...@@ -6696,9 +6748,9 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6696,9 +6748,9 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
if (TARGET_64BIT) if (TARGET_64BIT)
{ {
/* Setup literal pool pointer if required. */ /* Setup literal pool pointer if required. */
if ((!DISP_IN_RANGE (delta) if ((!DISP_IN_RANGE (delta)
&& !CONST_OK_FOR_LETTER_P (delta, 'K')) && !CONST_OK_FOR_LETTER_P (delta, 'K'))
|| (!DISP_IN_RANGE (vcall_offset) || (!DISP_IN_RANGE (vcall_offset)
&& !CONST_OK_FOR_LETTER_P (vcall_offset, 'K'))) && !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{ {
op[5] = gen_label_rtx (); op[5] = gen_label_rtx ();
...@@ -6743,7 +6795,7 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6743,7 +6795,7 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
output_asm_insn ("ag\t%1,0(%4)", op); output_asm_insn ("ag\t%1,0(%4)", op);
} }
} }
/* Jump to target. */ /* Jump to target. */
output_asm_insn ("jg\t%0", op); output_asm_insn ("jg\t%0", op);
...@@ -6889,6 +6941,13 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function) ...@@ -6889,6 +6941,13 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
} }
} }
bool
s390_valid_pointer_mode (mode)
enum machine_mode mode;
{
return (mode == SImode || (TARGET_64BIT && mode == DImode));
}
/* How to allocate a 'struct machine_function'. */ /* How to allocate a 'struct machine_function'. */
static struct machine_function * static struct machine_function *
......
gcc/config/s390/s390.h
...@@ -29,15 +29,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA ...@@ -29,15 +29,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
#include <s390/fixdfdi.h> #include <s390/fixdfdi.h>
#endif #endif
/* Which processor to generate code or schedule for. The cpu attribute /* Which processor to generate code or schedule for. The cpu attribute
defines a list that mirrors this list, so changes to s390.md must be defines a list that mirrors this list, so changes to s390.md must be
made at the same time. */ made at the same time. */
enum processor_type enum processor_type
{ {
PROCESSOR_9672_G5, PROCESSOR_9672_G5,
PROCESSOR_9672_G6, PROCESSOR_9672_G6,
PROCESSOR_2064_Z900, PROCESSOR_2064_Z900,
PROCESSOR_2084_Z990, PROCESSOR_2084_Z990,
PROCESSOR_max PROCESSOR_max
}; };
...@@ -94,6 +94,7 @@ extern int target_flags; ...@@ -94,6 +94,7 @@ extern int target_flags;
#define MASK_64BIT 0x10 #define MASK_64BIT 0x10
#define MASK_ZARCH 0x20 #define MASK_ZARCH 0x20
#define MASK_MVCLE 0x40 #define MASK_MVCLE 0x40
#define MASK_TPF 0x80
#define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT) #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
#define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT)) #define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT))
...@@ -103,6 +104,7 @@ extern int target_flags; ...@@ -103,6 +104,7 @@ extern int target_flags;
#define TARGET_64BIT (target_flags & MASK_64BIT) #define TARGET_64BIT (target_flags & MASK_64BIT)
#define TARGET_ZARCH (target_flags & MASK_ZARCH) #define TARGET_ZARCH (target_flags & MASK_ZARCH)
#define TARGET_MVCLE (target_flags & MASK_MVCLE) #define TARGET_MVCLE (target_flags & MASK_MVCLE)
#define TARGET_TPF (target_flags & MASK_TPF)
/* ??? Once this actually works, it could be made a runtime option. */ /* ??? Once this actually works, it could be made a runtime option. */
#define TARGET_IBM_FLOAT 0 #define TARGET_IBM_FLOAT 0
...@@ -129,6 +131,8 @@ extern int target_flags; ...@@ -129,6 +131,8 @@ extern int target_flags;
{ "esa", -32, N_("ESA/390 architecture")}, \ { "esa", -32, N_("ESA/390 architecture")}, \
{ "mvcle", 64, N_("mvcle use")}, \ { "mvcle", 64, N_("mvcle use")}, \
{ "no-mvcle", -64, N_("mvc&ex")}, \ { "no-mvcle", -64, N_("mvc&ex")}, \
{ "tpf", 128, N_("enable tpf OS code")}, \
{ "no-tpf", -128, N_("disable tpf OS code")}, \
{ "", TARGET_DEFAULT, 0 } } { "", TARGET_DEFAULT, 0 } }
#define TARGET_OPTIONS \ #define TARGET_OPTIONS \
...@@ -264,7 +268,7 @@ if (INTEGRAL_MODE_P (MODE) && \ ...@@ -264,7 +268,7 @@ if (INTEGRAL_MODE_P (MODE) && \
/* We have 16 general purpose registers (registers 0-15), /* We have 16 general purpose registers (registers 0-15),
and 16 floating point registers (registers 16-31). and 16 floating point registers (registers 16-31).
(On non-IEEE machines, we have only 4 fp registers.) (On non-IEEE machines, we have only 4 fp registers.)
Amongst the general purpose registers, some are used Amongst the general purpose registers, some are used
for specific purposes: for specific purposes:
GPR 11: Hard frame pointer (if needed) GPR 11: Hard frame pointer (if needed)
...@@ -272,7 +276,7 @@ if (INTEGRAL_MODE_P (MODE) && \ ...@@ -272,7 +276,7 @@ if (INTEGRAL_MODE_P (MODE) && \
GPR 13: Literal pool base register GPR 13: Literal pool base register
GPR 14: Return address register GPR 14: Return address register
GPR 15: Stack pointer GPR 15: Stack pointer
Registers 32-34 are 'fake' hard registers that do not Registers 32-34 are 'fake' hard registers that do not
correspond to actual hardware: correspond to actual hardware:
Reg 32: Argument pointer Reg 32: Argument pointer
...@@ -376,19 +380,19 @@ do \ ...@@ -376,19 +380,19 @@ do \
/* Fitting values into registers. */ /* Fitting values into registers. */
/* Integer modes <= word size fit into any GPR. /* Integer modes <= word size fit into any GPR.
Integer modes > word size fit into successive GPRs, starting with Integer modes > word size fit into successive GPRs, starting with
an even-numbered register. an even-numbered register.
SImode and DImode fit into FPRs as well. SImode and DImode fit into FPRs as well.
Floating point modes <= word size fit into any FPR or GPR. Floating point modes <= word size fit into any FPR or GPR.
Floating point modes > word size (i.e. DFmode on 32-bit) fit Floating point modes > word size (i.e. DFmode on 32-bit) fit
into any FPR, or an even-odd GPR pair. into any FPR, or an even-odd GPR pair.
Complex floating point modes fit either into two FPRs, or into Complex floating point modes fit either into two FPRs, or into
successive GPRs (again starting with an even number). successive GPRs (again starting with an even number).
Condition code modes fit only into the CC register. */ Condition code modes fit only into the CC register. */
#define HARD_REGNO_NREGS(REGNO, MODE) \ #define HARD_REGNO_NREGS(REGNO, MODE) \
...@@ -430,19 +434,19 @@ do \ ...@@ -430,19 +434,19 @@ do \
? reg_classes_intersect_p (FP_REGS, CLASS) : 0) ? reg_classes_intersect_p (FP_REGS, CLASS) : 0)
/* Register classes. */ /* Register classes. */
/* We use the following register classes: /* We use the following register classes:
GENERAL_REGS All general purpose registers GENERAL_REGS All general purpose registers
ADDR_REGS All general purpose registers except %r0 ADDR_REGS All general purpose registers except %r0
(These registers can be used in address generation) (These registers can be used in address generation)
FP_REGS All floating point registers FP_REGS All floating point registers
GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
ADDR_FP_REGS Union of ADDR_REGS and FP_REGS ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
NO_REGS No registers NO_REGS No registers
ALL_REGS All registers ALL_REGS All registers
Note that the 'fake' frame pointer and argument pointer registers Note that the 'fake' frame pointer and argument pointer registers
are included amongst the address registers here. The condition are included amongst the address registers here. The condition
code register is only included in ALL_REGS. */ code register is only included in ALL_REGS. */
...@@ -539,7 +543,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; ...@@ -539,7 +543,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
/* Stack layout and calling conventions. */ /* Stack layout and calling conventions. */
/* Our stack grows from higher to lower addresses. However, local variables /* Our stack grows from higher to lower addresses. However, local variables
are accessed by positive offsets, and function arguments are stored at are accessed by positive offsets, and function arguments are stored at
increasing addresses. */ increasing addresses. */
...@@ -569,7 +573,7 @@ extern int current_function_outgoing_args_size; ...@@ -569,7 +573,7 @@ extern int current_function_outgoing_args_size;
the argument area. */ the argument area. */
#define FIRST_PARM_OFFSET(FNDECL) 0 #define FIRST_PARM_OFFSET(FNDECL) 0
/* The return address of the current frame is retrieved /* The return address of the current frame is retrieved
from the initial value of register RETURN_REGNUM. from the initial value of register RETURN_REGNUM.
For frames farther back, we use the stack slot where For frames farther back, we use the stack slot where
the corresponding RETURN_REGNUM register was saved. */ the corresponding RETURN_REGNUM register was saved. */
...@@ -577,7 +581,7 @@ extern int current_function_outgoing_args_size; ...@@ -577,7 +581,7 @@ extern int current_function_outgoing_args_size;
#define DYNAMIC_CHAIN_ADDRESS(FRAME) \ #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \ ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \
plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
#define RETURN_ADDR_RTX(COUNT, FRAME) \ #define RETURN_ADDR_RTX(COUNT, FRAME) \
s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
...@@ -586,7 +590,7 @@ extern int current_function_outgoing_args_size; ...@@ -586,7 +590,7 @@ extern int current_function_outgoing_args_size;
/* Exception handling. */ /* Exception handling. */
/* Describe calling conventions for DWARF-2 exception handling. */ /* Describe calling conventions for DWARF-2 exception handling. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
#define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
...@@ -612,8 +616,8 @@ extern int current_function_outgoing_args_size; ...@@ -612,8 +616,8 @@ extern int current_function_outgoing_args_size;
#define HARD_FRAME_POINTER_REGNUM 11 #define HARD_FRAME_POINTER_REGNUM 11
#define ARG_POINTER_REGNUM 32 #define ARG_POINTER_REGNUM 32
/* The static chain must be call-clobbered, but not used for /* The static chain must be call-clobbered, but not used for
function argument passing. As register 1 is clobbered by function argument passing. As register 1 is clobbered by
the trampoline code, we only have one option. */ the trampoline code, we only have one option. */
#define STATIC_CHAIN_REGNUM 0 #define STATIC_CHAIN_REGNUM 0
...@@ -633,7 +637,7 @@ extern int current_function_outgoing_args_size; ...@@ -633,7 +637,7 @@ extern int current_function_outgoing_args_size;
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
#define CAN_ELIMINATE(FROM, TO) (1) #define CAN_ELIMINATE(FROM, TO) (1)
...@@ -654,7 +658,7 @@ extern int current_function_outgoing_args_size; ...@@ -654,7 +658,7 @@ extern int current_function_outgoing_args_size;
/* Stack arguments. */ /* Stack arguments. */
/* We need current_function_outgoing_args to be valid. */ /* We need current_function_outgoing_args to be valid. */
#define ACCUMULATE_OUTGOING_ARGS 1 #define ACCUMULATE_OUTGOING_ARGS 1
...@@ -663,7 +667,7 @@ extern int current_function_outgoing_args_size; ...@@ -663,7 +667,7 @@ extern int current_function_outgoing_args_size;
/* Register arguments. */ /* Register arguments. */
typedef struct s390_arg_structure typedef struct s390_arg_structure
{ {
int gprs; /* gpr so far */ int gprs; /* gpr so far */
...@@ -692,7 +696,7 @@ CUMULATIVE_ARGS; ...@@ -692,7 +696,7 @@ CUMULATIVE_ARGS;
/* Scalar return values. */ /* Scalar return values. */
/* We return scalars in general purpose register 2 for integral values, /* We return scalars in general purpose register 2 for integral values,
and floating point register 0 for fp values. */ and floating point register 0 for fp values. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \ #define FUNCTION_VALUE(VALTYPE, FUNC) \
...@@ -726,7 +730,7 @@ CUMULATIVE_ARGS; ...@@ -726,7 +730,7 @@ CUMULATIVE_ARGS;
/* Function entry and exit. */ /* Function entry and exit. */
/* When returning from a function, the stack pointer does not matter. */ /* When returning from a function, the stack pointer does not matter. */
#define EXIT_IGNORE_STACK 1 #define EXIT_IGNORE_STACK 1
...@@ -763,7 +767,7 @@ CUMULATIVE_ARGS; ...@@ -763,7 +767,7 @@ CUMULATIVE_ARGS;
/* Library calls. */ /* Library calls. */
/* We should use memcpy, not bcopy. */ /* We should use memcpy, not bcopy. */
#define TARGET_MEM_FUNCTIONS #define TARGET_MEM_FUNCTIONS
...@@ -790,7 +794,7 @@ CUMULATIVE_ARGS; ...@@ -790,7 +794,7 @@ CUMULATIVE_ARGS;
#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
((GET_MODE (X) == Pmode) && \ ((GET_MODE (X) == Pmode) && \
((REGNO (X) >= FIRST_PSEUDO_REGISTER) \ ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS)) || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
#define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
...@@ -860,7 +864,7 @@ CUMULATIVE_ARGS; ...@@ -860,7 +864,7 @@ CUMULATIVE_ARGS;
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. */ return the mode to be used for the comparison. */
#define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
/* Define the information needed to generate branch and scc insns. This is /* Define the information needed to generate branch and scc insns. This is
stored from the compare operation. Note that we can't use "rtx" here stored from the compare operation. Note that we can't use "rtx" here
since it hasn't been defined! */ since it hasn't been defined! */
...@@ -933,7 +937,7 @@ extern struct rtx_def *s390_compare_op0, *s390_compare_op1; ...@@ -933,7 +937,7 @@ extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
/* Position independent code. */ /* Position independent code. */
extern int flag_pic; extern int flag_pic;
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
...@@ -1087,7 +1091,7 @@ extern int s390_nr_constants; ...@@ -1087,7 +1091,7 @@ extern int s390_nr_constants;
#define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
/* Load from integral MODE < SI from memory into register makes sign_extend /* Load from integral MODE < SI from memory into register makes sign_extend
or zero_extend or zero_extend
In our case sign_extension happens for Halfwords, other no extension. */ In our case sign_extension happens for Halfwords, other no extension. */
#define LOAD_EXTEND_OP(MODE) \ #define LOAD_EXTEND_OP(MODE) \
(TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \ (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \
...@@ -1103,6 +1107,9 @@ extern int s390_nr_constants; ...@@ -1103,6 +1107,9 @@ extern int s390_nr_constants;
between pointers and any other objects of this machine mode. */ between pointers and any other objects of this machine mode. */
#define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
/* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */
#define POINTERS_EXTEND_UNSIGNED -1
/* A function address in a call instruction is a byte address (for /* A function address in a call instruction is a byte address (for
indexing purposes) so give the MEM rtx a byte's mode. */ indexing purposes) so give the MEM rtx a byte's mode. */
#define FUNCTION_MODE QImode #define FUNCTION_MODE QImode
...@@ -1110,4 +1117,4 @@ extern int s390_nr_constants; ...@@ -1110,4 +1117,4 @@ extern int s390_nr_constants;
/* This macro definition sets up a default value for `main' to return. */ /* This macro definition sets up a default value for `main' to return. */
#define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node) #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node)
#endif #endif
gcc/config/s390/s390.md
...@@ -115,7 +115,7 @@ ...@@ -115,7 +115,7 @@
fmuld,fmuls,fdivd,fdivs, fmuld,fmuls,fdivd,fdivs,
ftoi,itof,fsqrtd,fsqrts, ftoi,itof,fsqrtd,fsqrts,
other,o2,o3" other,o2,o3"
(const_string "integer")) (const_string "integer"))
;; Operand type. Used to default length attribute values ;; Operand type. Used to default length attribute values
...@@ -147,7 +147,7 @@ ...@@ -147,7 +147,7 @@
(eq_attr "op_type" "SIY") (const_string "agen")] (eq_attr "op_type" "SIY") (const_string "agen")]
(const_string "reg"))) (const_string "reg")))
;; Generic pipeline function unit. ;; Generic pipeline function unit.
(define_function_unit "integer" 1 0 (define_function_unit "integer" 1 0
(eq_attr "type" "none") 0 0) (eq_attr "type" "none") 0 0)
...@@ -286,11 +286,11 @@ ...@@ -286,11 +286,11 @@
; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
; CCZ -> CCL / CCZ1 ; CCZ -> CCL / CCZ1
; CCZ1 -> CCA/CCU/CCS/CCT ; CCZ1 -> CCA/CCU/CCS/CCT
; CCS -> CCA ; CCS -> CCA
; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
...@@ -357,7 +357,7 @@ ...@@ -357,7 +357,7 @@
(match_operand:DI 2 "const_int_operand" "n")) (match_operand:DI 2 "const_int_operand" "n"))
(const_int 0)))] (const_int 0)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
&& (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
== INTVAL (operands[2]) >> 4" == INTVAL (operands[2]) >> 4"
...@@ -387,7 +387,7 @@ ...@@ -387,7 +387,7 @@
(match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 2 "const_int_operand" "n"))
(const_int 0)))] (const_int 0)))]
"s390_match_ccmode(insn, CCTmode) "s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
&& (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
== INTVAL (operands[2]) >> 4" == INTVAL (operands[2]) >> 4"
...@@ -415,7 +415,7 @@ ...@@ -415,7 +415,7 @@
(match_operand:SI 2 "const_int_operand" "n,n")) (match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))] (const_int 0)))]
"s390_match_ccmode(insn, CCTmode) "s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
"* "*
{ {
...@@ -442,7 +442,7 @@ ...@@ -442,7 +442,7 @@
int part = s390_single_qi (operands[1], DImode, 0); int part = s390_single_qi (operands[1], DImode, 0);
operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part)); operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
operands[0] = gen_rtx_MEM (QImode, operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part)); plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\"; return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}" }"
...@@ -460,7 +460,7 @@ ...@@ -460,7 +460,7 @@
int part = s390_single_qi (operands[1], SImode, 0); int part = s390_single_qi (operands[1], SImode, 0);
operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part)); operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
operands[0] = gen_rtx_MEM (QImode, operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part)); plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\"; return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}" }"
...@@ -478,7 +478,7 @@ ...@@ -478,7 +478,7 @@
int part = s390_single_qi (operands[1], HImode, 0); int part = s390_single_qi (operands[1], HImode, 0);
operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part)); operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
operands[0] = gen_rtx_MEM (QImode, operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part)); plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\"; return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}" }"
...@@ -749,7 +749,7 @@ ...@@ -749,7 +749,7 @@
cghi\\t%0,%c1 cghi\\t%0,%c1
cg\\t%0,%1" cg\\t%0,%1"
[(set_attr "op_type" "RRE,RI,RXY")]) [(set_attr "op_type" "RRE,RI,RXY")])
(define_insn "*cmpsi_ccs_sign" (define_insn "*cmpsi_ccs_sign"
[(set (reg 33) [(set (reg 33)
(compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
...@@ -771,7 +771,7 @@ ...@@ -771,7 +771,7 @@
c\\t%0,%1 c\\t%0,%1
cy\\t%0,%1" cy\\t%0,%1"
[(set_attr "op_type" "RR,RI,RX,RXY")]) [(set_attr "op_type" "RR,RI,RX,RXY")])
; Compare (unsigned) instructions ; Compare (unsigned) instructions
...@@ -1045,7 +1045,7 @@ ...@@ -1045,7 +1045,7 @@
/* During and after reload, we need to force constants /* During and after reload, we need to force constants
to the literal pool ourselves, if necessary. */ to the literal pool ourselves, if necessary. */
if ((reload_in_progress || reload_completed) if ((reload_in_progress || reload_completed)
&& CONSTANT_P (operands[1]) && CONSTANT_P (operands[1])
&& (!legitimate_reload_constant_p (operands[1]) && (!legitimate_reload_constant_p (operands[1])
|| FP_REG_P (operands[0]))) || FP_REG_P (operands[0])))
operands[1] = force_const_mem (DImode, operands[1]); operands[1] = force_const_mem (DImode, operands[1]);
...@@ -1085,7 +1085,7 @@ ...@@ -1085,7 +1085,7 @@
(define_insn "*movdi_lay" (define_insn "*movdi_lay"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(match_operand:DI 1 "address_operand" "p"))] (match_operand:DI 1 "address_operand" "p"))]
"TARGET_64BIT "TARGET_64BIT
&& TARGET_LONG_DISPLACEMENT && TARGET_LONG_DISPLACEMENT
&& GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT
&& !FP_REG_P (operands[0])" && !FP_REG_P (operands[0])"
...@@ -1216,8 +1216,8 @@ ...@@ -1216,8 +1216,8 @@
if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
emit_symbolic_move (operands); emit_symbolic_move (operands);
/* expr.c tries to load an effective address using /* expr.c tries to load an effective address using
force_reg. This fails because we don't have a force_reg. This fails because we don't have a
generic load_address pattern. Convert the move generic load_address pattern. Convert the move
to a proper arithmetic operation instead, unless to a proper arithmetic operation instead, unless
it is guaranteed to be OK. */ it is guaranteed to be OK. */
...@@ -1232,7 +1232,7 @@ ...@@ -1232,7 +1232,7 @@
/* During and after reload, we need to force constants /* During and after reload, we need to force constants
to the literal pool ourselves, if necessary. */ to the literal pool ourselves, if necessary. */
if ((reload_in_progress || reload_completed) if ((reload_in_progress || reload_completed)
&& CONSTANT_P (operands[1]) && CONSTANT_P (operands[1])
&& (!legitimate_reload_constant_p (operands[1]) && (!legitimate_reload_constant_p (operands[1])
|| FP_REG_P (operands[0]))) || FP_REG_P (operands[0])))
operands[1] = force_const_mem (SImode, operands[1]); operands[1] = force_const_mem (SImode, operands[1]);
...@@ -1658,7 +1658,7 @@ ...@@ -1658,7 +1658,7 @@
(set_attr "type" "lm")]) (set_attr "type" "lm")])
; ;
; store multiple pattern(s). ; store multiple pattern(s).
; ;
(define_expand "store_multiple" (define_expand "store_multiple"
...@@ -1708,7 +1708,7 @@ ...@@ -1708,7 +1708,7 @@
if (to == frame_pointer_rtx || to == arg_pointer_rtx) if (to == frame_pointer_rtx || to == arg_pointer_rtx)
FAIL; FAIL;
} }
else else
{ {
to = force_reg (Pmode, XEXP (operands[0], 0)); to = force_reg (Pmode, XEXP (operands[0], 0));
off = 0; off = 0;
...@@ -1993,7 +1993,7 @@ ...@@ -1993,7 +1993,7 @@
(use (match_operand:DI 3 "general_operand" "")) (use (match_operand:DI 3 "general_operand" ""))
(use (match_operand:DI 4 "" ""))] (use (match_operand:DI 4 "" ""))]
"TARGET_64BIT" "TARGET_64BIT"
"s390_expand_cmpmem (operands[0], operands[1], "s390_expand_cmpmem (operands[0], operands[1],
operands[2], operands[3]); DONE;") operands[2], operands[3]); DONE;")
(define_expand "cmpmemsi" (define_expand "cmpmemsi"
...@@ -2003,7 +2003,7 @@ ...@@ -2003,7 +2003,7 @@
(use (match_operand:SI 3 "general_operand" "")) (use (match_operand:SI 3 "general_operand" ""))
(use (match_operand:SI 4 "" ""))] (use (match_operand:SI 4 "" ""))]
"" ""
"s390_expand_cmpmem (operands[0], operands[1], "s390_expand_cmpmem (operands[0], operands[1],
operands[2], operands[3]); DONE;") operands[2], operands[3]); DONE;")
; Compare a block that is up to 256 bytes in length. ; Compare a block that is up to 256 bytes in length.
...@@ -2263,7 +2263,7 @@ ...@@ -2263,7 +2263,7 @@
{ {
operands[1] = gen_lowpart (DImode, operands[1]); operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
DONE; DONE;
} }
} }
...@@ -2297,7 +2297,7 @@ ...@@ -2297,7 +2297,7 @@
{ {
operands[1] = gen_lowpart (DImode, operands[1]); operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
DONE; DONE;
} }
} }
...@@ -2334,7 +2334,7 @@ ...@@ -2334,7 +2334,7 @@
{ {
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
DONE; DONE;
} }
") ")
...@@ -2360,7 +2360,7 @@ ...@@ -2360,7 +2360,7 @@
{ {
operands[1] = gen_lowpart (SImode, operands[1]); operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
DONE; DONE;
} }
") ")
...@@ -2439,7 +2439,7 @@ ...@@ -2439,7 +2439,7 @@
{ {
operands[1] = gen_lowpart (DImode, operands[1]); operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
DONE; DONE;
} }
} }
...@@ -2473,7 +2473,7 @@ ...@@ -2473,7 +2473,7 @@
{ {
operands[1] = gen_lowpart (DImode, operands[1]); operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
DONE; DONE;
} }
} }
...@@ -2522,7 +2522,7 @@ ...@@ -2522,7 +2522,7 @@
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"operands[2] = gen_lowpart (HImode, operands[0]);" "operands[2] = gen_lowpart (HImode, operands[0]);"
[(set_attr "atype" "agen")]) [(set_attr "atype" "agen")])
; ;
; zero_extendqisi2 instruction pattern(s). ; zero_extendqisi2 instruction pattern(s).
; ;
...@@ -2556,7 +2556,7 @@ ...@@ -2556,7 +2556,7 @@
(set (strict_low_part (match_dup 2)) (match_dup 1))] (set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);" "operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "atype" "agen")]) [(set_attr "atype" "agen")])
; ;
; zero_extendqihi2 instruction pattern(s). ; zero_extendqihi2 instruction pattern(s).
; ;
...@@ -2607,7 +2607,7 @@ ...@@ -2607,7 +2607,7 @@
rtx temp = gen_reg_rtx (DFmode); rtx temp = gen_reg_rtx (DFmode);
operands[1] = force_reg (DFmode, operands[1]); operands[1] = force_reg (DFmode, operands[1]);
emit_insn (gen_cmpdf (operands[1], emit_insn (gen_cmpdf (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE ( CONST_DOUBLE_FROM_REAL_VALUE (
REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode))); REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
emit_jump_insn (gen_blt (label1)); emit_jump_insn (gen_blt (label1));
...@@ -2659,7 +2659,7 @@ ...@@ -2659,7 +2659,7 @@
rtx temp = gen_reg_rtx (DFmode); rtx temp = gen_reg_rtx (DFmode);
operands[1] = force_reg (DFmode,operands[1]); operands[1] = force_reg (DFmode,operands[1]);
emit_insn (gen_cmpdf (operands[1], emit_insn (gen_cmpdf (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE ( CONST_DOUBLE_FROM_REAL_VALUE (
REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode))); REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
emit_jump_insn (gen_blt (label1)); emit_jump_insn (gen_blt (label1));
...@@ -2681,7 +2681,7 @@ ...@@ -2681,7 +2681,7 @@
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
" "
{ {
if (TARGET_IBM_FLOAT) if (TARGET_IBM_FLOAT)
{ {
/* This is the algorithm from POP chapter A.5.7.2. */ /* This is the algorithm from POP chapter A.5.7.2. */
...@@ -2690,10 +2690,10 @@ ...@@ -2690,10 +2690,10 @@
rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
operands[1] = force_reg (DFmode, operands[1]); operands[1] = force_reg (DFmode, operands[1]);
emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
two31r, two32, temp)); two31r, two32, temp));
} }
else else
{ {
operands[1] = force_reg (DFmode, operands[1]); operands[1] = force_reg (DFmode, operands[1]);
emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
...@@ -2748,7 +2748,7 @@ ...@@ -2748,7 +2748,7 @@
rtx temp = gen_reg_rtx (SFmode); rtx temp = gen_reg_rtx (SFmode);
operands[1] = force_reg (SFmode, operands[1]); operands[1] = force_reg (SFmode, operands[1]);
emit_insn (gen_cmpsf (operands[1], emit_insn (gen_cmpsf (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE ( CONST_DOUBLE_FROM_REAL_VALUE (
REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode))); REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
emit_jump_insn (gen_blt (label1)); emit_jump_insn (gen_blt (label1));
...@@ -2887,12 +2887,12 @@ ...@@ -2887,12 +2887,12 @@
"TARGET_HARD_FLOAT" "TARGET_HARD_FLOAT"
" "
{ {
if (TARGET_IBM_FLOAT) if (TARGET_IBM_FLOAT)
{ {
/* This is the algorithm from POP chapter A.5.7.1. */ /* This is the algorithm from POP chapter A.5.7.1. */
rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
DONE; DONE;
...@@ -3024,7 +3024,7 @@ ...@@ -3024,7 +3024,7 @@
[(set_attr "op_type" "NN,NN") [(set_attr "op_type" "NN,NN")
(set_attr "atype" "reg,agen") (set_attr "atype" "reg,agen")
(set_attr "length" "4,6") (set_attr "length" "4,6")
(set_attr "type" "o2,o2")]) (set_attr "type" "o2,o2")])
;; ;;
...@@ -3054,7 +3054,7 @@ ...@@ -3054,7 +3054,7 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc" (define_insn "*adddi3_zero_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0")) (match_operand:DI 1 "register_operand" "0,0"))
(const_int 0))) (const_int 0)))
...@@ -3067,7 +3067,7 @@ ...@@ -3067,7 +3067,7 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly" (define_insn "*adddi3_zero_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0")) (match_operand:DI 1 "register_operand" "0,0"))
(const_int 0))) (const_int 0)))
...@@ -3090,20 +3090,20 @@ ...@@ -3090,20 +3090,20 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc" (define_insn "*adddi3_imm_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:DI 2 "const_int_operand" "K")) (match_operand:DI 2 "const_int_operand" "K"))
(const_int 0))) (const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d") (set (match_operand:DI 0 "register_operand" "=d")
(plus:DI (match_dup 1) (match_dup 2)))] (plus:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT "TARGET_64BIT
&& s390_match_ccmode (insn, CCAmode) && s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"aghi\\t%0,%h2" "aghi\\t%0,%h2"
[(set_attr "op_type" "RI")]) [(set_attr "op_type" "RI")])
(define_insn "*adddi3_cc" (define_insn "*adddi3_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m")) (match_operand:DI 2 "general_operand" "d,m"))
(const_int 0))) (const_int 0)))
...@@ -3116,7 +3116,7 @@ ...@@ -3116,7 +3116,7 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly" (define_insn "*adddi3_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m")) (match_operand:DI 2 "general_operand" "d,m"))
(const_int 0))) (const_int 0)))
...@@ -3128,7 +3128,7 @@ ...@@ -3128,7 +3128,7 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2" (define_insn "*adddi3_cconly2"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(neg:SI (match_operand:DI 2 "general_operand" "d,m")))) (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
(clobber (match_scratch:DI 0 "=d,d"))] (clobber (match_scratch:DI 0 "=d,d"))]
...@@ -3239,13 +3239,13 @@ ...@@ -3239,13 +3239,13 @@
DONE; DONE;
}") }")
; ;
; addsi3 instruction pattern(s). ; addsi3 instruction pattern(s).
; ;
(define_insn "*addsi3_imm_cc" (define_insn "*addsi3_imm_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "const_int_operand" "K")) (match_operand:SI 2 "const_int_operand" "K"))
(const_int 0))) (const_int 0)))
...@@ -3257,13 +3257,13 @@ ...@@ -3257,13 +3257,13 @@
[(set_attr "op_type" "RI")]) [(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc" (define_insn "*addsi3_carry1_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1))) (match_dup 1)))
(set (match_operand:SI 0 "register_operand" "=d,d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2 al\\t%0,%2
...@@ -3271,12 +3271,12 @@ ...@@ -3271,12 +3271,12 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly" (define_insn "*addsi3_carry1_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1))) (match_dup 1)))
(clobber (match_scratch:SI 0 "=d,d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2 al\\t%0,%2
...@@ -3284,13 +3284,13 @@ ...@@ -3284,13 +3284,13 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc" (define_insn "*addsi3_carry2_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2))) (match_dup 2)))
(set (match_operand:SI 0 "register_operand" "=d,d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2 al\\t%0,%2
...@@ -3298,12 +3298,12 @@ ...@@ -3298,12 +3298,12 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly" (define_insn "*addsi3_carry2_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")) (match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2))) (match_dup 2)))
(clobber (match_scratch:SI 0 "=d,d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)" "s390_match_ccmode (insn, CCL1mode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2 al\\t%0,%2
...@@ -3311,13 +3311,13 @@ ...@@ -3311,13 +3311,13 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc" (define_insn "*addsi3_cc"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d") (set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2 al\\t%0,%2
...@@ -3325,12 +3325,12 @@ ...@@ -3325,12 +3325,12 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly" (define_insn "*addsi3_cconly"
[(set (reg 33) [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T")) (match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0))) (const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
"s390_match_ccmode (insn, CCLmode)" "s390_match_ccmode (insn, CCLmode)"
"@ "@
alr\\t%0,%2 alr\\t%0,%2
al\\t%0,%2 al\\t%0,%2
...@@ -3338,7 +3338,7 @@ ...@@ -3338,7 +3338,7 @@
[(set_attr "op_type" "RR,RX,RXY")]) [(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2" (define_insn "*addsi3_cconly2"
[(set (reg 33) [(set (reg 33)
(compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:SI 0 "=d,d,d"))] (clobber (match_scratch:SI 0 "=d,d,d"))]
...@@ -3439,7 +3439,7 @@ ...@@ -3439,7 +3439,7 @@
"!TARGET_64BIT" "!TARGET_64BIT"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 0) [(set (match_dup 0)
(and:SI (match_dup 1) (const_int 2147483647)))] (and:SI (match_dup 1) (const_int 2147483647)))]
"" ""
[(set_attr "op_type" "RX") [(set_attr "op_type" "RX")
...@@ -3563,7 +3563,7 @@ ...@@ -3563,7 +3563,7 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc" (define_insn "*subdi3_zero_cc"
[(set (reg 33) [(set (reg 33)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0))) (const_int 0)))
...@@ -3576,7 +3576,7 @@ ...@@ -3576,7 +3576,7 @@
[(set_attr "op_type" "RRE,RXY")]) [(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly" (define_insn "*subdi3_zero_cconly"
[(set (reg 33) [(set (reg 33)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0))) (const_int 0)))
...@@ -3910,17 +3910,17 @@ ...@@ -3910,17 +3910,17 @@
insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2])); insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, gen_rtx_EXPR_LIST (REG_EQUAL,
gen_rtx_MULT (DImode, gen_rtx_MULT (DImode,
gen_rtx_SIGN_EXTEND (DImode, operands[1]), gen_rtx_SIGN_EXTEND (DImode, operands[1]),
gen_rtx_SIGN_EXTEND (DImode, operands[2])), gen_rtx_SIGN_EXTEND (DImode, operands[2])),
REG_NOTES (insn)); REG_NOTES (insn));
DONE; DONE;
}") }")
(define_insn "mulsi_6432" (define_insn "mulsi_6432"
[(set (match_operand:DI 0 "register_operand" "=d,d") [(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (mult:DI (sign_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))] (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
...@@ -3930,7 +3930,7 @@ ...@@ -3930,7 +3930,7 @@
m\\t%0,%2" m\\t%0,%2"
[(set_attr "op_type" "RR,RX") [(set_attr "op_type" "RR,RX")
(set_attr "type" "imul")]) (set_attr "type" "imul")])
; ;
; muldf3 instruction pattern(s). ; muldf3 instruction pattern(s).
; ;
...@@ -4061,7 +4061,7 @@ ...@@ -4061,7 +4061,7 @@
(match_operand:DI 2 "general_operand" "d,m"))) (match_operand:DI 2 "general_operand" "d,m")))
(ashift:TI (ashift:TI
(zero_extend:TI (zero_extend:TI
(mod:DI (truncate:DI (match_dup 1)) (mod:DI (truncate:DI (match_dup 1))
(match_dup 2))) (match_dup 2)))
(const_int 64))))] (const_int 64))))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -4079,7 +4079,7 @@ ...@@ -4079,7 +4079,7 @@
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
(ashift:TI (ashift:TI
(zero_extend:TI (zero_extend:TI
(mod:DI (truncate:DI (match_dup 1)) (mod:DI (truncate:DI (match_dup 1))
(sign_extend:DI (match_dup 2)))) (sign_extend:DI (match_dup 2))))
(const_int 64))))] (const_int 64))))]
"TARGET_64BIT" "TARGET_64BIT"
...@@ -4134,7 +4134,7 @@ ...@@ -4134,7 +4134,7 @@
(define_insn "udivmodtidi3" (define_insn "udivmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d") [(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI (zero_extend:TI (ior:TI (zero_extend:TI
(truncate:DI (truncate:DI
(udiv:TI (match_operand:TI 1 "register_operand" "0,0") (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
(zero_extend:TI (zero_extend:TI
...@@ -4197,7 +4197,7 @@ ...@@ -4197,7 +4197,7 @@
(ior:DI (zero_extend:DI (ior:DI (zero_extend:DI
(truncate:SI (truncate:SI
(div:DI (match_operand:DI 1 "register_operand" "0,0") (div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))) (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
(ashift:DI (ashift:DI
(zero_extend:DI (zero_extend:DI
...@@ -4251,32 +4251,32 @@ ...@@ -4251,32 +4251,32 @@
} }
else else
{ {
operands[2] = force_reg (SImode, operands[2]); operands[2] = force_reg (SImode, operands[2]);
operands[2] = make_safe_from (operands[2], operands[0]); operands[2] = make_safe_from (operands[2], operands[0]);
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2])); operands[2]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
insn = emit_move_insn (operands[0], insn = emit_move_insn (operands[0],
gen_lowpart (SImode, operands[3])); gen_lowpart (SImode, operands[3]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, gen_rtx_EXPR_LIST (REG_EQUAL,
udiv_equal, REG_NOTES (insn)); udiv_equal, REG_NOTES (insn));
} }
} }
else else
{ {
rtx label1 = gen_label_rtx (); rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx (); rtx label2 = gen_label_rtx ();
rtx label3 = gen_label_rtx (); rtx label3 = gen_label_rtx ();
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
operands[1] = make_safe_from (operands[1], operands[0]); operands[1] = make_safe_from (operands[1], operands[0]);
operands[2] = force_reg (SImode, operands[2]); operands[2] = force_reg (SImode, operands[2]);
operands[2] = make_safe_from (operands[2], operands[0]); operands[2] = make_safe_from (operands[2], operands[0]);
emit_move_insn (operands[0], const0_rtx); emit_move_insn (operands[0], const0_rtx);
emit_insn (gen_cmpsi (operands[2], operands[1])); emit_insn (gen_cmpsi (operands[2], operands[1]));
...@@ -4290,11 +4290,11 @@ ...@@ -4290,11 +4290,11 @@
operands[2])); operands[2]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
insn = emit_move_insn (operands[0], insn = emit_move_insn (operands[0],
gen_lowpart (SImode, operands[3])); gen_lowpart (SImode, operands[3]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, gen_rtx_EXPR_LIST (REG_EQUAL,
udiv_equal, REG_NOTES (insn)); udiv_equal, REG_NOTES (insn));
emit_jump (label3); emit_jump (label3);
emit_label (label1); emit_label (label1);
...@@ -4304,7 +4304,7 @@ ...@@ -4304,7 +4304,7 @@
emit_move_insn (operands[0], const1_rtx); emit_move_insn (operands[0], const1_rtx);
emit_label (label3); emit_label (label3);
} }
emit_move_insn (operands[0], operands[0]); emit_move_insn (operands[0], operands[0]);
DONE; DONE;
}") }")
...@@ -4344,19 +4344,19 @@ ...@@ -4344,19 +4344,19 @@
} }
else else
{ {
operands[2] = force_reg (SImode, operands[2]); operands[2] = force_reg (SImode, operands[2]);
operands[2] = make_safe_from (operands[2], operands[0]); operands[2] = make_safe_from (operands[2], operands[0]);
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2])); operands[2]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
insn = emit_move_insn (operands[0], insn = emit_move_insn (operands[0],
gen_highpart (SImode, operands[3])); gen_highpart (SImode, operands[3]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, gen_rtx_EXPR_LIST (REG_EQUAL,
umod_equal, REG_NOTES (insn)); umod_equal, REG_NOTES (insn));
} }
} }
...@@ -4366,12 +4366,12 @@ ...@@ -4366,12 +4366,12 @@
rtx label2 = gen_label_rtx (); rtx label2 = gen_label_rtx ();
rtx label3 = gen_label_rtx (); rtx label3 = gen_label_rtx ();
operands[1] = force_reg (SImode, operands[1]); operands[1] = force_reg (SImode, operands[1]);
operands[1] = make_safe_from (operands[1], operands[0]); operands[1] = make_safe_from (operands[1], operands[0]);
operands[2] = force_reg (SImode, operands[2]); operands[2] = force_reg (SImode, operands[2]);
operands[2] = make_safe_from (operands[2], operands[0]); operands[2] = make_safe_from (operands[2], operands[0]);
emit_move_insn(operands[0], operands[1]); emit_move_insn(operands[0], operands[1]);
emit_insn (gen_cmpsi (operands[2], operands[1])); emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3)); emit_jump_insn (gen_bgtu (label3));
emit_insn (gen_cmpsi (operands[2], const1_rtx)); emit_insn (gen_cmpsi (operands[2], const1_rtx));
...@@ -4383,11 +4383,11 @@ ...@@ -4383,11 +4383,11 @@
operands[2])); operands[2]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
insn = emit_move_insn (operands[0], insn = emit_move_insn (operands[0],
gen_highpart (SImode, operands[3])); gen_highpart (SImode, operands[3]));
REG_NOTES (insn) = REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, gen_rtx_EXPR_LIST (REG_EQUAL,
umod_equal, REG_NOTES (insn)); umod_equal, REG_NOTES (insn));
emit_jump (label3); emit_jump (label3);
emit_label (label1); emit_label (label1);
...@@ -5422,7 +5422,7 @@ ...@@ -5422,7 +5422,7 @@
; ;
; one_cmpldi2 instruction pattern(s). ; one_cmpldi2 instruction pattern(s).
; ;
(define_expand "one_cmpldi2" (define_expand "one_cmpldi2"
[(parallel [(parallel
[(set (match_operand:DI 0 "register_operand" "") [(set (match_operand:DI 0 "register_operand" "")
...@@ -5431,11 +5431,11 @@ ...@@ -5431,11 +5431,11 @@
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"TARGET_64BIT" "TARGET_64BIT"
"") "")
; ;
; one_cmplsi2 instruction pattern(s). ; one_cmplsi2 instruction pattern(s).
; ;
(define_expand "one_cmplsi2" (define_expand "one_cmplsi2"
[(parallel [(parallel
[(set (match_operand:SI 0 "register_operand" "") [(set (match_operand:SI 0 "register_operand" "")
...@@ -5444,11 +5444,11 @@ ...@@ -5444,11 +5444,11 @@
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"" ""
"") "")
; ;
; one_cmplhi2 instruction pattern(s). ; one_cmplhi2 instruction pattern(s).
; ;
(define_expand "one_cmplhi2" (define_expand "one_cmplhi2"
[(parallel [(parallel
[(set (match_operand:HI 0 "register_operand" "") [(set (match_operand:HI 0 "register_operand" "")
...@@ -5457,11 +5457,11 @@ ...@@ -5457,11 +5457,11 @@
(clobber (reg:CC 33))])] (clobber (reg:CC 33))])]
"" ""
"") "")
; ;
; one_cmplqi2 instruction pattern(s). ; one_cmplqi2 instruction pattern(s).
; ;
(define_expand "one_cmplqi2" (define_expand "one_cmplqi2"
[(parallel [(parallel
[(set (match_operand:QI 0 "register_operand" "") [(set (match_operand:QI 0 "register_operand" "")
...@@ -5529,7 +5529,7 @@ ...@@ -5529,7 +5529,7 @@
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
sldl\\t%0,%c2 sldl\\t%0,%c2
sldl\\t%0,0(%2)" sldl\\t%0,0(%2)"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -5567,7 +5567,7 @@ ...@@ -5567,7 +5567,7 @@
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"@ "@
srda\\t%0,%c2 srda\\t%0,%c2
srda\\t%0,0(%2)" srda\\t%0,0(%2)"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -5580,7 +5580,7 @@ ...@@ -5580,7 +5580,7 @@
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"@ "@
srda\\t%0,%c2 srda\\t%0,%c2
srda\\t%0,0(%2)" srda\\t%0,0(%2)"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -5592,10 +5592,10 @@ ...@@ -5592,10 +5592,10 @@
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
srda\\t%0,%c2 srda\\t%0,%c2
srda\\t%0,0(%2)" srda\\t%0,0(%2)"
[(set_attr "op_type" "RS") [(set_attr "op_type" "RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
(define_insn "*ashrdi3_cc_64" (define_insn "*ashrdi3_cc_64"
[(set (reg 33) [(set (reg 33)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
...@@ -5718,7 +5718,7 @@ ...@@ -5718,7 +5718,7 @@
"!TARGET_64BIT" "!TARGET_64BIT"
"@ "@
srdl\\t%0,%c2 srdl\\t%0,%c2
srdl\\t%0,0(%2)" srdl\\t%0,0(%2)"
[(set_attr "op_type" "RS,RS") [(set_attr "op_type" "RS,RS")
(set_attr "atype" "reg")]) (set_attr "atype" "reg")])
...@@ -5922,7 +5922,7 @@ ...@@ -5922,7 +5922,7 @@
(define_insn "cjump" (define_insn "cjump"
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))]
...@@ -5960,7 +5960,7 @@ ...@@ -5960,7 +5960,7 @@
else else
return \"b%C1\\t%a0\"; return \"b%C1\\t%a0\";
}" }"
[(set (attr "op_type") [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "") (if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "branch") (set_attr "type" "branch")
...@@ -5975,11 +5975,11 @@ ...@@ -5975,11 +5975,11 @@
[(set (pc) [(set (pc)
(if_then_else (if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(pc) (pc)
(label_ref (match_operand 0 "" ""))))] (label_ref (match_operand 0 "" ""))))]
"" ""
"* "*
{ {
if (get_attr_length (insn) == 4) if (get_attr_length (insn) == 4)
return \"j%D1\\t%l0\"; return \"j%D1\\t%l0\";
else if (TARGET_64BIT) else if (TARGET_64BIT)
...@@ -6011,7 +6011,7 @@ ...@@ -6011,7 +6011,7 @@
else else
return \"b%D1\\t%a0\"; return \"b%D1\\t%a0\";
}" }"
[(set (attr "op_type") [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "") (if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "branch") (set_attr "type" "branch")
...@@ -6038,10 +6038,10 @@ ...@@ -6038,10 +6038,10 @@
{ {
enum machine_mode ccmode; enum machine_mode ccmode;
if (operands[1] != const0_rtx) FAIL; if (operands[1] != const0_rtx) FAIL;
ccmode = s390_select_ccmode (GET_CODE (operands[0]), ccmode = s390_select_ccmode (GET_CODE (operands[0]),
s390_compare_op0, s390_compare_op1); s390_compare_op0, s390_compare_op1);
operands[2] = gen_rtx_REG (ccmode, 33); operands[2] = gen_rtx_REG (ccmode, 33);
operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
}") }")
...@@ -6059,7 +6059,7 @@ ...@@ -6059,7 +6059,7 @@
;; ;;
;; This is all complicated by the fact that since this is a jump insn ;; This is all complicated by the fact that since this is a jump insn
;; we must handle our own output reloads. ;; we must handle our own output reloads.
(define_expand "doloop_end" (define_expand "doloop_end"
[(use (match_operand 0 "" "")) ; loop pseudo [(use (match_operand 0 "" "")) ; loop pseudo
(use (match_operand 1 "" "")) ; iterations; zero if unknown (use (match_operand 1 "" "")) ; iterations; zero if unknown
...@@ -6129,7 +6129,7 @@ ...@@ -6129,7 +6129,7 @@
else else
return \"bct\\t%1,%a0\"; return \"bct\\t%1,%a0\";
}" }"
[(set (attr "op_type") [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "") (if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "branch") (set_attr "type" "branch")
...@@ -6205,7 +6205,7 @@ ...@@ -6205,7 +6205,7 @@
else else
return \"bctg\\t%1,%a0\"; return \"bctg\\t%1,%a0\";
}" }"
[(set (attr "op_type") [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "") (if_then_else (match_operand 0 "register_operand" "")
(const_string "RRE") (const_string "RXE"))) (const_string "RRE") (const_string "RXE")))
(set_attr "type" "branch") (set_attr "type" "branch")
...@@ -6279,7 +6279,7 @@ ...@@ -6279,7 +6279,7 @@
else else
return \"b\\t%a0\"; return \"b\\t%a0\";
}" }"
[(set (attr "op_type") [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "") (if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "branch") (set_attr "type" "branch")
...@@ -6300,7 +6300,7 @@ ...@@ -6300,7 +6300,7 @@
else else
return \"b\\t%a0\"; return \"b\\t%a0\";
}" }"
[(set (attr "op_type") [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "") (if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX"))) (const_string "RR") (const_string "RX")))
(set_attr "type" "branch") (set_attr "type" "branch")
...@@ -6422,7 +6422,7 @@ ...@@ -6422,7 +6422,7 @@
sym = gen_rtx_CONST (Pmode, sym); sym = gen_rtx_CONST (Pmode, sym);
} }
/* Unless we can use the bras(l) insn, force the /* Unless we can use the bras(l) insn, force the
routine address into a register. */ routine address into a register. */
if (!TARGET_SMALL_EXEC && !TARGET_64BIT) if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
{ {
...@@ -6532,7 +6532,7 @@ ...@@ -6532,7 +6532,7 @@
sym = gen_rtx_CONST (Pmode, sym); sym = gen_rtx_CONST (Pmode, sym);
} }
/* Unless we can use the bras(l) insn, force the /* Unless we can use the bras(l) insn, force the
routine address into a register. */ routine address into a register. */
if (!TARGET_SMALL_EXEC && !TARGET_64BIT) if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
{ {
...@@ -6667,7 +6667,7 @@ ...@@ -6667,7 +6667,7 @@
sar\\t%%a0,%0 sar\\t%%a0,%0
lam\\t%%a0,%%a0,%0" lam\\t%%a0,%%a0,%0"
[(set_attr "op_type" "RRE,RS")]) [(set_attr "op_type" "RRE,RS")])
(define_insn "*tls_load_64" (define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d") [(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m") (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
...@@ -6704,7 +6704,7 @@ ...@@ -6704,7 +6704,7 @@
sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
sym = gen_rtx_CONST (Pmode, sym); sym = gen_rtx_CONST (Pmode, sym);
/* Unless we can use the bras(l) insn, force the /* Unless we can use the bras(l) insn, force the
routine address into a register. */ routine address into a register. */
if (!TARGET_SMALL_EXEC && !TARGET_64BIT) if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
{ {
...@@ -6828,7 +6828,7 @@ ...@@ -6828,7 +6828,7 @@
rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
rtx chain = gen_rtx (MEM, Pmode, stack); rtx chain = gen_rtx (MEM, Pmode, stack);
rtx temp = gen_reg_rtx (Pmode); rtx temp = gen_reg_rtx (Pmode);
emit_move_insn (temp, chain); emit_move_insn (temp, chain);
if (TARGET_64BIT) if (TARGET_64BIT)
...@@ -6838,7 +6838,7 @@ ...@@ -6838,7 +6838,7 @@
emit_move_insn (chain, temp); emit_move_insn (chain, temp);
emit_move_insn (operands[0], virtual_stack_dynamic_rtx); emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE; DONE;
}") }")
...@@ -6980,7 +6980,7 @@ ...@@ -6980,7 +6980,7 @@
; ;
(define_insn "consttable_qi" (define_insn "consttable_qi"
[(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")]
UNSPECV_POOL_QI)] UNSPECV_POOL_QI)]
"" ""
{ {
...@@ -6991,7 +6991,7 @@ ...@@ -6991,7 +6991,7 @@
(set_attr "length" "1")]) (set_attr "length" "1")])
(define_insn "consttable_hi" (define_insn "consttable_hi"
[(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")]
UNSPECV_POOL_HI)] UNSPECV_POOL_HI)]
"" ""
{ {
...@@ -7002,7 +7002,7 @@ ...@@ -7002,7 +7002,7 @@
(set_attr "length" "2")]) (set_attr "length" "2")])
(define_insn "consttable_si" (define_insn "consttable_si"
[(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")]
UNSPECV_POOL_SI)] UNSPECV_POOL_SI)]
"" ""
".long\t%0" ".long\t%0"
...@@ -7010,7 +7010,7 @@ ...@@ -7010,7 +7010,7 @@
(set_attr "length" "4")]) (set_attr "length" "4")])
(define_insn "consttable_di" (define_insn "consttable_di"
[(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")]
UNSPECV_POOL_DI)] UNSPECV_POOL_DI)]
"" ""
".quad\t%0" ".quad\t%0"
...@@ -7018,7 +7018,7 @@ ...@@ -7018,7 +7018,7 @@
(set_attr "length" "8")]) (set_attr "length" "8")])
(define_insn "consttable_ti" (define_insn "consttable_ti"
[(unspec_volatile [(match_operand:TI 0 "consttable_operand" "X")] [(unspec_volatile [(match_operand:TI 0 "consttable_operand" "X")]
UNSPECV_POOL_TI)] UNSPECV_POOL_TI)]
"" ""
{ {
...@@ -7029,7 +7029,7 @@ ...@@ -7029,7 +7029,7 @@
(set_attr "length" "16")]) (set_attr "length" "16")])
(define_insn "consttable_sf" (define_insn "consttable_sf"
[(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")]
UNSPECV_POOL_SF)] UNSPECV_POOL_SF)]
"" ""
{ {
...@@ -7144,7 +7144,7 @@ ...@@ -7144,7 +7144,7 @@
"!TARGET_64BIT" "!TARGET_64BIT"
"br\\t%0" "br\\t%0"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "jsr") (set_attr "type" "jsr")
(set_attr "atype" "agen")]) (set_attr "atype" "agen")])
(define_insn "*return_di" (define_insn "*return_di"
...@@ -7153,21 +7153,21 @@ ...@@ -7153,21 +7153,21 @@
"TARGET_64BIT" "TARGET_64BIT"
"br\\t%0" "br\\t%0"
[(set_attr "op_type" "RR") [(set_attr "op_type" "RR")
(set_attr "type" "jsr") (set_attr "type" "jsr")
(set_attr "atype" "agen")]) (set_attr "atype" "agen")])
(define_insn "literal_pool_31" (define_insn "literal_pool_31"
[(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL) [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)
(set (match_operand:SI 0 "register_operand" "=a") (set (match_operand:SI 0 "register_operand" "=a")
(label_ref (match_operand 1 "" ""))) (label_ref (match_operand 1 "" "")))
(use (label_ref (match_operand 2 "" "")))] (use (label_ref (match_operand 2 "" "")))]
"" ""
{ {
if (s390_nr_constants) if (s390_nr_constants)
{ {
output_asm_insn ("bras\\t%0,%2", operands); output_asm_insn ("bras\\t%0,%2", operands);
s390_output_constant_pool (operands[1], operands[2]); s390_output_constant_pool (operands[1], operands[2]);
} }
else if (flag_pic) else if (flag_pic)
{ {
/* We need the anchor label in any case. */ /* We need the anchor label in any case. */
...@@ -7175,25 +7175,46 @@ ...@@ -7175,25 +7175,46 @@
CODE_LABEL_NUMBER (operands[1])); CODE_LABEL_NUMBER (operands[1]));
} }
return ""; return "";
} }
[(set_attr "op_type" "NN") [(set_attr "op_type" "NN")
(set_attr "type" "larl")]) (set_attr "type" "larl")])
(define_insn "literal_pool_64" (define_insn "literal_pool_64"
[(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL) [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)
(set (match_operand:DI 0 "register_operand" "=a") (set (match_operand:DI 0 "register_operand" "=a")
(label_ref (match_operand 1 "" ""))) (label_ref (match_operand 1 "" "")))
(use (label_ref (match_operand 2 "" "")))] (use (label_ref (match_operand 2 "" "")))]
"" ""
{ {
if (s390_nr_constants) if (s390_nr_constants)
{ {
output_asm_insn ("larl\\t%0,%1", operands); output_asm_insn ("larl\\t%0,%1", operands);
s390_output_constant_pool (operands[1], operands[2]); s390_output_constant_pool (operands[1], operands[2]);
} }
return ""; return "";
} }
[(set_attr "op_type" "NN") [(set_attr "op_type" "NN")
(set_attr "type" "larl")]) (set_attr "type" "larl")])
;; Instruction definition to extend a 31-bit pointer into a 64-bit
;; pointer. This is used for compatability.
(define_expand "ptr_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:SI 1 "register_operand" "r"))]
""
"
{
/*
emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
emit_insn (gen_anddi3 (operands[0], operands[0], GEN_INT (0x7fffffff)));
*/
emit_insn (gen_anddi3 (operands[0],
gen_lowpart (DImode, operands[1]),
GEN_INT (0x7fffffff)));
DONE;
}")
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