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riscv-gcc-1
Commit c69899f0 by Claudiu Zissulescu Committed by Claudiu Zissulescu
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[ARC] Add and refurbish the builtins related functions. 

gcc/
2015-12-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/builtins.def: New file.
	* config/arc/arc.c (arc_init_simd_builtins): Remove.
	(arc_builtins): Likewise.
	(TARGET_BUILTIN_DECL): Define.
	(arc_builtin_id): New enum.
	(arc_builtin_description): New structure.
	(arc_bdesc): New variable.
	(arc_tolower): New function.
	(def_mbuiltin): Remove.
	(arc_builtin_decl): New function.
	(arc_expand_builtin_aligned ): Likewise.
	(apply_GEN_FCN): Likewise.
	(arc_init_builtins): Refurbish.
	(arc_expand_builtin): Likewise.
	(simd_insn_args_type): Remove.
	(builtin_description): Likewise
	(arc_simd_builtin_desc_list): Likewise.
	(arc_expand_simd_builtin): Likewise.
	(arc_process_double_reg_moves): Use the new builtin name format.
	* config/arc/arc.md (unspec): New builtin function UNSPEC codes.
	(vunspec): New builtin function VUNSPEC codes.
	(UNSPEC_SWAP, UNSPEC_MUL64, UNSPEC_MULU64, UNSPEC_DIVAW)
	(UNSPEC_DIRECT, UNSPEC_LP, UNSPEC_CASESI, VUNSPEC_RTIE)
	(VUNSPEC_SYNC, VUNSPEC_BRK, VUNSPEC_FLAG, VUNSPEC_SLEEP)
	(VUNSPEC_SWI, VUNSPEC_CORE_READ, VUNSPEC_CORE_WRITE, VUNSPEC_LR)
	(VUNSPEC_SR, VUNSPEC_TRAP_S, VUNSPEC_UNIMP_S, VUNSPEC_NOP)
	(UNSPEC_ARC_MEMBAR,VUNSPEC_ARC_CAS, VUNSPEC_ARC_LL)
	(VUNSPEC_ARC_SC, VUNSPEC_ARC_EX, VUNSPEC_DEXCL)
	(VUNSPEC_DEXCL_NORES, VUNSPEC_LR_HIGH): Remove.
	(mul64, mulu64): Remove patterns.
	(store_direct, *movdf_insn_nolrsr, casesi, casesi_load)
	(casesi_compact_jump, nopv, swap, divaw, flag, brk, rtie, sync)
	(swi, sleep, core_read, core_write, lr, sr, trap_s, unimp_s)
	(doloop_begin_i): Use new builtin function code naming.
	(kflag, clri, ffs, ffs_f, ffssi2, fls, seti): New patterns.
	* config/arc/builtins.def: New file.
	* config/arc/fpx.md: Use new builtin function code naming.
	* config/arc/simdext.md: New SIMD builtin function UNSPEC
	codes. Use them in the SIMD patterns.

gcc/testsuite
2015-12-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/builtin_general.c: New test.
	* gcc.target/arc/builtin_simd.c: Likewise.
	* gcc.target/arc/builtin_special.c: Likewise.

From-SVN: r231874
parent f8e66330
Showing with 406 additions and 110 deletions
gcc/ChangeLog
2015-12-21 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/builtins.def: New file.
* config/arc/arc.c (arc_init_simd_builtins): Remove.
(arc_builtins): Likewise.
(TARGET_BUILTIN_DECL): Define.
(arc_builtin_id): New enum.
(arc_builtin_description): New structure.
(arc_bdesc): New variable.
(arc_tolower): New function.
(def_mbuiltin): Remove.
(arc_builtin_decl): New function.
(arc_expand_builtin_aligned ): Likewise.
(apply_GEN_FCN): Likewise.
(arc_init_builtins): Refurbish.
(arc_expand_builtin): Likewise.
(simd_insn_args_type): Remove.
(builtin_description): Likewise
(arc_simd_builtin_desc_list): Likewise.
(arc_expand_simd_builtin): Likewise.
(arc_process_double_reg_moves): Use the new builtin name format.
* config/arc/arc.md (unspec): New builtin function UNSPEC codes.
(vunspec): New builtin function VUNSPEC codes.
(UNSPEC_SWAP, UNSPEC_MUL64, UNSPEC_MULU64, UNSPEC_DIVAW)
(UNSPEC_DIRECT, UNSPEC_LP, UNSPEC_CASESI, VUNSPEC_RTIE)
(VUNSPEC_SYNC, VUNSPEC_BRK, VUNSPEC_FLAG, VUNSPEC_SLEEP)
(VUNSPEC_SWI, VUNSPEC_CORE_READ, VUNSPEC_CORE_WRITE, VUNSPEC_LR)
(VUNSPEC_SR, VUNSPEC_TRAP_S, VUNSPEC_UNIMP_S, VUNSPEC_NOP)
(UNSPEC_ARC_MEMBAR,VUNSPEC_ARC_CAS, VUNSPEC_ARC_LL)
(VUNSPEC_ARC_SC, VUNSPEC_ARC_EX, VUNSPEC_DEXCL)
(VUNSPEC_DEXCL_NORES, VUNSPEC_LR_HIGH): Remove.
(mul64, mulu64): Remove patterns.
(store_direct, *movdf_insn_nolrsr, casesi, casesi_load)
(casesi_compact_jump, nopv, swap, divaw, flag, brk, rtie, sync)
(swi, sleep, core_read, core_write, lr, sr, trap_s, unimp_s)
(doloop_begin_i): Use new builtin function code naming.
(kflag, clri, ffs, ffs_f, ffssi2, fls, seti): New patterns.
* config/arc/builtins.def: New file.
* config/arc/fpx.md: Use new builtin function code naming.
* config/arc/simdext.md: New SIMD builtin function UNSPEC
codes. Use them in the SIMD patterns.
2015-12-21 Sujoy Saraswati <sujoy.saraswati@hpe.com>
PR tree-optimization/61441
gcc/config/arc/fpx.md
......@@ -151,7 +151,7 @@
;; op0_reg = D1_reg.low
(define_insn "*lr_double_lower"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR ))]
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_ARC_LR ))]
"TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR"
"lr %0, [%1l] ; *lr_double_lower"
[(set_attr "length" "8")
......@@ -160,7 +160,8 @@
(define_insn "*lr_double_higher"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR_HIGH ))]
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")]
VUNSPEC_ARC_LR_HIGH ))]
"TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR"
"lr %0, [%1h] ; *lr_double_higher"
[(set_attr "length" "8")
......@@ -174,7 +175,7 @@
(match_operand:DF 1 "arc_double_register_operand" "D")
(match_operand:SI 2 "shouldbe_register_operand" "r") ; r1
(match_operand:SI 3 "shouldbe_register_operand" "r") ; r0
] VUNSPEC_DEXCL ))
] VUNSPEC_ARC_DEXCL ))
]
"TARGET_DPFP"
"dexcl%F1 %0, %2, %3"
......@@ -188,7 +189,7 @@
(match_operand:DF 0 "arc_double_register_operand" "D")
(match_operand:SI 1 "shouldbe_register_operand" "r") ; r1
(match_operand:SI 2 "shouldbe_register_operand" "r") ; r0
] VUNSPEC_DEXCL_NORES )
] VUNSPEC_ARC_DEXCL_NORES )
]
"TARGET_DPFP"
"dexcl%F0 0, %1, %2"
......@@ -199,7 +200,7 @@
;; dexcl a,b,c pattern generated by the peephole2 above
(define_insn "*dexcl_3op_peep2_insn_lr"
[(parallel [(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_LR ))
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_ARC_LR ))
(set (match_dup 1) (match_operand:DF 2 "register_operand" "r"))]
)
]
......@@ -413,7 +414,7 @@
;; (parallel [
;; ;; (set (subreg:SI (match_dup 5) 0)
;; (set (match_dup 7)
;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR ))
;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR ))
;; (set (match_dup 0) (match_dup 6))]
;; )
;; ]
......@@ -472,7 +473,7 @@
(parallel [
;; (set (subreg:SI (match_dup 7) 0)
(set (match_dup 9)
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR ))
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR ))
(set (match_dup 0) (match_dup 8))]
)
]
......@@ -522,7 +523,7 @@
;; (match_dup 3)]))])
;; ; (set (subreg:SI (match_dup 5) 0)
;; (set (match_dup 6)
;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR ))
;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR ))
;; ]
;; "operands[6] = simplify_gen_subreg(SImode,operands[5],DFmode,0);"
;; )
......@@ -572,7 +573,7 @@
(match_dup 3)]))])
; (set (subreg:SI (match_dup 7) 0)
(set (match_dup 8)
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR ))
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR ))
]
"operands[8] = simplify_gen_subreg(SImode,operands[7],DFmode,0);"
)
......
gcc/config/arc/simdext.md
......@@ -17,119 +17,117 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_constants
[
(define_c_enum "unspec" [
;; Va, Vb, Vc builtins
(UNSPEC_ARC_SIMD_VADDAW 1000)
(UNSPEC_ARC_SIMD_VADDW 1001)
(UNSPEC_ARC_SIMD_VAVB 1002)
(UNSPEC_ARC_SIMD_VAVRB 1003)
(UNSPEC_ARC_SIMD_VDIFAW 1004)
(UNSPEC_ARC_SIMD_VDIFW 1005)
(UNSPEC_ARC_SIMD_VMAXAW 1006)
(UNSPEC_ARC_SIMD_VMAXW 1007)
(UNSPEC_ARC_SIMD_VMINAW 1008)
(UNSPEC_ARC_SIMD_VMINW 1009)
(UNSPEC_ARC_SIMD_VMULAW 1010)
(UNSPEC_ARC_SIMD_VMULFAW 1011)
(UNSPEC_ARC_SIMD_VMULFW 1012)
(UNSPEC_ARC_SIMD_VMULW 1013)
(UNSPEC_ARC_SIMD_VSUBAW 1014)
(UNSPEC_ARC_SIMD_VSUBW 1015)
(UNSPEC_ARC_SIMD_VSUMMW 1016)
(UNSPEC_ARC_SIMD_VAND 1017)
(UNSPEC_ARC_SIMD_VANDAW 1018)
(UNSPEC_ARC_SIMD_VBIC 1019)
(UNSPEC_ARC_SIMD_VBICAW 1020)
(UNSPEC_ARC_SIMD_VOR 1021)
(UNSPEC_ARC_SIMD_VXOR 1022)
(UNSPEC_ARC_SIMD_VXORAW 1023)
(UNSPEC_ARC_SIMD_VEQW 1024)
(UNSPEC_ARC_SIMD_VLEW 1025)
(UNSPEC_ARC_SIMD_VLTW 1026)
(UNSPEC_ARC_SIMD_VNEW 1027)
(UNSPEC_ARC_SIMD_VMR1AW 1028)
(UNSPEC_ARC_SIMD_VMR1W 1029)
(UNSPEC_ARC_SIMD_VMR2AW 1030)
(UNSPEC_ARC_SIMD_VMR2W 1031)
(UNSPEC_ARC_SIMD_VMR3AW 1032)
(UNSPEC_ARC_SIMD_VMR3W 1033)
(UNSPEC_ARC_SIMD_VMR4AW 1034)
(UNSPEC_ARC_SIMD_VMR4W 1035)
(UNSPEC_ARC_SIMD_VMR5AW 1036)
(UNSPEC_ARC_SIMD_VMR5W 1037)
(UNSPEC_ARC_SIMD_VMR6AW 1038)
(UNSPEC_ARC_SIMD_VMR6W 1039)
(UNSPEC_ARC_SIMD_VMR7AW 1040)
(UNSPEC_ARC_SIMD_VMR7W 1041)
(UNSPEC_ARC_SIMD_VMRB 1042)
(UNSPEC_ARC_SIMD_VH264F 1043)
(UNSPEC_ARC_SIMD_VH264FT 1044)
(UNSPEC_ARC_SIMD_VH264FW 1045)
(UNSPEC_ARC_SIMD_VVC1F 1046)
(UNSPEC_ARC_SIMD_VVC1FT 1047)
UNSPEC_ARC_SIMD_VADDAW
UNSPEC_ARC_SIMD_VADDW
UNSPEC_ARC_SIMD_VAVB
UNSPEC_ARC_SIMD_VAVRB
UNSPEC_ARC_SIMD_VDIFAW
UNSPEC_ARC_SIMD_VDIFW
UNSPEC_ARC_SIMD_VMAXAW
UNSPEC_ARC_SIMD_VMAXW
UNSPEC_ARC_SIMD_VMINAW
UNSPEC_ARC_SIMD_VMINW
UNSPEC_ARC_SIMD_VMULAW
UNSPEC_ARC_SIMD_VMULFAW
UNSPEC_ARC_SIMD_VMULFW
UNSPEC_ARC_SIMD_VMULW
UNSPEC_ARC_SIMD_VSUBAW
UNSPEC_ARC_SIMD_VSUBW
UNSPEC_ARC_SIMD_VSUMMW
UNSPEC_ARC_SIMD_VAND
UNSPEC_ARC_SIMD_VANDAW
UNSPEC_ARC_SIMD_VBIC
UNSPEC_ARC_SIMD_VBICAW
UNSPEC_ARC_SIMD_VOR
UNSPEC_ARC_SIMD_VXOR
UNSPEC_ARC_SIMD_VXORAW
UNSPEC_ARC_SIMD_VEQW
UNSPEC_ARC_SIMD_VLEW
UNSPEC_ARC_SIMD_VLTW
UNSPEC_ARC_SIMD_VNEW
UNSPEC_ARC_SIMD_VMR1AW
UNSPEC_ARC_SIMD_VMR1W
UNSPEC_ARC_SIMD_VMR2AW
UNSPEC_ARC_SIMD_VMR2W
UNSPEC_ARC_SIMD_VMR3AW
UNSPEC_ARC_SIMD_VMR3W
UNSPEC_ARC_SIMD_VMR4AW
UNSPEC_ARC_SIMD_VMR4W
UNSPEC_ARC_SIMD_VMR5AW
UNSPEC_ARC_SIMD_VMR5W
UNSPEC_ARC_SIMD_VMR6AW
UNSPEC_ARC_SIMD_VMR6W
UNSPEC_ARC_SIMD_VMR7AW
UNSPEC_ARC_SIMD_VMR7W
UNSPEC_ARC_SIMD_VMRB
UNSPEC_ARC_SIMD_VH264F
UNSPEC_ARC_SIMD_VH264FT
UNSPEC_ARC_SIMD_VH264FW
UNSPEC_ARC_SIMD_VVC1F
UNSPEC_ARC_SIMD_VVC1FT
;; Va, Vb, rc/limm builtins
(UNSPEC_ARC_SIMD_VBADDW 1050)
(UNSPEC_ARC_SIMD_VBMAXW 1051)
(UNSPEC_ARC_SIMD_VBMINW 1052)
(UNSPEC_ARC_SIMD_VBMULAW 1053)
(UNSPEC_ARC_SIMD_VBMULFW 1054)
(UNSPEC_ARC_SIMD_VBMULW 1055)
(UNSPEC_ARC_SIMD_VBRSUBW 1056)
(UNSPEC_ARC_SIMD_VBSUBW 1057)
UNSPEC_ARC_SIMD_VBADDW
UNSPEC_ARC_SIMD_VBMAXW
UNSPEC_ARC_SIMD_VBMINW
UNSPEC_ARC_SIMD_VBMULAW
UNSPEC_ARC_SIMD_VBMULFW
UNSPEC_ARC_SIMD_VBMULW
UNSPEC_ARC_SIMD_VBRSUBW
UNSPEC_ARC_SIMD_VBSUBW
;; Va, Vb, Ic builtins
(UNSPEC_ARC_SIMD_VASRW 1060)
(UNSPEC_ARC_SIMD_VSR8 1061)
(UNSPEC_ARC_SIMD_VSR8AW 1062)
UNSPEC_ARC_SIMD_VASRW
UNSPEC_ARC_SIMD_VSR8
UNSPEC_ARC_SIMD_VSR8AW
;; Va, Vb, Ic builtins
(UNSPEC_ARC_SIMD_VASRRWi 1065)
(UNSPEC_ARC_SIMD_VASRSRWi 1066)
(UNSPEC_ARC_SIMD_VASRWi 1067)
(UNSPEC_ARC_SIMD_VASRPWBi 1068)
(UNSPEC_ARC_SIMD_VASRRPWBi 1069)
(UNSPEC_ARC_SIMD_VSR8AWi 1070)
(UNSPEC_ARC_SIMD_VSR8i 1071)
UNSPEC_ARC_SIMD_VASRRWi
UNSPEC_ARC_SIMD_VASRSRWi
UNSPEC_ARC_SIMD_VASRWi
UNSPEC_ARC_SIMD_VASRPWBi
UNSPEC_ARC_SIMD_VASRRPWBi
UNSPEC_ARC_SIMD_VSR8AWi
UNSPEC_ARC_SIMD_VSR8i
;; Va, Vb, u8 (simm) builtins
(UNSPEC_ARC_SIMD_VMVAW 1075)
(UNSPEC_ARC_SIMD_VMVW 1076)
(UNSPEC_ARC_SIMD_VMVZW 1077)
(UNSPEC_ARC_SIMD_VD6TAPF 1078)
UNSPEC_ARC_SIMD_VMVAW
UNSPEC_ARC_SIMD_VMVW
UNSPEC_ARC_SIMD_VMVZW
UNSPEC_ARC_SIMD_VD6TAPF
;; Va, rlimm, u8 (simm) builtins
(UNSPEC_ARC_SIMD_VMOVAW 1080)
(UNSPEC_ARC_SIMD_VMOVW 1081)
(UNSPEC_ARC_SIMD_VMOVZW 1082)
UNSPEC_ARC_SIMD_VMOVAW
UNSPEC_ARC_SIMD_VMOVW
UNSPEC_ARC_SIMD_VMOVZW
;; Va, Vb builtins
(UNSPEC_ARC_SIMD_VABSAW 1085)
(UNSPEC_ARC_SIMD_VABSW 1086)
(UNSPEC_ARC_SIMD_VADDSUW 1087)
(UNSPEC_ARC_SIMD_VSIGNW 1088)
(UNSPEC_ARC_SIMD_VEXCH1 1089)
(UNSPEC_ARC_SIMD_VEXCH2 1090)
(UNSPEC_ARC_SIMD_VEXCH4 1091)
(UNSPEC_ARC_SIMD_VUPBAW 1092)
(UNSPEC_ARC_SIMD_VUPBW 1093)
(UNSPEC_ARC_SIMD_VUPSBAW 1094)
(UNSPEC_ARC_SIMD_VUPSBW 1095)
(UNSPEC_ARC_SIMD_VDIRUN 1100)
(UNSPEC_ARC_SIMD_VDORUN 1101)
(UNSPEC_ARC_SIMD_VDIWR 1102)
(UNSPEC_ARC_SIMD_VDOWR 1103)
(UNSPEC_ARC_SIMD_VREC 1105)
(UNSPEC_ARC_SIMD_VRUN 1106)
(UNSPEC_ARC_SIMD_VRECRUN 1107)
(UNSPEC_ARC_SIMD_VENDREC 1108)
(UNSPEC_ARC_SIMD_VCAST 1200)
(UNSPEC_ARC_SIMD_VINTI 1201)
]
)
UNSPEC_ARC_SIMD_VABSAW
UNSPEC_ARC_SIMD_VABSW
UNSPEC_ARC_SIMD_VADDSUW
UNSPEC_ARC_SIMD_VSIGNW
UNSPEC_ARC_SIMD_VEXCH1
UNSPEC_ARC_SIMD_VEXCH2
UNSPEC_ARC_SIMD_VEXCH4
UNSPEC_ARC_SIMD_VUPBAW
UNSPEC_ARC_SIMD_VUPBW
UNSPEC_ARC_SIMD_VUPSBAW
UNSPEC_ARC_SIMD_VUPSBW
UNSPEC_ARC_SIMD_VDIRUN
UNSPEC_ARC_SIMD_VDORUN
UNSPEC_ARC_SIMD_VDIWR
UNSPEC_ARC_SIMD_VDOWR
UNSPEC_ARC_SIMD_VREC
UNSPEC_ARC_SIMD_VRUN
UNSPEC_ARC_SIMD_VRECRUN
UNSPEC_ARC_SIMD_VENDREC
UNSPEC_ARC_SIMD_VCAST
UNSPEC_ARC_SIMD_VINTI
])
;; Scheduler descriptions for the simd instructions
(define_insn_reservation "simd_lat_0_insn" 1
......
gcc/testsuite/ChangeLog
2015-12-21 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/builtin_general.c: New test.
* gcc.target/arc/builtin_simd.c: Likewise.
* gcc.target/arc/builtin_special.c: Likewise.
2015-12-20 Jeff Law <law@redhat.com>
PR tree-optimization/64910
......
gcc/testsuite/gcc.target/arc/builtin_general.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration" } */
#define NORET1OP(name, op1type) \
void test_ ## name ## _0 (op1type a) \
{ \
__builtin_arc_ ## name (a); \
} \
void test_ ## name ## _1 (void) \
{ \
__builtin_arc_ ## name (0x10); \
}
#define RET1OP(name, rettype, op1type) \
rettype test_ ## name ## _0 (op1type a) \
{ \
return __builtin_arc_ ## name (a); \
} \
rettype test_ ## name ## _1 (void) \
{ \
return __builtin_arc_ ## name (0x10); \
}
NORET1OP (flag, unsigned int)
#if defined (__EM__) || defined (__HS__)
NORET1OP (kflag, unsigned int)
NORET1OP (seti, int)
#endif
#ifdef __ARC_NORM__
RET1OP (norm, int, int)
RET1OP (normw, int, short)
#endif
gcc/testsuite/gcc.target/arc/builtin_simd.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -mARC700 -msimd" } */
#define STEST1(name, rettype, op1) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1); \
}
#define STEST2(name, rettype, op1, op2) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1, op2); \
}
#define STEST3(name, rettype, op1, op2, op3) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1, op2, op3); \
}
#define STEST4(name, rettype, op1, op2, op3, op4) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1, op2, op3, op4); \
}
typedef short v8hi __attribute__ ((vector_size (16)));
v8hi Va;
v8hi Vb;
v8hi Vc;
#define rlimm 0xf3eec0fe
#define Ic 0x02
#define Ib 0x02
#define u3 0x02
#define u6 0x1F
#define u8 0xB0
STEST2 ( vaddaw, v8hi, Vb, Vc)
STEST2 ( vaddw, v8hi, Vb, Vc)
STEST2 ( vavb, v8hi, Vb, Vc)
STEST2 ( vavrb, v8hi, Vb, Vc)
STEST2 ( vdifaw, v8hi, Vb, Vc)
STEST2 ( vdifw, v8hi, Vb, Vc)
STEST2 ( vmaxaw, v8hi, Vb, Vc)
STEST2 ( vmaxw, v8hi, Vb, Vc)
STEST2 ( vminaw, v8hi, Vb, Vc)
STEST2 ( vminw, v8hi, Vb, Vc)
STEST2 ( vmulaw, v8hi, Vb, Vc)
STEST2 (vmulfaw, v8hi, Vb, Vc)
STEST2 ( vmulfw, v8hi, Vb, Vc)
STEST2 ( vmulw, v8hi, Vb, Vc)
STEST2 ( vsubaw, v8hi, Vb, Vc)
STEST2 ( vsubw, v8hi, Vb, Vc)
STEST2 ( vsummw, v8hi, Vb, Vc)
STEST2 ( vand, v8hi, Vb, Vc)
STEST2 ( vandaw, v8hi, Vb, Vc)
STEST2 ( vbic, v8hi, Vb, Vc)
STEST2 ( vbicaw, v8hi, Vb, Vc)
STEST2 ( vor, v8hi, Vb, Vc)
STEST2 ( vxor, v8hi, Vb, Vc)
STEST2 ( vxoraw, v8hi, Vb, Vc)
STEST2 ( veqw, v8hi, Vb, Vc)
STEST2 ( vlew, v8hi, Vb, Vc)
STEST2 ( vltw, v8hi, Vb, Vc)
STEST2 ( vnew, v8hi, Vb, Vc)
STEST2 ( vmr1aw, v8hi, Vb, Vc)
STEST2 ( vmr1w, v8hi, Vb, Vc)
STEST2 ( vmr2aw, v8hi, Vb, Vc)
STEST2 ( vmr2w, v8hi, Vb, Vc)
STEST2 ( vmr3aw, v8hi, Vb, Vc)
STEST2 ( vmr3w, v8hi, Vb, Vc)
STEST2 ( vmr4aw, v8hi, Vb, Vc)
STEST2 ( vmr4w, v8hi, Vb, Vc)
STEST2 ( vmr5aw, v8hi, Vb, Vc)
STEST2 ( vmr5w, v8hi, Vb, Vc)
STEST2 ( vmr6aw, v8hi, Vb, Vc)
STEST2 ( vmr6w, v8hi, Vb, Vc)
STEST2 ( vmr7aw, v8hi, Vb, Vc)
STEST2 ( vmr7w, v8hi, Vb, Vc)
STEST2 ( vmrb, v8hi, Vb, Vc)
STEST2 ( vh264f, v8hi, Vb, Vc)
STEST2 (vh264ft, v8hi, Vb, Vc)
STEST2 (vh264fw, v8hi, Vb, Vc)
STEST2 ( vvc1f, v8hi, Vb, Vc)
STEST2 ( vvc1ft, v8hi, Vb, Vc)
STEST2 ( vbaddw, v8hi, Vb, rlimm)
STEST2 ( vbmaxw, v8hi, Vb, rlimm)
STEST2 ( vbminw, v8hi, Vb, rlimm)
STEST2 (vbmulaw, v8hi, Vb, rlimm)
STEST2 (vbmulfw, v8hi, Vb, rlimm)
STEST2 ( vbmulw, v8hi, Vb, rlimm)
STEST2 (vbrsubw, v8hi, Vb, rlimm)
STEST2 ( vbsubw, v8hi, Vb, rlimm)
/* Va, Vb, Ic instructions. */
STEST2 ( vasrw, v8hi, Vb, Ic)
STEST2 ( vsr8, v8hi, Vb, Ic)
STEST2 (vsr8aw, v8hi, Vb, Ic)
/* Va, Vb, u6 instructions. */
STEST2 ( vasrrwi, v8hi, Vb, u6)
STEST2 ( vasrsrwi, v8hi, Vb, u6)
STEST2 ( vasrwi, v8hi, Vb, u6)
STEST2 ( vasrpwbi, v8hi, Vb, u6)
STEST2 (vasrrpwbi, v8hi, Vb, u6)
STEST2 ( vsr8awi, v8hi, Vb, u6)
STEST2 ( vsr8i, v8hi, Vb, u6)
/* Va, Vb, u8 (simm) instructions. */
STEST2 ( vmvaw, v8hi, Vb, u8)
STEST2 ( vmvw, v8hi, Vb, u8)
STEST2 ( vmvzw, v8hi, Vb, u8)
STEST2 (vd6tapf, v8hi, Vb, u8)
/* Va, rlimm, u8 (simm) instructions. */
STEST2 (vmovaw, v8hi, rlimm, u8)
STEST2 ( vmovw, v8hi, rlimm, u8)
STEST2 (vmovzw, v8hi, rlimm, u8)
/* Va, Vb instructions. */
STEST1 ( vabsaw, v8hi, Vb)
STEST1 ( vabsw, v8hi, Vb)
STEST1 (vaddsuw, v8hi, Vb)
STEST1 ( vsignw, v8hi, Vb)
STEST1 ( vexch1, v8hi, Vb)
STEST1 ( vexch2, v8hi, Vb)
STEST1 ( vexch4, v8hi, Vb)
STEST1 ( vupbaw, v8hi, Vb)
STEST1 ( vupbw, v8hi, Vb)
STEST1 (vupsbaw, v8hi, Vb)
STEST1 ( vupsbw, v8hi, Vb)
/* DIb, rlimm, rlimm instructions. */
STEST2 (vdirun, void, rlimm, rlimm)
STEST2 (vdorun, void, rlimm, rlimm)
/* DIb, limm, rlimm instructions. */
STEST2 (vdiwr, void, u3, rlimm)
STEST2 (vdowr, void, u3, rlimm)
/* rlimm instructions. */
STEST1 ( vrec, void, rlimm)
STEST1 ( vrun, void, rlimm)
STEST1 (vrecrun, void, rlimm)
STEST1 (vendrec, void, rlimm)
/* Va, [Ib,u8] instructions. */
STEST3 (vld32wh, v8hi, Vb, Ic, u8)
STEST3 (vld32wl, v8hi, Vb, Ic, u8)
STEST3 ( vld64, v8hi, Vb, Ic, u8)
STEST3 ( vld32, v8hi, Vb, Ic, u8)
STEST2 (vld64w, v8hi, Ib, u8)
STEST2 (vld128, v8hi, Ib, u8)
STEST3 (vst128, void, Va, Ib, u8)
STEST3 ( vst64, void, Va, Ib, u8)
/* Va, [Ib, u8] instructions. */
STEST4 (vst16_n, void, Va, u3, Ib, u8)
STEST4 (vst32_n, void, Va, u3, Ib, u8)
STEST1 (vinti, void, u6)
gcc/testsuite/gcc.target/arc/builtin_special.c 0 → 100644
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration" } */
#define NORET(name) \
void test_ ## name (void) \
{ \
__builtin_arc_ ## name (); \
}
#define RET(name, rettype) \
rettype test_ ## name (void) \
{ \
return __builtin_arc_ ## name (); \
}
#define NORET1OP(name, op1type) \
void test_ ## name ## _1 (void) \
{ \
__builtin_arc_ ## name (0x10); \
}
NORET (nop)
NORET (rtie)
#ifdef __A7__
NORET (sync)
#endif
NORET (brk)
NORET (swi)
NORET1OP (sleep, unsigned int)
#if defined (__A7__) || defined (__EM__) || defined (__HS__)
NORET1OP (trap_s, unsigned int)
NORET (unimp_s)
#endif
#if defined (__EM__) || defined (__HS__)
RET (clri, int)
#endif
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