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riscv-gcc-1
Commit c61465bd by Matthew Wahab Committed by Jiong Wang
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[AArch64] ARMv8.2 command line and feature macros support 

	* config/aarch64/aarch64-arches.def: Add "armv8.2-a".
	* config/aarch64/aarch64.h (AARCH64_FL_V8_2): New.
	(AARCH64_FL_F16): New.
	(AARCH64_FL_FOR_ARCH8_2): New.
	(AARCH64_ISA_8_2): New.
	(AARCH64_ISA_F16): New.
	(TARGET_FP_F16INST): New.
	(TARGET_SIMD_F16INST): New.
	* config/aarch64/aarch64-option-extensions.def ("fp16"): New entry.
	("fp"): Disabling "fp" also disables "fp16".
	* config/aarch64/aarch64-c.c (arch64_update_cpp_builtins): Conditionally define
	__ARM_FEATURE_FP16_SCALAR_ARITHMETIC and __ARM_FEATURE_FP16_VECTOR_ARITHMETIC.
	* doc/invoke.texi (AArch64 Options): Document "armv8.2-a" and "fp16".


Co-Authored-By: Jiong Wang <jiong.wang@arm.com>

From-SVN: r237956
parent 79335075
Showing with 46 additions and 3 deletions
gcc/ChangeLog
2016-07-04 Matthew Wahab <matthew.wahab@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64-arches.def: Add "armv8.2-a".
* config/aarch64/aarch64.h (AARCH64_FL_V8_2): New.
(AARCH64_FL_F16): New.
(AARCH64_FL_FOR_ARCH8_2): New.
(AARCH64_ISA_8_2): New.
(AARCH64_ISA_F16): New.
(TARGET_FP_F16INST): New.
(TARGET_SIMD_F16INST): New.
* config/aarch64/aarch64-option-extensions.def ("fp16"): New entry.
("fp"): Disabling "fp" also disables "fp16".
* config/aarch64/aarch64-c.c (arch64_update_cpp_builtins): Conditionally define
__ARM_FEATURE_FP16_SCALAR_ARITHMETIC and __ARM_FEATURE_FP16_VECTOR_ARITHMETIC.
* doc/invoke.texi (AArch64 Options): Document "armv8.2-a" and "fp16".
2016-07-04 Jan Beulich <jbeulich@suse.com>
* gcc.c (default_compilers["@c-header"]): Conditionalize "-o".
......
gcc/config/aarch64/aarch64-arches.def
......@@ -32,4 +32,5 @@
AARCH64_ARCH("armv8-a", generic, 8A, 8, AARCH64_FL_FOR_ARCH8)
AARCH64_ARCH("armv8.1-a", generic, 8_1A, 8, AARCH64_FL_FOR_ARCH8_1)
AARCH64_ARCH("armv8.2-a", generic, 8_2A, 8, AARCH64_FL_FOR_ARCH8_2)
gcc/config/aarch64/aarch64-c.c
......@@ -95,6 +95,11 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
else
cpp_undef (pfile, "__ARM_FP");
aarch64_def_or_undef (TARGET_FP_F16INST,
"__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_SIMD_F16INST,
"__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", pfile);
aarch64_def_or_undef (TARGET_SIMD, "__ARM_FEATURE_NUMERIC_MAXMIN", pfile);
aarch64_def_or_undef (TARGET_SIMD, "__ARM_NEON", pfile);
......
gcc/config/aarch64/aarch64-option-extensions.def
......@@ -39,8 +39,8 @@
that are required. Their order is not important. */
/* Enabling "fp" just enables "fp".
Disabling "fp" also disables "simd", "crypto". */
AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO, "fp")
Disabling "fp" also disables "simd", "crypto" and "fp16". */
AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16, "fp")
/* Enabling "simd" also enables "fp".
Disabling "simd" also disables "crypto". */
......@@ -55,3 +55,7 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, "crc32")
/* Enabling or disabling "lse" only changes "lse". */
AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, "atomics")
/* Enabling "fp16" also enables "fp".
Disabling "fp16" just disables "fp16". */
AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fp16")
gcc/config/aarch64/aarch64.h
......@@ -135,6 +135,9 @@ extern unsigned aarch64_architecture_version;
/* ARMv8.1 architecture extensions. */
#define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */
#define AARCH64_FL_V8_1 (1 << 5) /* Has ARMv8.1 extensions. */
/* ARMv8.2-A architecture extensions. */
#define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */
#define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */
/* Has FP and SIMD. */
#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
......@@ -146,6 +149,8 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD)
#define AARCH64_FL_FOR_ARCH8_1 \
(AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1)
#define AARCH64_FL_FOR_ARCH8_2 \
(AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
/* Macros to test ISA flags. */
......@@ -155,6 +160,8 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD)
#define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE)
#define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_V8_1)
#define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2)
#define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16)
/* Crypto is an optional extension to AdvSIMD. */
#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
......@@ -165,6 +172,10 @@ extern unsigned aarch64_architecture_version;
/* Atomic instructions that can be enabled through the +lse extension. */
#define TARGET_LSE (AARCH64_ISA_LSE)
/* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */
#define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
#define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
/* Make sure this is always defined so we don't have to check for ifdefs
but rather use normal ifs. */
#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
......
gcc/doc/invoke.texi
......@@ -13101,7 +13101,10 @@ more feature modifiers. This option has the form
@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
The permissible values for @var{arch} are @samp{armv8-a},
@samp{armv8.1-a} or @var{native}.
@samp{armv8.1-a}, @samp{armv8.2-a} or @var{native}.
The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler
support for the ARMv8.2-A architecture extensions.
The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
support for the ARMv8.1 architecture extension. In particular, it
......@@ -13208,6 +13211,8 @@ instructions. This is on by default for all possible values for options
@item lse
Enable Large System Extension instructions. This is on by default for
@option{-march=armv8.1-a}.
@item fp16
Enable FP16 extension. This also enables floating-point instructions.
@end table
......
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