re PR target/8603 ([Alpha] s?addl pattern doesn't work)

	PR target/8603
	* config/alpha/alpha.md (addsi3): Remove expander.
	(addsi3): Rename from *addsi3_internal insn pattern.
	(subsi3): Remove expander.
	(subsi3): Rename from *subsi3_internal insn pattern.

From-SVN: r150654

gcc/ChangeLog

+2009-08-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/8603
+	* config/alpha/alpha.md (addsi3): Remove expander.
+	(addsi3): Rename from *addsi3_internal insn pattern.
+	(subsi3): Remove expander.
+	(subsi3): Rename from *subsi3_internal insn pattern.
+
 2009-08-11  Douglas B Rupp  <rupp@gnat.com>
 
 	* config/alpha/alpha.c (alpha_init_builtins): Nullify FWRITE and
@@ -24,8 +32,7 @@
 2009-08-11  Richard Guenther  <rguenther@suse.de>
 	
 	PR bootstrap/40788
-        * builtins.c (gimplify_va_arg_expr): Do not call 
-        SET_EXPR_LOCATION.
+	* builtins.c (gimplify_va_arg_expr): Do not call SET_EXPR_LOCATION.
 
 2009-08-10  Douglas B Rupp  <rupp@gnat.com>
 
@@ -203,8 +210,7 @@
 2009-08-09  Richard Guenther  <rguenther@suse.de>
 
 	PR tree-optimization/41016
-	* tree-ssa-ifcombine.c (get_name_for_bit_test): Fix tuplification
-	bug.
+	* tree-ssa-ifcombine.c (get_name_for_bit_test): Fix tuplification bug.
 	(operand_precision): Remove.
 	(integral_operand_p): Likewise.
 	(recognize_single_bit_test): Adjust.
@@ -252,8 +258,7 @@
 	(force_expr_to_var_cost): Cast target_spill_cost to int.
 	(get_address_cost): New arguments STMT_AFTER_INC and MAY_AUTOINC.
 	All callers changed.  Check for availability of autoinc addressing
-	modes, both in general for a given mode, and in the specific use
-	case.
+	modes, both in general for a given mode, and in the specific use case.
 	(get_computation_cost_at): New argument CAN_AUTOINC.  All callers
 	changed.
 	(get_computation_cost): Likewise.

gcc/config/alpha/alpha.md

@@ -256,16 +256,7 @@
 	(sign_extend:DI (match_dup 1)))]
   "")
 
-;; Don't say we have addsi3 if optimizing.  This generates better code.  We
-;; have the anonymous addsi3 pattern below in case combine wants to make it.
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
-		 (match_operand:SI 2 "add_operand" "")))]
-  "! optimize"
-  "")
-
-(define_insn "*addsi_internal"
+(define_insn "addsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
 		 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
@@ -619,14 +610,7 @@
   ""
   "subqv $31,%1,%0")
 
-(define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
-		  (match_operand:SI 2 "reg_or_8bit_operand" "")))]
-  "! optimize"
-  "")
-
-(define_insn "*subsi_internal"
+(define_insn "subsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
 		  (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]