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Commit c3c3ddbb by Jeff Law Committed by Jeff Law
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h8300.c (h8300_insn_length_from_table): Consolidate ADDB... 

	* config/h8300/h8300.c (h8300_insn_length_from_table): Consolidate
	ADDB, ADDW and ADDL into a single ADD attribute which selects the
	right table based on the size of the operand.
	* config/h8300/h8300.md (length_table): Corresponding changes. All
	references to "addb", "addw" and "addl" changed to "add".
	(btst patterns): Merge two variants into a single pattern.
	(tstqi, tsthi): Likewise.
	(addhi3_incdec, addsi3_incdec): Likewise.
	(subhi3_h8300hs, subsi3_h8300hs): Likewise.
	(mulhi3, mulsi3): Likewise.
	(udivhi3, udivsi3): Likewise.
	(divhi3, divsi3): Likewise.
	(andorqi3, andorhi3, andorsi3): Likewise.

From-SVN: r262357
parent 15333be7
Showing with 99 additions and 139 deletions
gcc/ChangeLog
2018-07-03 Jeff Law <law@redhat.com>
* config/h8300/h8300.c (h8300_insn_length_from_table): Consolidate
ADDB, ADDW and ADDL into a single ADD attribute which selects the
right table based on the size of the operand.
* config/h8300/h8300.md (length_table): Corresponding changes. All
references to "addb", "addw" and "addl" changed to "add".
(btst patterns): Merge two variants into a single pattern.
(tstqi, tsthi): Likewise.
(addhi3_incdec, addsi3_incdec): Likewise.
(subhi3_h8300hs, subsi3_h8300hs): Likewise.
(mulhi3, mulsi3): Likewise.
(udivhi3, udivsi3): Likewise.
(divhi3, divsi3): Likewise.
(andorqi3, andorhi3, andorsi3): Likewise.
2018-07-03 Uros Bizjak <ubizjak@gmail.com>
PR target/85694
......
gcc/config/h8300/h8300.c
......@@ -2551,14 +2551,14 @@ h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
case LENGTH_TABLE_NONE:
gcc_unreachable ();
case LENGTH_TABLE_ADDB:
case LENGTH_TABLE_ADD:
if (GET_MODE (operands[0]) == QImode)
return h8300_binary_length (insn, &addb_length_table);
case LENGTH_TABLE_ADDW:
else if (GET_MODE (operands[0]) == HImode)
return h8300_binary_length (insn, &addw_length_table);
case LENGTH_TABLE_ADDL:
else if (GET_MODE (operands[0]) == SImode)
return h8300_binary_length (insn, &addl_length_table);
gcc_unreachable ();
case LENGTH_TABLE_LOGICB:
return h8300_binary_length (insn, &logicb_length_table);
......
gcc/config/h8300/h8300.md
......@@ -77,7 +77,7 @@
(define_attr "type" "branch,arith,bitbranch,call"
(const_string "arith"))
(define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
(define_attr "length_table" "none,add,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
(const_string "none"))
;; The size of instructions in bytes.
......@@ -824,17 +824,6 @@
[(set_attr "length" "2,4")
(set_attr "cc" "set_zn,set_zn")])
(define_insn ""
[(set (cc0)
(compare (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
(const_int 1)
(match_operand 1 "const_int_operand" "n"))
(const_int 0)))]
"TARGET_H8300"
"btst %Z1,%Y0"
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
(define_insn_and_split "*tst_extzv_1_n"
[(set (cc0)
(compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
......@@ -862,11 +851,11 @@
(define_insn ""
[(set (cc0)
(compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
(compare (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
(const_int 1)
(match_operand 1 "const_int_operand" "n"))
(const_int 0)))]
"(TARGET_H8300H || TARGET_H8300S)
"(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S)
&& INTVAL (operands[1]) <= 15"
"btst %Z1,%Y0"
[(set_attr "length" "2")
......@@ -937,21 +926,18 @@
[(set_attr "length" "2,8,10")
(set_attr "cc" "set_zn,set_zn,set_zn")])
(define_insn "*tstqi"
[(set (cc0)
(compare (match_operand:QI 0 "register_operand" "r")
(const_int 0)))]
""
"mov.b %X0,%X0"
[(set_attr "length" "2")
(set_attr "cc" "set_znv")])
(define_insn "*tsthi"
(define_insn "*tst<mode>"
[(set (cc0)
(compare (match_operand:HI 0 "register_operand" "r")
(compare (match_operand:QHI 0 "register_operand" "r")
(const_int 0)))]
""
"mov.w %T0,%T0"
{
if (<MODE>mode == QImode)
return "mov.b %X0,%X0";
else if (<MODE>mode == HImode)
return "mov.w %T0,%T0";
gcc_unreachable ();
}
[(set_attr "length" "2")
(set_attr "cc" "set_znv")])
......@@ -990,7 +976,7 @@
(match_operand:QI 1 "h8300_src_operand" "rQi")))]
""
"cmp.b %X1,%X0"
[(set_attr "length_table" "addb")
[(set_attr "length_table" "add")
(set_attr "cc" "compare")])
(define_insn "*cmphi_h8300_znvc"
......@@ -1021,7 +1007,7 @@
gcc_unreachable ();
}
}
[(set_attr "length_table" "short_immediate,addw")
[(set_attr "length_table" "short_immediate,add")
(set_attr "cc" "compare,compare")])
(define_insn "cmpsi"
......@@ -1044,7 +1030,7 @@
}
}
[(set_attr "length" "2,*")
(set_attr "length_table" "*,addl")
(set_attr "length_table" "*,add")
(set_attr "cc" "compare,compare")])
;; ----------------------------------------------------------------------
......@@ -1064,7 +1050,7 @@
(match_operand:QI 2 "h8300_src_operand" "rQi")))]
"h8300_operands_match_p (operands)"
"add.b %X2,%X0"
[(set_attr "length_table" "addb")
[(set_attr "length_table" "add")
(set_attr "cc" "set_zn")])
(define_insn "*addhi3_h8300"
......@@ -1127,15 +1113,19 @@
[(set_attr "length" "2,2,2,4,2")
(set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
(define_insn "*addhi3_incdec"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
(match_operand:HI 2 "incdec_operand" "M,O")]
(define_insn "*add<mode>3_incdec"
[(set (match_operand:HSI 0 "register_operand" "=r,r")
(unspec:HSI [(match_operand:HSI 1 "register_operand" "0,0")
(match_operand:HSI 2 "incdec_operand" "M,O")]
UNSPEC_INCDEC))]
"TARGET_H8300H || TARGET_H8300S"
"@
inc.w %2,%T0
dec.w %G2,%T0"
{
if (which_alternative == 0)
return <MODE>mode == HImode ? "inc.w\t%2,%T0" : "inc.l\t%2,%S0";
else if (which_alternative == 1)
return <MODE>mode == HImode ? "dec.w\t%G2,%T0" : "dec.l\t%G2,%S0";
gcc_unreachable ();
}
[(set_attr "length" "2,2")
(set_attr "cc" "set_zn,set_zn")])
......@@ -1149,7 +1139,7 @@
sub.w %G2:3,%T0
add.b %t2,%t0
add.w %T2,%T0"
[(set_attr "length_table" "short_immediate,short_immediate,*,addw")
[(set_attr "length_table" "short_immediate,short_immediate,*,add")
(set_attr "length" "*,*,2,*")
(set_attr "cc" "set_zn")])
......@@ -1191,18 +1181,6 @@
(set (attr "cc")
(symbol_ref "compute_plussi_cc (operands)"))])
(define_insn "*addsi3_incdec"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
(match_operand:SI 2 "incdec_operand" "M,O")]
UNSPEC_INCDEC))]
"TARGET_H8300H || TARGET_H8300S"
"@
inc.l %2,%S0
dec.l %G2,%S0"
[(set_attr "length" "2,2")
(set_attr "cc" "set_zn,set_zn")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_dup 0)
......@@ -1234,7 +1212,7 @@
(match_operand:QI 2 "h8300_dst_operand" "rQ")))]
"h8300_operands_match_p (operands)"
"sub.b %X2,%X0"
[(set_attr "length_table" "addb")
[(set_attr "length_table" "add")
(set_attr "cc" "set_zn")])
(define_insn "*subhi3_h8300"
......@@ -1248,15 +1226,19 @@
[(set_attr "length" "2,4")
(set_attr "cc" "set_zn,clobber")])
(define_insn "*subhi3_h8300hs"
[(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
(minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
(match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
(define_insn "*sub<mode>3_h8300hs"
[(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ,rQ")
(minus:HSI (match_operand:HSI 1 "h8300_dst_operand" "0,0")
(match_operand:HSI 2 "h8300_src_operand" "rQ,i")))]
"(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
"@
sub.w %T2,%T0
sub.w %T2,%T0"
[(set_attr "length_table" "addw")
{
if (<MODE>mode == HImode)
return "sub.w %T2,%T0";
else if (<MODE>mode == SImode)
return "sub.l %S2,%S0";
gcc_unreachable ();
}
[(set_attr "length_table" "add")
(set_attr "cc" "set_zn")])
(define_insn "*subsi3_h8300"
......@@ -1267,16 +1249,6 @@
"sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
[(set_attr "length" "6")])
(define_insn "*subsi3_h8300hs"
[(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
(minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
(match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
"(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
"@
sub.l %S2,%S0
sub.l %S2,%S0"
[(set_attr "length_table" "addl")
(set_attr "cc" "set_zn")])
;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS
......@@ -1404,21 +1376,12 @@
;; on a H8SX with a multiplier, whereas muls.w seems to be available
;; on all H8SX variants.
(define_insn "mulhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (match_operand:HI 1 "register_operand" "%0")
(match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
"TARGET_H8300SX"
"muls.w\\t%T2,%T0"
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
(define_insn "mul<mode>3"
[(set (match_operand:HSI 0 "register_operand" "=r")
(mult:HSI (match_operand:HSI 1 "register_operand" "%0")
(match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
"TARGET_H8300SX"
"muls.l\\t%S2,%S0"
{ return <MODE>mode == HImode ? "muls.w\\t%T2,%T0" : "muls.l\\t%S2,%S0"; }
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
......@@ -1485,36 +1448,20 @@
;; DIVIDE/MOD INSTRUCTIONS
;; ----------------------------------------------------------------------
(define_insn "udivhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(udiv:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
"TARGET_H8300SX"
"divu.w\\t%T2,%T0"
[(set_attr "length" "2")])
(define_insn "divhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(div:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
"TARGET_H8300SX"
"divs.w\\t%T2,%T0"
[(set_attr "length" "2")])
(define_insn "udivsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(udiv:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
(define_insn "udiv<mode>3"
[(set (match_operand:HSI 0 "register_operand" "=r")
(udiv:HSI (match_operand:HSI 1 "register_operand" "0")
(match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
"TARGET_H8300SX"
"divu.l\\t%S2,%S0"
{ return <MODE>mode == HImode ? "divu.w\\t%T2,%T0" : "divu.l\\t%S2,%S0"; }
[(set_attr "length" "2")])
(define_insn "divsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(div:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
(define_insn "div<mode>3"
[(set (match_operand:HSI 0 "register_operand" "=r")
(div:HSI (match_operand:HSI 1 "register_operand" "0")
(match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
"TARGET_H8300SX"
"divs.l\\t%S2,%S0"
{ return <MODE>mode == HImode ? "divs.w\\t%T2,%T0" : "divs.l\\t%S2,%S0"; }
[(set_attr "length" "2")])
(define_insn "udivmodqi4"
......@@ -1671,22 +1618,21 @@
""
"")
(define_insn "*andorqi3"
[(set (match_operand:QI 0 "register_operand" "=r")
(ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
(match_operand:QI 3 "single_one_operand" "n"))
(match_operand:QI 1 "register_operand" "0")))]
""
"bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
[(set_attr "length" "6")])
(define_insn "*andor<mode>3"
[(set (match_operand:QHSI 0 "register_operand" "=r")
(ior:QHSI (and:QHSI (match_operand:QHSI 2 "register_operand" "r")
(match_operand:QHSI 3 "single_one_operand" "n"))
(match_operand:QHSI 1 "register_operand" "0")))]
"(<MODE>mode == QImode
|| <MODE>mode == HImode
|| (<MODE>mode == SImode
&& (INTVAL (operands[3]) & 0xffff) != 0))"
{
if (<MODE>mode == QImode)
return "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0";
(define_insn "*andorhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
(match_operand:HI 3 "single_one_operand" "n"))
(match_operand:HI 1 "register_operand" "0")))]
""
{
if (<MODE>mode == HImode)
{
operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
if (INTVAL (operands[3]) > 128)
{
......@@ -1694,16 +1640,10 @@
return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0";
}
return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0";
}
[(set_attr "length" "6")])
}
(define_insn "*andorsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "single_one_operand" "n"))
(match_operand:SI 1 "register_operand" "0")))]
"(INTVAL (operands[3]) & 0xffff) != 0"
{
if (<MODE>mode == SImode)
{
operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
if (INTVAL (operands[3]) > 128)
{
......@@ -1711,7 +1651,11 @@
return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0";
}
return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0";
}
}
gcc_unreachable ();
}
[(set_attr "length" "6")])
(define_insn "*andorsi3_shift_8"
......
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