* config/alpha/alpha.c (alpha_emit_set_const_1)

	(alpha_emit_set_long_const, alpha_extract_integer)
	(alpha_legitimate_constant_p, alpha_split_const_mov)
	(alpha_expand_block_clear, alpha_expand_zap_mask, print_operand):
	[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
	(alpha_emit_set_const_1): Change "(HOST_WIDE_INT) 1" to
	HOST_WIDE_INT_1U.
	* config/alpha/predicates.md (mode_mask_operand): Do not match
	const_double RTX.
	[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
	* config/alpha/alpha.md (abstf, *abstf_internal, UNSPEC_ZAP splitter):
	Change "(HOST_WIDE_INT) 1" to HOST_WIDE_INT_1U.
	[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
	(*negtf_internal): Use gen_int_mode instead of immed_double_const.

From-SVN: r222994

gcc/ChangeLog

+2015-05-11  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/alpha/alpha.c (alpha_emit_set_const_1)
+	(alpha_emit_set_long_const, alpha_extract_integer)
+	(alpha_legitimate_constant_p, alpha_split_const_mov)
+	(alpha_expand_block_clear, alpha_expand_zap_mask, print_operand):
+	[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
+	(alpha_emit_set_const_1): Change "(HOST_WIDE_INT) 1" to
+	HOST_WIDE_INT_1U.
+	* config/alpha/predicates.md (mode_mask_operand): Do not match
+	const_double RTX.
+	[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
+	* config/alpha/alpha.md (abstf, *abstf_internal, UNSPEC_ZAP splitter):
+	Change "(HOST_WIDE_INT) 1" to HOST_WIDE_INT_1U.
+	[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
+	(*negtf_internal): Use gen_int_mode instead of immed_double_const.
+
 2015-05-11  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/65780

gcc/config/alpha/alpha.c

@@ -1771,11 +1771,9 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
   rtx temp, insn;
 
   /* If this is a sign-extended 32-bit constant, we can do this in at most
-     three insns, so do it if we have enough insns left.  We always have
-     a sign-extended 32-bit constant when compiling on a narrow machine.  */
+     three insns, so do it if we have enough insns left.  */
 
-  if (HOST_BITS_PER_WIDE_INT != 64
-      || c >> 31 == -1 || c >> 31 == 0)
+  if (c >> 31 == -1 || c >> 31 == 0)
     {
       HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
       HOST_WIDE_INT tmp1 = c - low;
@@ -1917,11 +1915,9 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
       /* Now try high-order zero bits.  Here we try the shifted-in bits as
 	 all zero and all ones.  Be careful to avoid shifting outside the
 	 mode and to avoid shifting outside the host wide int size.  */
-      /* On narrow hosts, don't shift a 1 into the high bit, since we'll
-	 confuse the recursive call and set all of the high 32 bits.  */
 
       bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
-	      - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64));
+	      - floor_log2 (c) - 1);
       if (bits > 0)
 	for (; bits > 0; bits--)
 	  {
@@ -1929,7 +1925,7 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
 	    temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
 	    if (!temp)
 	      {
-		new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
+		new_const = (c << bits) | ((HOST_WIDE_INT_1U << bits) - 1);
 	        temp = alpha_emit_set_const (subtarget, mode, new_const,
 					     i, no_output);
 	      }
@@ -1955,7 +1951,7 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
 	    temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
 	    if (!temp)
 	      {
-		new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
+		new_const = (c << bits) | ((HOST_WIDE_INT_1U << bits) - 1);
 	        temp = alpha_emit_set_const (subtarget, mode, new_const,
 					     i, no_output);
 	      }
@@ -1969,7 +1965,6 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
 	  }
     }
 
-#if HOST_BITS_PER_WIDE_INT == 64
   /* Finally, see if can load a value into the target that is the same as the
      constant except that all bytes that are 0 are changed to be 0xff.  If we
      can, then we can do a ZAPNOT to obtain the desired constant.  */
@@ -1996,7 +1991,6 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
 			       target, 0, OPTAB_WIDEN);
 	}
     }
-#endif
 
   return 0;
 }
@@ -2077,7 +2071,7 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
   HOST_WIDE_INT d1, d2, d3, d4;
 
   /* Decompose the entire word */
-#if HOST_BITS_PER_WIDE_INT >= 64
+
   gcc_assert (c2 == -(c1 < 0));
   d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
   c1 -= d1;
@@ -2087,17 +2081,6 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
   c1 -= d3;
   d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
   gcc_assert (c1 == d4);
-#else
-  d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
-  c1 -= d1;
-  d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
-  gcc_assert (c1 == d2);
-  c2 += (d2 < 0);
-  d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
-  c2 -= d3;
-  d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
-  gcc_assert (c2 == d4);
-#endif
 
   /* Construct the high word */
   if (d4)
@@ -2138,15 +2121,10 @@ alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
       i0 = INTVAL (x);
       i1 = -(i0 < 0);
     }
-  else if (HOST_BITS_PER_WIDE_INT >= 64)
-    {
-      i0 = CONST_DOUBLE_LOW (x);
-      i1 = -(i0 < 0);
-    }
   else
     {
       i0 = CONST_DOUBLE_LOW (x);
-      i1 = CONST_DOUBLE_HIGH (x);
+      i1 = -(i0 < 0);
     }
 
   *p0 = i0;
@@ -2206,9 +2184,7 @@ alpha_legitimate_constant_p (machine_mode mode, rtx x)
       if (TARGET_BUILD_CONSTANTS)
 	return true;
       alpha_extract_integer (x, &i0, &i1);
-      if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == (-i0 < 0))
       return alpha_emit_set_const_1 (x, mode, i0, 3, true) != NULL;
-      return false;
 
     default:
       return false;
@@ -2226,7 +2202,6 @@ alpha_split_const_mov (machine_mode mode, rtx *operands)
 
   alpha_extract_integer (operands[1], &i0, &i1);
 
-  if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
   temp = alpha_emit_set_const (operands[0], mode, i0, 3, false);
 
   if (!temp && TARGET_BUILD_CONSTANTS)
@@ -4099,7 +4074,6 @@ alpha_expand_block_clear (rtx operands[])
 
   if (alignofs > 0)
     {
-#if HOST_BITS_PER_WIDE_INT >= 64
       /* Given that alignofs is bounded by align, the only time BWX could
 	 generate three stores is for a 7 byte fill.  Prefer two individual
 	 stores over a load/mask/store sequence.  */
@@ -4134,7 +4108,6 @@ alpha_expand_block_clear (rtx operands[])
 
 	  emit_move_insn (mem, tmp);
 	}
-#endif
 
       if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
 	{
@@ -4246,7 +4219,6 @@ alpha_expand_block_clear (rtx operands[])
 
   /* Next clean up any trailing pieces.  */
 
-#if HOST_BITS_PER_WIDE_INT >= 64
   /* Count the number of bits in BYTES for which aligned stores could
      be emitted.  */
   words = 0;
@@ -4291,7 +4263,6 @@ alpha_expand_block_clear (rtx operands[])
 	  return 1;
 	}
     }
-#endif
 
   if (!TARGET_BWX && bytes >= 4)
     {
@@ -4336,9 +4307,6 @@ alpha_expand_zap_mask (HOST_WIDE_INT value)
 {
   rtx result;
   int i;
-
-  if (HOST_BITS_PER_WIDE_INT >= 64)
-    {
   HOST_WIDE_INT mask = 0;
 
   for (i = 7; i >= 0; --i)
@@ -4349,30 +4317,6 @@ alpha_expand_zap_mask (HOST_WIDE_INT value)
     }
 
   result = gen_int_mode (mask, DImode);
-    }
-  else
-    {
-      HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
-
-      gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
-      
-      for (i = 7; i >= 4; --i)
-	{
-	  mask_hi <<= 8;
-	  if (!((value >> i) & 1))
-	    mask_hi |= 0xff;
-	}
-
-      for (i = 3; i >= 0; --i)
-	{
-	  mask_lo <<= 8;
-	  if (!((value >> i) & 1))
-	    mask_lo |= 0xff;
-	}
-
-      result = immed_double_const (mask_lo, mask_hi, DImode);
-    }
-
   return result;
 }
 
@@ -5288,7 +5232,7 @@ print_operand (FILE *file, rtx x, int code)
       if (!CONST_INT_P (x))
 	output_operand_lossage ("invalid %%P value");
 
-      fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, HOST_WIDE_INT_1 << INTVAL (x));
       break;
 
     case 'h':
@@ -5385,14 +5329,7 @@ print_operand (FILE *file, rtx x, int code)
 	      break;
 	    }
 	}
-      else if (HOST_BITS_PER_WIDE_INT == 32
-	       && GET_CODE (x) == CONST_DOUBLE
-	       && CONST_DOUBLE_LOW (x) == 0xffffffff
-	       && CONST_DOUBLE_HIGH (x) == 0)
-	{
-	  fputc ('l', file);
-	  break;
-	}
+
       output_operand_lossage ("invalid %%U value");
       break;
 
@@ -6788,13 +6725,6 @@ alpha_expand_builtin (tree exp, rtx target,
     return const0_rtx;
 }
 
-
-/* Several bits below assume HWI >= 64 bits.  This should be enforced
-   by config.gcc.  */
-#if HOST_BITS_PER_WIDE_INT < 64
-# error "HOST_WIDE_INT too small"
-#endif
-
 /* Fold the builtin for the CMPBGE instruction.  This is a vector comparison
    with an 8-bit output vector.  OPINT contains the integer operands; bit N
    of OP_CONST is set if OPINT[N] is valid.  */

gcc/config/alpha/alpha.md

@@ -951,7 +951,7 @@
   [(set (match_operand:DI 0 "register_operand")
 	(and:DI (match_operand:DI 1 "register_operand")
 		(match_operand:DI 2 "const_int_operand")))]
-  "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
+  "! and_operand (operands[2], DImode)"
   [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
    (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
 {
@@ -1508,17 +1508,14 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
 		   	   (match_operand:DI 2 "mul8_operand" "I"))
-		(match_operand:DI 3 "immediate_operand" "i")))]
-  "HOST_BITS_PER_WIDE_INT == 64
-   && CONST_INT_P (operands[3])
-   && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
+		(match_operand:DI 3 "const_int_operand" "i")))]
+  "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
     == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
     || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
         == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
     || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
-        == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
+        == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))"
 {
-#if HOST_BITS_PER_WIDE_INT == 64
   if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
       == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
     return "insbl %1,%s2,%0";
@@ -1528,7 +1525,7 @@
   if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
       == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
     return "insll %1,%s2,%0";
-#endif
+
   gcc_unreachable ();
 }
   [(set_attr "type" "shift")])
@@ -1619,13 +1616,7 @@
 		   (abs:TF (match_operand:TF 1 "reg_or_0_operand")))
 	      (use (match_dup 2))])]
   "TARGET_HAS_XFLOATING_LIBS"
-{
-#if HOST_BITS_PER_WIDE_INT >= 64
-  operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
-#else
-  operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
-#endif
-})
+  "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
 
 (define_insn_and_split "*abstf_internal"
   [(set (match_operand:TF 0 "register_operand" "=r")
@@ -1649,13 +1640,7 @@
 		   (neg:TF (match_operand:TF 1 "reg_or_0_operand")))
 	      (use (match_dup 2))])]
   "TARGET_HAS_XFLOATING_LIBS"
-{
-#if HOST_BITS_PER_WIDE_INT >= 64
-  operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
-#else
-  operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
-#endif
-})
+  "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
 
 (define_insn_and_split "*negtf_internal"
   [(set (match_operand:TF 0 "register_operand" "=r")
@@ -5440,7 +5425,7 @@
    (match_operand:DI 2 "reg_or_8bit_operand")]
   ""
 {
-  rtx mask = immed_double_const (0xffffffff, 0, DImode);
+  rtx mask = gen_int_mode (0xffffffff, DImode);
   emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
   DONE;
 })
@@ -5542,16 +5527,8 @@
   [(const_int 0)]
 {
   rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
-  if (HOST_BITS_PER_WIDE_INT >= 64 || CONST_INT_P (mask))
+
   operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
-  else
-    {
-      HOST_WIDE_INT c_lo = INTVAL (operands[1]);
-      HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
-      operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
-					c_hi & CONST_DOUBLE_HIGH (mask),
-					DImode);
-    }
   emit_move_insn (operands[0], operands[1]);
   DONE;
 })

gcc/config/alpha/predicates.md

@@ -110,10 +110,8 @@
 ;; Return 1 if OP is a constant that is a mask of ones of width of an
 ;; integral machine mode not larger than DImode.
 (define_predicate "mode_mask_operand"
-  (match_code "const_int,const_double")
+  (match_code "const_int")
 {
-  if (CONST_INT_P (op))
-    {
   HOST_WIDE_INT value = INTVAL (op);
 
   if (value == 0xff)
@@ -124,12 +122,7 @@
     return 1;
   if (value == -1)
     return 1;
-    }
-  else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
-    {
-      if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
-	return 1;
-    }
+
   return 0;
 })