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riscv-gcc-1
Commit c25a21f5 by Richard Henderson Committed by Richard Henderson
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mn10300: Expose the MDR register to register allocation. 

Note that nothing uses the "z" constraint yet except the one
move pattern; this merely defines the register class properly.

From-SVN: r169007
parent 36846b26
Showing with 64 additions and 14 deletions
gcc/ChangeLog
2011-01-19 Richard Henderson <rth@redhat.com>
* config/mn10300/constraints.md ("z"): New constraint.
* config/mn10300/mn10300.h (MDR_REGNUM): Remove.
(FIXED_REGISTERS): Don't fix MDR.
(CALL_USED_REGSITERS): Reformat nicely.
(REG_ALLOC_ORDER): Add MDR.
(enum regclass): Add MDR_REGS.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update to match.
(IRA_COVER_CLASSES): Add MDR_REGS.
(REGNO_REG_CLASS): Handle MDR_REG.
* config/mn10300/mn10300.c (mn10300_secondary_reload): Handle MDR_REGS.
(mn10300_register_move_cost): Likewise.
* config/mn10300/mn10300.md (MDR_REG): New.
(*movsi_internal): Handle moves to/from MDR_REGS.
* config/mn10300/mn10300.c (mn10300_print_operand_address): Handle
POST_MODIFY.
(mn10300_secondary_reload): Tidy combination reload classes.
......
gcc/config/mn10300/constraints.md
......@@ -35,6 +35,9 @@
(define_register_constraint "y" "SP_REGS"
"An SP register (if available).")
(define_register_constraint "z" "MDR_REGS"
"The MDR register.")
(define_register_constraint "x" "TARGET_AM33 ? EXTENDED_REGS : NO_REGS"
"An extended register.")
......
gcc/config/mn10300/mn10300.c
......@@ -1416,6 +1416,12 @@ mn10300_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
return NO_REGS;
}
/* We can only move MDR to/from a data register. */
if (rclass == MDR_REGS && xclass != DATA_REGS)
return DATA_REGS;
if (xclass == MDR_REGS && rclass != DATA_REGS)
return DATA_REGS;
/* We can't load/store an FP register from a constant address. */
if (TARGET_AM33_2
&& (rclass == FP_REGS || xclass == FP_REGS)
......@@ -2256,6 +2262,8 @@ mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
test = from;
if (to == SP_REGS)
scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
else if (to == MDR_REGS)
scratch = DATA_REGS;
else if (to == FP_REGS && to != from)
scratch = GENERAL_REGS;
else
......@@ -2263,6 +2271,8 @@ mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
test = to;
if (from == SP_REGS)
scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
else if (from == MDR_REGS)
scratch = DATA_REGS;
else if (from == FP_REGS && to != from)
scratch = GENERAL_REGS;
}
......
gcc/config/mn10300/mn10300.h
......@@ -157,7 +157,7 @@ extern enum processor_type mn10300_tune_cpu;
#define LAST_EXTENDED_REGNUM 17
#define FIRST_FP_REGNUM 18
#define LAST_FP_REGNUM 49
#define MDR_REGNUM 50
/* #define MDR_REG 50 */
/* #define CC_REG 51 */
#define FIRST_ARGUMENT_REGNUM 0
......@@ -182,9 +182,17 @@ extern enum processor_type mn10300_tune_cpu;
and are not available for the register allocator. */
#define FIXED_REGISTERS \
{ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 \
, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 \
{ 0, 0, 0, 0, /* data regs */ \
0, 0, 0, 0, /* addr regs */ \
1, /* arg reg */ \
1, /* sp reg */ \
0, 0, 0, 0, 0, 0, 0, 0, /* extended regs */ \
0, 0, /* fp regs (18-19) */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (30-39) */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (40-49) */ \
0, /* mdr reg */ \
1 /* cc reg */ \
}
/* 1 for registers not available across function calls.
......@@ -196,9 +204,17 @@ extern enum processor_type mn10300_tune_cpu;
like. */
#define CALL_USED_REGISTERS \
{ 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 \
, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
{ 1, 1, 0, 0, /* data regs */ \
1, 1, 0, 0, /* addr regs */ \
1, /* arg reg */ \
1, /* sp reg */ \
1, 1, 1, 1, 0, 0, 0, 0, /* extended regs */ \
1, 1, /* fp regs (18-19) */ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, /* fp regs (30-39) */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* fp regs (40-49) */ \
1, /* mdr reg */ \
1 /* cc reg */ \
}
/* Note: The definition of CALL_REALLY_USED_REGISTERS is not
......@@ -211,7 +227,7 @@ extern enum processor_type mn10300_tune_cpu;
#define REG_ALLOC_ORDER \
{ 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \
, 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \
, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 51 \
, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \
}
/* Return number of consecutive hard regs needed starting at reg REGNO
......@@ -262,7 +278,7 @@ extern enum processor_type mn10300_tune_cpu;
enum reg_class
{
NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, SP_OR_ADDRESS_REGS,
EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS,
EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS, MDR_REGS,
GENERAL_REGS, SP_OR_GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
};
......@@ -272,7 +288,7 @@ enum reg_class
#define REG_CLASS_NAMES \
{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \
"EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", \
"EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS", \
"GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS" \
}
......@@ -290,6 +306,7 @@ enum reg_class
{ 0xfffc0000, 0x3ffff },/* FP_REGS */ \
{ 0x03fc0000, 0 }, /* FP_ACC_REGS */ \
{ 0x00000000, 0x80000 },/* CC_REGS */ \
{ 0x00000000, 0x40000 },/* MDR_REGS */ \
{ 0x0003fdff, 0 }, /* GENERAL_REGS */ \
{ 0x0003ffff, 0 }, /* SP_OR_GENERAL_REGS */ \
{ 0xffffffff, 0xfffff } /* ALL_REGS */ \
......@@ -305,7 +322,7 @@ enum reg_class
#define IRA_COVER_CLASSES \
{ \
GENERAL_REGS, FP_REGS, LIM_REG_CLASSES \
GENERAL_REGS, FP_REGS, MDR_REGS, LIM_REG_CLASSES \
}
/* The same information, inverted:
......@@ -319,6 +336,7 @@ enum reg_class
(REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \
(REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \
(REGNO) <= LAST_FP_REGNUM ? FP_REGS : \
(REGNO) == MDR_REG ? MDR_REGS : \
(REGNO) == CC_REG ? CC_REGS : \
NO_REGS)
......
gcc/config/mn10300/mn10300.md
......@@ -28,6 +28,7 @@
(define_constants [
(PIC_REG 6)
(SP_REG 9)
(MDR_REG 50)
(CC_REG 51)
(UNSPEC_INT_LABEL 0)
......@@ -386,9 +387,9 @@
(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r,r,r,m,r, A,*y,*y")
"=r,r,r,m,r, A,*y,*y,*z,*d")
(match_operand:SI 1 "general_operand"
" 0,i,r,r,m,*y, A, i"))]
" 0,i,r,r,m,*y, A, i,*d,*z"))]
"register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)"
{
......@@ -416,12 +417,14 @@
case 5: /* sp-reg */
case 6: /* reg-sp */
case 7: /* imm-sp */
case 8: /* reg-mdr */
case 9: /* mdr-reg */
return "mov %1,%0";
default:
gcc_unreachable ();
}
}
[(set_attr "isa" "*,*,*,*,*,*,*,am33")
[(set_attr "isa" "*,*,*,*,*,*,*,am33,*,*")
(set_attr_alternative "timings"
[(const_int 11)
(const_int 22)
......@@ -435,6 +438,8 @@
(if_then_else (eq_attr "cpu" "am34")
(const_int 13) (const_int 24))
(const_int 11)
(const_int 11)
(const_int 11)
])]
)
......
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