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riscv-gcc-1
Commit be12c2b0 by Vladimir Makarov Committed by Vladimir Makarov
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2003-04-02 Vladimir Makarov <vmakarov@redhat.com> 

	* config/rs6000/rs6000.c
	(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Redefine the
	macros.
	(rs6000_issue_rate): Add case for 8540.
	(rs6000_use_sched_lookahead): New function.

	* config/rs6000/8540.md: Rename SIU units into SU ones and MIU
	units into MU ones.
	(ppc8540_branch, ppc8540_cr_logical): Add one cycle in the
	reservation before retirement.
	(ppc8540_multiply, ppc8540_load, ppc8540_store,
	ppc8540_simple_float, ppc8540_vector_load, ppc8540_vector_store):
	Remove additional cycle in the reservation before retirement.
	(ppc8540_mfcr, ppc8540_mtcrf, ppc8540_mtjmpr): Add missed
	reservation of ppc8540_issue.

From-SVN: r65167
parent 0f91f094
Showing with 91 additions and 47 deletions
gcc/ChangeLog
2003-04-02 Vladimir Makarov <vmakarov@redhat.com>
* config/rs6000/rs6000.c
(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Redefine the
macros.
(rs6000_issue_rate): Add case for 8540.
(rs6000_use_sched_lookahead): New function.
* config/rs6000/8540.md: Rename SIU units into SU ones and MIU
units into MU ones.
(ppc8540_branch, ppc8540_cr_logical): Add one cycle in the
reservation before retirement.
(ppc8540_multiply, ppc8540_load, ppc8540_store,
ppc8540_simple_float, ppc8540_vector_load, ppc8540_vector_store):
Remove additional cycle in the reservation before retirement.
(ppc8540_mfcr, ppc8540_mtcrf, ppc8540_mtjmpr): Add missed
reservation of ppc8540_issue.
2003-04-02 Andreas Schwab <schwab@suse.de> 2003-04-02 Andreas Schwab <schwab@suse.de>
* real.c (decode_ieee_single): Fix decoding of SNaN bit. * real.c (decode_ieee_single): Fix decoding of SNaN bit.
......
gcc/config/rs6000/8540.md
...@@ -20,6 +20,13 @@ ...@@ -20,6 +20,13 @@
(define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire") (define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire")
(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most") (define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most")
;; We don't simulate general issue queue (GIC). If we have SU insn
;; and then SU1 insn, they can not be issued on the same cycle
;; (although SU1 insn and then SU insn can be issued) because the SU
;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
;; multipass insn scheduling will find the situation and issue the SU1
;; insn and then the SU insn.
(define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most") (define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most")
;; We could describe completion buffers slots in combination with the ;; We could describe completion buffers slots in combination with the
...@@ -37,19 +44,19 @@ ...@@ -37,19 +44,19 @@
;; Branch unit: ;; Branch unit:
(define_cpu_unit "ppc8540_bu" "ppc8540_most") (define_cpu_unit "ppc8540_bu" "ppc8540_most")
;; SIU: ;; SU:
(define_cpu_unit "ppc8540_siu0_stage0,ppc8540_siu1_stage0" "ppc8540_most") (define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most")
;; We could describe here MIU subunits for float multiply, float add ;; We could describe here MU subunits for float multiply, float add
;; etc. But the result automaton would behave the same way as the ;; etc. But the result automaton would behave the same way as the
;; described one pipeline below because MIU can start only one insn ;; described one pipeline below because MU can start only one insn
;; per cycle. Actually we could simplify the automaton more not ;; per cycle. Actually we could simplify the automaton more not
;; describing stages 1-3, the result automata would be the same. ;; describing stages 1-3, the result automata would be the same.
(define_cpu_unit "ppc8540_miu_stage0,ppc8540_miu_stage1" "ppc8540_most") (define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most")
(define_cpu_unit "ppc8540_miu_stage2,ppc8540_miu_stage3" "ppc8540_most") (define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most")
;; The following unit is used to describe non-pipelined division. ;; The following unit is used to describe non-pipelined division.
(define_cpu_unit "ppc8540_miu_div" "ppc8540_long") (define_cpu_unit "ppc8540_mu_div" "ppc8540_long")
;; Here we simplified LSU unit description not describing the stages. ;; Here we simplified LSU unit description not describing the stages.
(define_cpu_unit "ppc8540_lsu" "ppc8540_most") (define_cpu_unit "ppc8540_lsu" "ppc8540_most")
...@@ -58,13 +65,13 @@ ...@@ -58,13 +65,13 @@
(define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most") (define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most")
(define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most") (define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most")
(define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire") (define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire")
(define_cpu_unit "present_ppc8540_siu0_stage0" "ppc8540_most") (define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most")
;; The following sets to make automata deterministic when option ndfa is used. ;; The following sets to make automata deterministic when option ndfa is used.
(presence_set "present_ppc8540_decode_0" "ppc8540_decode_0") (presence_set "present_ppc8540_decode_0" "ppc8540_decode_0")
(presence_set "present_ppc8540_issue_0" "ppc8540_issue_0") (presence_set "present_ppc8540_issue_0" "ppc8540_issue_0")
(presence_set "present_ppc8540_retire_0" "ppc8540_retire_0") (presence_set "present_ppc8540_retire_0" "ppc8540_retire_0")
(presence_set "present_ppc8540_siu0_stage0" "ppc8540_siu0_stage0") (presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0")
;; Some useful abbreviations. ;; Some useful abbreviations.
(define_reservation "ppc8540_decode" (define_reservation "ppc8540_decode"
...@@ -73,153 +80,156 @@ ...@@ -73,153 +80,156 @@
"ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0") "ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0")
(define_reservation "ppc8540_retire" (define_reservation "ppc8540_retire"
"ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0") "ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0")
(define_reservation "ppc8540_siu_stage0" (define_reservation "ppc8540_su_stage0"
"ppc8540_siu0_stage0|ppc8540_siu1_stage0+present_ppc8540_siu0_stage0") "ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0")
;; Simple SIU insns ;; Simple SU insns
(define_insn_reservation "ppc8540_siu" 1 (define_insn_reservation "ppc8540_su" 1
(and (eq_attr "type" "integer,cmp,compare,delayed_compare,fast_compare") (and (eq_attr "type" "integer,cmp,compare,delayed_compare,fast_compare")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Branch. Actually this latency time is not used by the scheduler. ;; Branch. Actually this latency time is not used by the scheduler.
(define_insn_reservation "ppc8540_branch" 1 (define_insn_reservation "ppc8540_branch" 1
(and (eq_attr "type" "jmpreg,branch") (and (eq_attr "type" "jmpreg,branch")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_bu+ppc8540_retire") "ppc8540_decode,ppc8540_bu,ppc8540_retire")
;; Multiply ;; Multiply
(define_insn_reservation "ppc8540_multiply" 4 (define_insn_reservation "ppc8540_multiply" 4
(and (eq_attr "type" "imul,imul2,imul3,imul_compare") (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\ "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_miu_stage2,ppc8540_miu_stage3,ppc8540_retire") ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; Divide. We use the average latency time here. We omit reserving a ;; Divide. We use the average latency time here. We omit reserving a
;; retire unit because of the result automata will be huge. ;; retire unit because of the result automata will be huge. We ignore
;; reservation of miu_stage3 here because we use the average latency
;; time.
(define_insn_reservation "ppc8540_divide" 14 (define_insn_reservation "ppc8540_divide" 14
(and (eq_attr "type" "idiv") (and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\ "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_miu_div*13") ppc8540_mu_div*13")
;; CR logical ;; CR logical
(define_insn_reservation "ppc8540_cr_logical" 1 (define_insn_reservation "ppc8540_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr") (and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_bu+ppc8540_retire") "ppc8540_decode,ppc8540_bu,ppc8540_retire")
;; Mfcr ;; Mfcr
(define_insn_reservation "ppc8540_mfcr" 1 (define_insn_reservation "ppc8540_mfcr" 1
(and (eq_attr "type" "mfcr") (and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_siu1_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Mtcrf ;; Mtcrf
(define_insn_reservation "ppc8540_mtcrf" 1 (define_insn_reservation "ppc8540_mtcrf" 1
(and (eq_attr "type" "mtcr") (and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_siu1_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Mtjmpr ;; Mtjmpr
(define_insn_reservation "ppc8540_mtjmpr" 1 (define_insn_reservation "ppc8540_mtjmpr" 1
(and (eq_attr "type" "mtjmpr") (and (eq_attr "type" "mtjmpr")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_siu_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Loads ;; Loads
(define_insn_reservation "ppc8540_load" 3 (define_insn_reservation "ppc8540_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Stores. ;; Stores.
(define_insn_reservation "ppc8540_store" 3 (define_insn_reservation "ppc8540_store" 3
(and (eq_attr "type" "store,store_ux,store_u") (and (eq_attr "type" "store,store_ux,store_u")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Simple FP ;; Simple FP
(define_insn_reservation "ppc8540_simple_float" 1 (define_insn_reservation "ppc8540_simple_float" 1
(and (eq_attr "type" "fpsimple") (and (eq_attr "type" "fpsimple")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; FP ;; FP
(define_insn_reservation "ppc8540_float" 4 (define_insn_reservation "ppc8540_float" 4
(and (eq_attr "type" "fp") (and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\ "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire") ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; float divides. We omit reserving a retire unit because of the ;; float divides. We omit reserving a retire unit and miu_stage3
;; result automata will be huge. ;; because of the result automata will be huge.
(define_insn_reservation "ppc8540_float_vector_divide" 29 (define_insn_reservation "ppc8540_float_vector_divide" 29
(and (eq_attr "type" "vecfdiv") (and (eq_attr "type" "vecfdiv")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\ "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_miu_div*28") ppc8540_mu_div*28")
;; Brinc ;; Brinc
(define_insn_reservation "ppc8540_brinc" 1 (define_insn_reservation "ppc8540_brinc" 1
(and (eq_attr "type" "brinc") (and (eq_attr "type" "brinc")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Simple vector ;; Simple vector
(define_insn_reservation "ppc8540_simple_vector" 1 (define_insn_reservation "ppc8540_simple_vector" 1
(and (eq_attr "type" "vecsimple") (and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Simple vector compare ;; Simple vector compare
(define_insn_reservation "ppc8540_simple_vector_compare" 1 (define_insn_reservation "ppc8540_simple_vector_compare" 1
(and (eq_attr "type" "veccmpsimple") (and (eq_attr "type" "veccmpsimple")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_siu_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Vector compare ;; Vector compare
(define_insn_reservation "ppc8540_vector_compare" 1 (define_insn_reservation "ppc8540_vector_compare" 1
(and (eq_attr "type" "veccmp") (and (eq_attr "type" "veccmp")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; evsplatfi evsplati ;; evsplatfi evsplati
(define_insn_reservation "ppc8540_vector_perm" 1 (define_insn_reservation "ppc8540_vector_perm" 1
(and (eq_attr "type" "vecperm") (and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_siu1_stage0+ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Vector float ;; Vector float
(define_insn_reservation "ppc8540_float_vector" 4 (define_insn_reservation "ppc8540_float_vector" 4
(and (eq_attr "type" "vecfloat") (and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\ "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire") ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; Vector divides: Use the average. We omit reserving a retire unit ;; Vector divides: Use the average. We omit reserving a retire unit
;; because of the result automata will be huge. ;; because of the result automata will be huge. We ignore reservation
;; of miu_stage3 here because we use the average latency time.
(define_insn_reservation "ppc8540_vector_divide" 14 (define_insn_reservation "ppc8540_vector_divide" 14
(and (eq_attr "type" "vecdiv") (and (eq_attr "type" "vecdiv")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0+ppc8540_miu_div,\ "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_miu_div*13") ppc8540_mu_div*13")
;; Complex vector. ;; Complex vector.
(define_insn_reservation "ppc8540_complex_vector" 4 (define_insn_reservation "ppc8540_complex_vector" 4
(and (eq_attr "type" "veccomplex") (and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_miu_stage0,ppc8540_miu_stage1,\ "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_miu_stage2,ppc8540_miu_stage3+ppc8540_retire") ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; Vector load ;; Vector load
(define_insn_reservation "ppc8540_vector_load" 3 (define_insn_reservation "ppc8540_vector_load" 3
(and (eq_attr "type" "vecload") (and (eq_attr "type" "vecload")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Vector store ;; Vector store
(define_insn_reservation "ppc8540_vector_store" 3 (define_insn_reservation "ppc8540_vector_store" 3
(and (eq_attr "type" "vecstore") (and (eq_attr "type" "vecstore")
(eq_attr "cpu" "ppc8540")) (eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing*2,ppc8540_retire") "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
gcc/config/rs6000/rs6000.c
...@@ -241,6 +241,7 @@ static bool rs6000_rtx_costs PARAMS ((rtx, int, int, int *)); ...@@ -241,6 +241,7 @@ static bool rs6000_rtx_costs PARAMS ((rtx, int, int, int *));
static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
static int rs6000_adjust_priority PARAMS ((rtx, int)); static int rs6000_adjust_priority PARAMS ((rtx, int));
static int rs6000_issue_rate PARAMS ((void)); static int rs6000_issue_rate PARAMS ((void));
static int rs6000_use_sched_lookahead PARAMS ((void));
static void rs6000_init_builtins PARAMS ((void)); static void rs6000_init_builtins PARAMS ((void));
static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx));
...@@ -407,6 +408,9 @@ static const char alt_reg_names[][8] = ...@@ -407,6 +408,9 @@ static const char alt_reg_names[][8] =
#undef TARGET_SCHED_ADJUST_PRIORITY #undef TARGET_SCHED_ADJUST_PRIORITY
#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
#undef TARGET_INIT_BUILTINS #undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS rs6000_init_builtins #define TARGET_INIT_BUILTINS rs6000_init_builtins
...@@ -12661,6 +12665,7 @@ rs6000_issue_rate () ...@@ -12661,6 +12665,7 @@ rs6000_issue_rate ()
case CPU_PPC603: case CPU_PPC603:
case CPU_PPC750: case CPU_PPC750:
case CPU_PPC7400: case CPU_PPC7400:
case CPU_PPC8540:
return 2; return 2;
case CPU_RIOS2: case CPU_RIOS2:
case CPU_PPC604: case CPU_PPC604:
...@@ -12674,6 +12679,17 @@ rs6000_issue_rate () ...@@ -12674,6 +12679,17 @@ rs6000_issue_rate ()
} }
} }
/* Return how many instructions to look ahead for better insn
scheduling. */
static int
rs6000_use_sched_lookahead ()
{
if (rs6000_cpu_attr == CPU_PPC8540)
return 4;
return 0;
}
/* Length in units of the trampoline for entering a nested function. */ /* Length in units of the trampoline for entering a nested function. */
......
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